Commit ff0649f8 authored by Mauro Rossi's avatar Mauro Rossi Committed by Alex Deucher
Browse files

drm/amd/display: dce_hwseq: add DCE6 specific macros,functions 



[Why]
DCE6 has no BLND_CONTROL register for Blender HW programming
DCE6 has no BLND_V_UPDATE_LOCK register for Pipe Locking

[How]
Add DCE6 specific macros definitions for HWSEQ registers and masks
DCE6 HWSEQ macros will avoid buiding errors when using DCE6 headers
Add dce60_pipe_control_lock() stub with no op

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMauro Rossi <issor.oruam@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eab5a799

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c

+9 −0
Original line number Diff line number Diff line
@@ -85,6 +85,15 @@ void dce_pipe_control_lock(struct dc *dc, 
	}

}



#if defined(CONFIG_DRM_AMD_DC_SI)

void dce60_pipe_control_lock(struct dc *dc,

		struct pipe_ctx *pipe,

		bool lock)

{

	/* DCE6 has no BLND_V_UPDATE_LOCK register */

}

#endif



void dce_set_blender_mode(struct dce_hwseq *hws,

	unsigned int blnd_inst,

	enum blnd_mode mode)

drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h

+18 −0
Original line number Diff line number Diff line
@@ -110,6 +110,12 @@ 
	SR(BLNDV_CONTROL),\

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)



#if defined(CONFIG_DRM_AMD_DC_SI)

#define HWSEQ_DCE6_REG_LIST() \

	HWSEQ_DCEF_REG_LIST_DCE8(), \

	HWSEQ_PIXEL_RATE_REG_LIST(CRTC)

#endif



#define HWSEQ_DCE8_REG_LIST() \

	HWSEQ_DCEF_REG_LIST_DCE8(), \

	HWSEQ_BLND_REG_LIST(), \
@@ -488,6 +494,12 @@ struct dce_hwseq_registers { 
	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\

	HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh)



#if defined(CONFIG_DRM_AMD_DC_SI)

#define HWSEQ_DCE6_MASK_SH_LIST(mask_sh)\

	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \

	HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_)

#endif



#define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\

	.DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \

	HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\
@@ -836,6 +848,12 @@ void dce_pipe_control_lock(struct dc *dc, 
void dce_set_blender_mode(struct dce_hwseq *hws,

	unsigned int blnd_inst, enum blnd_mode mode);



#if defined(CONFIG_DRM_AMD_DC_SI)

void dce60_pipe_control_lock(struct dc *dc,

		struct pipe_ctx *pipe,

		bool lock);

#endif



void dce_clock_gating_power_up(struct dce_hwseq *hws,

		bool enable);