Commit ff3aeb34 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/dg2: Add Wa_18018781329 



A few more MOD registers need to be programmed on DG2.

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220120234147.1200574-1-matthew.d.roper@intel.com


Reviewed-by: default avatarSwathi Dhanavanthri <swathi.dhanavanthri@intel.com>
parent 70b42b58

drivers/gpu/drm/i915/gt/intel_workarounds.c

+6 −0
Original line number Diff line number Diff line
@@ -1508,6 +1508,12 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
	 */

	wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);

	wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);



	/* Wa_18018781329:dg2 */

	wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);

	wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);

	wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);

	wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);

}



static void

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -511,6 +511,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   TAG_BLOCK_CLKGATE_DIS		REG_BIT(7)









#define GEN12_MERT_MOD_CTRL		_MMIO(0xcf28)









#define RENDER_MOD_CTRL			_MMIO(0xcf2c)









#define COMP_MOD_CTRL			_MMIO(0xcf30)









#define VDBX_MOD_CTRL			_MMIO(0xcf34)









#define VEBX_MOD_CTRL			_MMIO(0xcf38)









#define   FORCE_MISS_FTLB		REG_BIT(3)

















#define GAB_CTL				_MMIO(0x24000)