Commit ff4b6bf7 authored by Conor Dooley's avatar Conor Dooley
Browse files

riscv: dts: microchip: add can resets to mpfs 



The can IP on PolarFire SoC requires the use of the blocks reset
during normal operation, and the property is therefore required by the
binding, causing a warning on the m100pfsevp board where it is default
enabled:
mpfs-m100pfsevp.dtb: can@2010c000 (microchip,mpfs-can): 'resets' is a required property
Add the reset to both can nodes.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 5a741f8c

arch/riscv/boot/dts/microchip/mpfs.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -425,6 +425,7 @@ can0: can@2010c000 { 
			clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>;

			interrupt-parent = <&plic>;

			interrupts = <56>;

			resets = <&mss_top_sysreg CLK_CAN0>;

			status = "disabled";

		};
@@ -434,6 +435,7 @@ can1: can@2010d000 { 
			clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>;

			interrupt-parent = <&plic>;

			interrupts = <57>;

			resets = <&mss_top_sysreg CLK_CAN1>;

			status = "disabled";

		};