Commit ff568d62 authored by Ankit Nautiyal's avatar Ankit Nautiyal
Browse files

drm/i915/display: Maintain asciibetical order for HAS_* macros 



Move HAS_* macros to maintain asciibetical order.

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250312054424.1628358-1-ankit.k.nautiyal@intel.com
parent 4051c59e

drivers/gpu/drm/i915/display/intel_display_device.h

+4 −4
Original line number Diff line number Diff line
@@ -143,9 +143,11 @@ struct intel_display_platforms { 


#define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)

#define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)

#define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)

#define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))

#define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)

#define HAS_CDCLK_SQUASH(__display)	(DISPLAY_INFO(__display)->has_cdclk_squash)

#define HAS_CMRR(__display)		(DISPLAY_VER(__display) >= 20)

#define HAS_CMTG(__display)		(!(__display)->platform.dg2 && DISPLAY_VER(__display) >= 13)

#define HAS_CUR_FBC(__display)		(!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))

#define HAS_D12_PLANE_MINIMIZATION(__display)	((__display)->platform.rocketlake || (__display)->platform.alderlake_s)
@@ -156,9 +158,9 @@ struct intel_display_platforms { 
#define HAS_DMC_WAKELOCK(__display)	(DISPLAY_VER(__display) >= 20)

#define HAS_DOUBLE_BUFFERED_M_N(__display)	(DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell)

#define HAS_DOUBLE_WIDE(__display)	(DISPLAY_VER(__display) < 4)

#define HAS_DP_MST(__display)		(DISPLAY_INFO(__display)->has_dp_mst)

#define HAS_DP20(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)

#define HAS_DPT(__display)		(DISPLAY_VER(__display) >= 13)

#define HAS_DP_MST(__display)		(DISPLAY_INFO(__display)->has_dp_mst)

#define HAS_DSB(__display)		(DISPLAY_INFO(__display)->has_dsb)

#define HAS_DSC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dsc)

#define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
@@ -166,8 +168,8 @@ struct intel_display_platforms { 
#define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)

#define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)

#define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)

#define HAS_GMBUS_IRQ(__display)	(DISPLAY_VER(__display) >= 4)

#define HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)

#define HAS_GMBUS_IRQ(__display)	(DISPLAY_VER(__display) >= 4)

#define HAS_GMCH(__display)		(DISPLAY_INFO(__display)->has_gmch)

#define HAS_HW_SAGV_WM(__display)	(DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx)

#define HAS_IPC(__display)		(DISPLAY_INFO(__display)->has_ipc)
@@ -189,8 +191,6 @@ struct intel_display_platforms { 
					  ((__display)->platform.dgfx && DISPLAY_VER(__display) == 14)) && \

					 HAS_DSC(__display))

#define HAS_VRR(__display)		(DISPLAY_VER(__display) >= 11)

#define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)

#define HAS_CMRR(__display)		(DISPLAY_VER(__display) >= 20)

#define INTEL_NUM_PIPES(__display)	(hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask))

#define I915_HAS_HOTPLUG(__display)	(DISPLAY_INFO(__display)->has_hotplug)

#define OVERLAY_NEEDS_PHYSICAL(__display)	(DISPLAY_INFO(__display)->overlay_needs_physical)