Commit ff7a6de0 authored by Akhil P Oommen's avatar Akhil P Oommen Committed by Rob Clark
Browse files

drm/msm/a6xx: Fix the gemnoc workaround 



Correct the register offset and enable this workaround for all A7x
and newer GPUs to match the recommendation. Also, downstream does this
w/a after moving the fence to allow mode. So do the same.

Fixes: dbfbb376 ("drm/msm/a6xx: Add A621 support")
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: default avatarAkhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688997/


Message-ID: <20251118-kaana-gpu-support-v4-3-86eeb8e93fb6@oss.qualcomm.com>
Signed-off-by: default avatarRob Clark <robin.clark@oss.qualcomm.com>
parent 180349b8

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+4 −4
Original line number Diff line number Diff line
@@ -511,8 +511,9 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) 
	 * in the power down sequence not being fully executed. That in turn can

	 * prevent CX_GDSC from collapsing. Assert Qactive to avoid this.

	 */

	if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu))

		gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0));

	if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) ||

				adreno_is_7c3(adreno_gpu)))

		gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0));

}



/* Let the GMU know that we are about to go into slumber */
@@ -548,10 +549,9 @@ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) 
	}



out:

	a6xx_gemnoc_workaround(gmu);



	/* Put fence into allow mode */

	gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);

	a6xx_gemnoc_workaround(gmu);

	return ret;

}