Commit ff898623 authored by Jim Mattson's avatar Jim Mattson Committed by Borislav Petkov (AMD)
Browse files

x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET 



AMD's initial implementation of IBPB did not clear the return address
predictor. Beginning with Zen4, AMD's IBPB *does* clear the return address
predictor. This behavior is enumerated by CPUID.80000008H:EBX.IBPB_RET[30].

Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID,
when determining cross-vendor capabilities.

Suggested-by: default avatarVenkatesh Srinivas <venkateshs@chromium.org>
Signed-off-by: default avatarJim Mattson <jmattson@google.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: <stable@kernel.org>
parent 8cf0b939

arch/x86/include/asm/cpufeatures.h

+2 −1
Original line number Diff line number Diff line
@@ -215,7 +215,7 @@ 
#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* Disable Speculative Store Bypass. */

#define X86_FEATURE_LS_CFG_SSBD		( 7*32+24)  /* AMD SSBD implementation via LS_CFG MSR */

#define X86_FEATURE_IBRS		( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */

#define X86_FEATURE_IBPB		( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */

#define X86_FEATURE_IBPB		( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */

#define X86_FEATURE_STIBP		( 7*32+27) /* "stibp" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ZEN			( 7*32+28) /* Generic flag for all Zen and newer */

#define X86_FEATURE_L1TF_PTEINV		( 7*32+29) /* L1TF workaround PTE inversion */
@@ -348,6 +348,7 @@ 
#define X86_FEATURE_CPPC		(13*32+27) /* "cppc" Collaborative Processor Performance Control */

#define X86_FEATURE_AMD_PSFD            (13*32+28) /* Predictive Store Forwarding Disable */

#define X86_FEATURE_BTC_NO		(13*32+29) /* Not vulnerable to Branch Type Confusion */

#define X86_FEATURE_AMD_IBPB_RET	(13*32+30) /* IBPB clears return address predictor */

#define X86_FEATURE_BRS			(13*32+31) /* "brs" Branch Sampling available */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */