Commit ff987ffc authored by Marc Zyngier's avatar Marc Zyngier
Browse files

KVM: arm64: nv: Add support for FEAT_ATS1A 



Handling FEAT_ATS1A (which provides the AT S1E{1,2}A instructions)
is pretty easy, as it is just the usual AT without the permission
check.

This basically amounts to plumbing the instructions in the various
dispatch tables, and handling FEAT_ATS1A being disabled in the
ID registers.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 8df747f4

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -673,6 +673,7 @@ 
#define OP_AT_S12E1W	sys_insn(AT_Op0, 4, AT_CRn, 8, 5)

#define OP_AT_S12E0R	sys_insn(AT_Op0, 4, AT_CRn, 8, 6)

#define OP_AT_S12E0W	sys_insn(AT_Op0, 4, AT_CRn, 8, 7)

#define OP_AT_S1E2A	sys_insn(AT_Op0, 4, AT_CRn, 9, 2)



/* TLBI instructions */

#define TLBI_Op0	1

arch/arm64/kvm/at.c

+10 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ static enum trans_regime compute_translation_regime(struct kvm_vcpu *vcpu, u32 o 
	switch (op) {

	case OP_AT_S1E2R:

	case OP_AT_S1E2W:

	case OP_AT_S1E2A:

		return vcpu_el2_e2h_is_set(vcpu) ? TR_EL20 : TR_EL2;

		break;

	default:
@@ -852,6 +853,9 @@ static u64 handle_at_slow(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) 
	case OP_AT_S1E0W:

		perm_fail = !uw;

		break;

	case OP_AT_S1E1A:

	case OP_AT_S1E2A:

		break;

	default:

		BUG();

	}
@@ -935,6 +939,9 @@ static u64 __kvm_at_s1e01_fast(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) 
	case OP_AT_S1E0W:

		fail = __kvm_at(OP_AT_S1E0W, vaddr);

		break;

	case OP_AT_S1E1A:

		fail = __kvm_at(OP_AT_S1E1A, vaddr);

		break;

	default:

		WARN_ON_ONCE(1);

		fail = true;
@@ -1010,6 +1017,9 @@ void __kvm_at_s1e2(struct kvm_vcpu *vcpu, u32 op, u64 vaddr) 
		case OP_AT_S1E2W:

			fail = __kvm_at(OP_AT_S1E1W, vaddr);

			break;

		case OP_AT_S1E2A:

			fail = __kvm_at(OP_AT_S1E1A, vaddr);

			break;

		default:

			WARN_ON_ONCE(1);

			fail = true;

arch/arm64/kvm/emulate-nested.c

+2 −0
Original line number Diff line number Diff line
@@ -786,6 +786,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 
	SR_TRAP(OP_AT_S12E1W,		CGT_HCR_NV),

	SR_TRAP(OP_AT_S12E0R,		CGT_HCR_NV),

	SR_TRAP(OP_AT_S12E0W,		CGT_HCR_NV),

	SR_TRAP(OP_AT_S1E2A,		CGT_HCR_NV),

	SR_TRAP(OP_TLBI_IPAS2E1,	CGT_HCR_NV),

	SR_TRAP(OP_TLBI_RIPAS2E1,	CGT_HCR_NV),

	SR_TRAP(OP_TLBI_IPAS2LE1,	CGT_HCR_NV),
@@ -867,6 +868,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { 
	SR_TRAP(OP_AT_S1E0W, 		CGT_HCR_AT),

	SR_TRAP(OP_AT_S1E1RP, 		CGT_HCR_AT),

	SR_TRAP(OP_AT_S1E1WP, 		CGT_HCR_AT),

	SR_TRAP(OP_AT_S1E1A,		CGT_HCR_AT),

	SR_TRAP(SYS_ERXPFGF_EL1,	CGT_HCR_nFIEN),

	SR_TRAP(SYS_ERXPFGCTL_EL1,	CGT_HCR_nFIEN),

	SR_TRAP(SYS_ERXPFGCDN_EL1,	CGT_HCR_nFIEN),

arch/arm64/kvm/sys_regs.c

+11 −0
Original line number Diff line number Diff line
@@ -2818,6 +2818,13 @@ static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 
{

	u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);



	/* There is no FGT associated with AT S1E2A :-( */

	if (op == OP_AT_S1E2A &&

	    !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) {

		kvm_inject_undefined(vcpu);

		return false;

	}



	__kvm_at_s1e2(vcpu, op, p->regval);



	return true;
@@ -3188,6 +3195,7 @@ static struct sys_reg_desc sys_insn_descs[] = { 
	SYS_INSN(AT_S12E1W, handle_at_s12),

	SYS_INSN(AT_S12E0R, handle_at_s12),

	SYS_INSN(AT_S12E0W, handle_at_s12),

	SYS_INSN(AT_S1E2A, handle_at_s1e2),



	SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is),

	SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is),
@@ -4645,6 +4653,9 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu) 
						HFGITR_EL2_TLBIRVAAE1OS	|

						HFGITR_EL2_TLBIRVAE1OS);



	if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP))

		kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A;



	if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2))

		kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP |

						HFGITR_EL2_ATS1E1WP);