Commit ffa7119c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mmc-v6.17-rc2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc 

Pull MMC host fixes from Ulf Hansson:

 - mvsdio: Fix dma_unmap_sg() nents value

 - sdhci: Fix clock management for UHS-II

 - sdhci-pci-gli: Fix initialization of UHS-II for GL9767

* tag 'mmc-v6.17-rc2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc:
  mmc: sdhci-pci-gli: GL9767: Fix initializing the UHS-II interface during a power-on
  mmc: sdhci-uhs2: Fix calling incorrect sdhci_set_clock() function
  mmc: sdhci: Move the code related to setting the clock from sdhci_set_ios_common() into sdhci_set_ios()
  mmc: mvsdio: Fix dma_unmap_sg() nents value
parents 46d2affd 77a436c9

drivers/mmc/host/mvsdio.c

+1 −1
Original line number Diff line number Diff line
@@ -292,7 +292,7 @@ static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data, 
		host->pio_ptr = NULL;

		host->pio_size = 0;

	} else {

		dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,

		dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,

			     mmc_get_dma_dir(data));

	}

drivers/mmc/host/sdhci-pci-gli.c

+67 −1
Original line number Diff line number Diff line
@@ -283,6 +283,8 @@ 
#define   PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE	  0xb

#define   PCIE_GLI_9767_UHS2_CTL2_ZC_CTL	  BIT(6)

#define   PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE	  0x1

#define   PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN	BIT(13)

#define   PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE	BIT(14)



#define GLI_MAX_TUNING_LOOP 40
@@ -1179,6 +1181,65 @@ static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable) 
	gl9767_vhs_read(pdev);

}



static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert)

{

	struct sdhci_pci_slot *slot = sdhci_priv(host);

	struct pci_dev *pdev = slot->chip->pdev;

	u32 value, set, clr;



	if (assert) {

		/* Assert reset, set RESETN and clean RESETN_VALUE */

		set = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;

		clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;

	} else {

		/* De-assert reset, clean RESETN and set RESETN_VALUE */

		set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;

		clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;

	}



	gl9767_vhs_write(pdev);

	pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);

	value |= set;

	pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);

	value &= ~clr;

	pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);

	gl9767_vhs_read(pdev);

}



static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd)

{

	u8 pwr = 0;



	if (mode != MMC_POWER_OFF) {

		pwr = sdhci_get_vdd_value(vdd);

		if (!pwr)

			WARN(1, "%s: Invalid vdd %#x\n",

			     mmc_hostname(host->mmc), vdd);

		pwr |= SDHCI_VDD2_POWER_180;

	}



	if (host->pwr == pwr)

		return;



	host->pwr = pwr;



	if (pwr == 0) {

		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);

	} else {

		sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);



		pwr |= SDHCI_POWER_ON;

		sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);

		usleep_range(5000, 6250);



		/* Assert reset */

		sdhci_gl9767_uhs2_phy_reset(host, true);

		pwr |= SDHCI_VDD2_POWER_ON;

		sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);

		usleep_range(5000, 6250);

	}

}



static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)

{

	struct sdhci_pci_slot *slot = sdhci_priv(host);
@@ -1205,6 +1266,11 @@ static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) 
	}



	sdhci_enable_clk(host, clk);



	if (mmc_card_uhs2(host->mmc))

		/* De-assert reset */

		sdhci_gl9767_uhs2_phy_reset(host, false);



	gl9767_set_low_power_negotiation(pdev, true);

}
@@ -1476,7 +1542,7 @@ static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode, 
		gl9767_vhs_read(pdev);



		sdhci_gli_overcurrent_event_enable(host, false);

		sdhci_uhs2_set_power(host, mode, vdd);

		__gl9767_uhs2_set_power(host, mode, vdd);

		sdhci_gli_overcurrent_event_enable(host, true);

	} else {

		gl9767_vhs_write(pdev);

drivers/mmc/host/sdhci-uhs2.c

+2 −1
Original line number Diff line number Diff line
@@ -295,7 +295,8 @@ static void __sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 
	else

		sdhci_uhs2_set_power(host, ios->power_mode, ios->vdd);



	sdhci_set_clock(host, host->clock);

	host->ops->set_clock(host, ios->clock);

	host->clock = ios->clock;

}



static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)

drivers/mmc/host/sdhci.c

+17 −17
Original line number Diff line number Diff line
@@ -2367,23 +2367,6 @@ void sdhci_set_ios_common(struct mmc_host *mmc, struct mmc_ios *ios) 
		(ios->power_mode == MMC_POWER_UP) &&

		!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))

		sdhci_enable_preset_value(host, false);



	if (!ios->clock || ios->clock != host->clock) {

		host->ops->set_clock(host, ios->clock);

		host->clock = ios->clock;



		if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&

		    host->clock) {

			host->timeout_clk = mmc->actual_clock ?

						mmc->actual_clock / 1000 :

						host->clock / 1000;

			mmc->max_busy_timeout =

				host->ops->get_max_timeout_count ?

				host->ops->get_max_timeout_count(host) :

				1 << 27;

			mmc->max_busy_timeout /= host->timeout_clk;

		}

	}

}

EXPORT_SYMBOL_GPL(sdhci_set_ios_common);
@@ -2410,6 +2393,23 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 


	sdhci_set_ios_common(mmc, ios);



	if (!ios->clock || ios->clock != host->clock) {

		host->ops->set_clock(host, ios->clock);

		host->clock = ios->clock;



		if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&

		    host->clock) {

			host->timeout_clk = mmc->actual_clock ?

						mmc->actual_clock / 1000 :

						host->clock / 1000;

			mmc->max_busy_timeout =

				host->ops->get_max_timeout_count ?

				host->ops->get_max_timeout_count(host) :

				1 << 27;

			mmc->max_busy_timeout /= host->timeout_clk;

		}

	}



	if (host->ops->set_power)

		host->ops->set_power(host, ios->power_mode, ios->vdd);

	else