Commit ffc011b6 authored Jun 11, 2021 by Linus Walleij

ARM: dts: ux500: Tag Janice display SPI correct



The s6e63m0 display used "type 3" SPI communication so
flag the device as using negative clocking and polarity
on the SPI bus.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

parent 6880fa6c

arch/arm/boot/dts/ste-ux500-samsung-janice.dts

+3 −0

Original line number	Diff line number	Diff line
		@@ -266,6 +266,9 @@ panel@0 {
		pinctrl-names = "default";
		pinctrl-0 = <&panel_default_mode>;
		spi-3wire;
		/* TYPE 3: inverse clock polarity and phase */
		spi-cpha;
		spi-cpol;

		port {
		panel_in: endpoint {