Commit ffd99396 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2024-10-28' of https://gitlab.freedesktop.org/drm/msm into drm-next 



Updates for v6.13

Core:
- Switch to aperture_remove_all_conflicting_devices()
- Simplify msm_disp_state_dump_regs()

DPU:
- Add SA8775P support
- Add (disabled by default) MSM8917, MSM8937, MSM8953 and MSM8996
  support
- Enable support for larger framebuffers (required for X.Org working
  with several outputs)
- Dropped LM_3, LM_4 (MSM8998, SDM845)
- Fixed DSPP_3 routing on SDM845

DP:
- Add SA8775P support

HDMI:
- Mark two arrays as const in MSM8998 HDMI PHY driver

GPU:
- a7xx preemption support
- Adreno A663 support
- Typos fixes, etc
- Fix excessive stack usage in a6xx GMU

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGt7k8zDHsg2Uzx9apzyQMut8XdLXMQSRNn7WArdPUV5Qw@mail.gmail.com
parents 30169bb6 d6d1ad32

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

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Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ properties: 
  compatible:

    oneOf:

      - enum:

          - qcom,sa8775p-dp

          - qcom,sc7180-dp

          - qcom,sc7280-dp

          - qcom,sc7280-edp

Documentation/devicetree/bindings/display/msm/gmu.yaml

+1 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ allOf: 
            enum:

              - qcom,adreno-gmu-635.0

              - qcom,adreno-gmu-660.1

              - qcom,adreno-gmu-663.0

    then:

      properties:

        reg:

Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml

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+241 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,sa8775p-mdss.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. SA87755P Display MDSS



maintainers:

  - Mahadevan <quic_mahap@quicinc.com>



description:

  SA8775P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like

  DPU display controller, DP interfaces and EDP etc.



$ref: /schemas/display/msm/mdss-common.yaml#



properties:

  compatible:

    const: qcom,sa8775p-mdss



  clocks:

    items:

      - description: Display AHB

      - description: Display hf AXI

      - description: Display core



  iommus:

    maxItems: 1



  interconnects:

    maxItems: 3



  interconnect-names:

    maxItems: 3



patternProperties:

  "^display-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true



    properties:

      compatible:

        const: qcom,sa8775p-dpu



  "^displayport-controller@[0-9a-f]+$":

    type: object

    additionalProperties: true



    properties:

      compatible:

        items:

          - const: qcom,sa8775p-dp



required:

  - compatible



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interconnect/qcom,icc.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>

    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-subsystem@ae00000 {

        compatible = "qcom,sa8775p-mdss";

        reg = <0x0ae00000 0x1000>;

        reg-names = "mdss";



        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,

                        <&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,

                        <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>;

        interconnect-names = "mdp0-mem",

                             "mdp1-mem",

                             "cpu-cfg";





        resets = <&dispcc_core_bcr>;

        power-domains = <&dispcc_gdsc>;



        clocks = <&dispcc_ahb_clk>,

                 <&gcc GCC_DISP_HF_AXI_CLK>,

                 <&dispcc_mdp_clk>;



        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

        interrupt-controller;

        #interrupt-cells = <1>;



        iommus = <&apps_smmu 0x1000 0x402>;



        #address-cells = <1>;

        #size-cells = <1>;

        ranges;



        display-controller@ae01000 {

            compatible = "qcom,sa8775p-dpu";

            reg = <0x0ae01000 0x8f000>,

                  <0x0aeb0000 0x2008>;

            reg-names = "mdp", "vbif";



            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                     <&dispcc_ahb_clk>,

                     <&dispcc_mdp_lut_clk>,

                     <&dispcc_mdp_clk>,

                     <&dispcc_mdp_vsync_clk>;

            clock-names = "nrt_bus",

                          "iface",

                          "lut",

                          "core",

                          "vsync";



            assigned-clocks = <&dispcc_mdp_vsync_clk>;

            assigned-clock-rates = <19200000>;



            operating-points-v2 = <&mdss0_mdp_opp_table>;

            power-domains = <&rpmhpd RPMHPD_MMCX>;



            interrupt-parent = <&mdss0>;

            interrupts = <0>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;

                    dpu_intf0_out: endpoint {

                         remote-endpoint = <&mdss0_dp0_in>;

                    };

                };

            };



            mdss0_mdp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-375000000 {

                    opp-hz = /bits/ 64 <375000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };



                opp-500000000 {

                    opp-hz = /bits/ 64 <500000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };



                opp-575000000 {

                    opp-hz = /bits/ 64 <575000000>;

                    required-opps = <&rpmhpd_opp_turbo>;

                };



                opp-650000000 {

                    opp-hz = /bits/ 64 <650000000>;

                    required-opps = <&rpmhpd_opp_turbo_l1>;

                };

            };

        };



        displayport-controller@af54000 {

            compatible = "qcom,sa8775p-dp";



            pinctrl-0 = <&dp_hot_plug_det>;

            pinctrl-names = "default";



            reg = <0xaf54000 0x104>,

                  <0xaf54200 0x0c0>,

                  <0xaf55000 0x770>,

                  <0xaf56000 0x09c>;



            interrupt-parent = <&mdss0>;

            interrupts = <12>;



            clocks = <&dispcc_mdss_ahb_clk>,

                     <&dispcc_dptx0_aux_clk>,

                     <&dispcc_dptx0_link_clk>,

                     <&dispcc_dptx0_link_intf_clk>,

                     <&dispcc_dptx0_pixel0_clk>;

            clock-names = "core_iface",

                          "core_aux",

                          "ctrl_link",

                          "ctrl_link_iface",

                          "stream_pixel";



            assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>,

                              <&dispcc_mdss_dptx0_pixel0_clk_src>;

            assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>;



            phys = <&mdss0_edp_phy>;

            phy-names = "dp";



            operating-points-v2 = <&dp_opp_table>;

            power-domains = <&rpmhpd SA8775P_MMCX>;



            #sound-dai-cells = <0>;



            ports {

                #address-cells = <1>;

                #size-cells = <0>;



                port@0 {

                    reg = <0>;

                    mdss0_dp0_in: endpoint {

                        remote-endpoint = <&dpu_intf0_out>;

                    };

                };



                port@1 {

                   reg = <1>;

                   mdss0_dp_out: endpoint { };

                };

            };



            dp_opp_table: opp-table {

                compatible = "operating-points-v2";



                opp-160000000 {

                    opp-hz = /bits/ 64 <160000000>;

                    required-opps = <&rpmhpd_opp_low_svs>;

                };



                opp-270000000 {

                    opp-hz = /bits/ 64 <270000000>;

                    required-opps = <&rpmhpd_opp_svs>;

                };



                opp-540000000 {

                    opp-hz = /bits/ 64 <540000000>;

                    required-opps = <&rpmhpd_opp_svs_l1>;

                };



                opp-810000000 {

                    opp-hz = /bits/ 64 <810000000>;

                    required-opps = <&rpmhpd_opp_nom>;

                };

            };

        };

    };

...

Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml

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@@ -7,13 +7,21 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 
title: Qualcomm Display DPU on SC7280



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

  - Krishna Manikandan <quic_mkrishn@quicinc.com>



$ref: /schemas/display/msm/dpu-common.yaml#



properties:

  compatible:

    const: qcom,sc7280-dpu

    enum:

      - qcom,sc7280-dpu

      - qcom,sc8280xp-dpu

      - qcom,sm8350-dpu

      - qcom,sm8450-dpu

      - qcom,sm8550-dpu



  reg:

    items:

Documentation/devicetree/bindings/display/msm/qcom,sc8280xp-dpu.yaml

deleted100644 → 0
+0 −122
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-dpu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SC8280XP Display Processing Unit



maintainers:

  - Bjorn Andersson <andersson@kernel.org>



description:

  Device tree bindings for SC8280XP Display Processing Unit.



$ref: /schemas/display/msm/dpu-common.yaml#



properties:

  compatible:

    const: qcom,sc8280xp-dpu



  reg:

    items:

      - description: Address offset and size for mdp register set

      - description: Address offset and size for vbif register set



  reg-names:

    items:

      - const: mdp

      - const: vbif



  clocks:

    items:

      - description: Display hf axi clock

      - description: Display sf axi clock

      - description: Display ahb clock

      - description: Display lut clock

      - description: Display core clock

      - description: Display vsync clock



  clock-names:

    items:

      - const: bus

      - const: nrt_bus

      - const: iface

      - const: lut

      - const: core

      - const: vsync



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>

    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interconnect/qcom,sc8280xp.h>

    #include <dt-bindings/power/qcom-rpmpd.h>



    display-controller@ae01000 {

        compatible = "qcom,sc8280xp-dpu";

        reg = <0x0ae01000 0x8f000>,

              <0x0aeb0000 0x2008>;

        reg-names = "mdp", "vbif";



        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,

                 <&gcc GCC_DISP_SF_AXI_CLK>,

                 <&dispcc0 DISP_CC_MDSS_AHB_CLK>,

                 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,

                 <&dispcc0 DISP_CC_MDSS_MDP_CLK>,

                 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;

        clock-names = "bus",

                      "nrt_bus",

                      "iface",

                      "lut",

                      "core",

                      "vsync";



        assigned-clocks = <&dispcc0 DISP_CC_MDSS_MDP_CLK>,

                          <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;

        assigned-clock-rates = <460000000>,

                               <19200000>;



        operating-points-v2 = <&mdp_opp_table>;

        power-domains = <&rpmhpd SC8280XP_MMCX>;



        interrupt-parent = <&mdss0>;

        interrupts = <0>;



        ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                endpoint {

                    remote-endpoint = <&mdss0_dp0_in>;

                };

            };



            port@4 {

                reg = <4>;

                endpoint {

                    remote-endpoint = <&mdss0_dp1_in>;

                };

            };



            port@5 {

                reg = <5>;

                endpoint {

                    remote-endpoint = <&mdss0_dp3_in>;

                };

            };



            port@6 {

                reg = <6>;

                endpoint {

                    remote-endpoint = <&mdss0_dp2_in>;

                };

            };

        };

    };

...