Commit ffdf504c authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull rdma fixes from Jason Gunthorpe:
 "Small bug fixes:

   - Prevent a crash in bnxt if the en and rdma drivers disagree on the
     MSI vectors

   - Have rxe memcpy inline data from the correct address

   - Fix rxe's validation of UD packets

   - Several mlx5 mr cache issues: bad lock balancing on error, missing
     propagation of the ATS property to the HW, wrong bucketing of freed
     mrs in some cases

   - Incorrect goto error unwind in mlx5 driver probe

   - Missed userspace input validation in mlx5 SRQ create

   - Incorrect uABI in MANA rejecting valid optional MR creation flags"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma:
  RDMA/mana_ib: Ignore optional access flags for MRs
  RDMA/mlx5: Add check for srq max_sge attribute
  RDMA/mlx5: Fix unwind flow as part of mlx5_ib_stage_init_init
  RDMA/mlx5: Ensure created mkeys always have a populated rb_key
  RDMA/mlx5: Follow rb_key.ats when creating new mkeys
  RDMA/mlx5: Remove extra unlock on error path
  RDMA/rxe: Fix responder length checking for UD request packets
  RDMA/rxe: Fix data copy for IB_SEND_INLINE
  RDMA/bnxt_re: Fix the max msix vectors macro
parents 4545981f 82a5cc78
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+1 −3
Original line number Diff line number Diff line
@@ -107,8 +107,6 @@ struct bnxt_re_gsi_context {
	struct	bnxt_re_sqp_entries *sqp_tbl;
};

#define BNXT_RE_MIN_MSIX		2
#define BNXT_RE_MAX_MSIX		9
#define BNXT_RE_AEQ_IDX			0
#define BNXT_RE_NQ_IDX			1
#define BNXT_RE_GEN_P5_MAX_VF		64
@@ -168,7 +166,7 @@ struct bnxt_re_dev {
	struct bnxt_qplib_rcfw		rcfw;

	/* NQ */
	struct bnxt_qplib_nq		nq[BNXT_RE_MAX_MSIX];
	struct bnxt_qplib_nq		nq[BNXT_MAX_ROCE_MSIX];

	/* Device Resources */
	struct bnxt_qplib_dev_attr	dev_attr;
+1 −0
Original line number Diff line number Diff line
@@ -112,6 +112,7 @@ struct ib_mr *mana_ib_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 length,
		  "start 0x%llx, iova 0x%llx length 0x%llx access_flags 0x%x",
		  start, iova, length, access_flags);

	access_flags &= ~IB_ACCESS_OPTIONAL;
	if (access_flags & ~VALID_MR_FLAGS)
		return ERR_PTR(-EINVAL);

+2 −2
Original line number Diff line number Diff line
@@ -3759,10 +3759,10 @@ static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
	spin_lock_init(&dev->dm.lock);
	dev->dm.dev = mdev;
	return 0;
err:
	mlx5r_macsec_dealloc_gids(dev);
err_mp:
	mlx5_ib_cleanup_multiport_master(dev);
err:
	mlx5r_macsec_dealloc_gids(dev);
	return err;
}

+4 −4
Original line number Diff line number Diff line
@@ -246,6 +246,7 @@ static void set_cache_mkc(struct mlx5_cache_ent *ent, void *mkc)
	MLX5_SET(mkc, mkc, access_mode_1_0, ent->rb_key.access_mode & 0x3);
	MLX5_SET(mkc, mkc, access_mode_4_2,
		(ent->rb_key.access_mode >> 2) & 0x7);
	MLX5_SET(mkc, mkc, ma_translation_mode, !!ent->rb_key.ats);

	MLX5_SET(mkc, mkc, translations_octword_size,
		 get_mkc_octo_size(ent->rb_key.access_mode,
@@ -641,11 +642,9 @@ static int mlx5_cache_ent_insert(struct mlx5_mkey_cache *cache,
			new = &((*new)->rb_left);
		if (cmp < 0)
			new = &((*new)->rb_right);
		if (cmp == 0) {
			mutex_unlock(&cache->rb_lock);
		if (cmp == 0)
			return -EEXIST;
	}
	}

	/* Add new node and rebalance tree. */
	rb_link_node(&ent->node, parent, new);
@@ -719,6 +718,8 @@ static struct mlx5_ib_mr *_mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
	}
	mr->mmkey.cache_ent = ent;
	mr->mmkey.type = MLX5_MKEY_MR;
	mr->mmkey.rb_key = ent->rb_key;
	mr->mmkey.cacheable = true;
	init_waitqueue_head(&mr->mmkey.wait);
	return mr;
}
@@ -1169,7 +1170,6 @@ static struct mlx5_ib_mr *alloc_cacheable_mr(struct ib_pd *pd,
	mr->ibmr.pd = pd;
	mr->umem = umem;
	mr->page_shift = order_base_2(page_size);
	mr->mmkey.cacheable = true;
	set_mr_fields(dev, mr, umem->length, access_flags, iova);

	return mr;
+8 −5
Original line number Diff line number Diff line
@@ -199,17 +199,20 @@ int mlx5_ib_create_srq(struct ib_srq *ib_srq,
	int err;
	struct mlx5_srq_attr in = {};
	__u32 max_srq_wqes = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
	__u32 max_sge_sz =  MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq) /
			    sizeof(struct mlx5_wqe_data_seg);

	if (init_attr->srq_type != IB_SRQT_BASIC &&
	    init_attr->srq_type != IB_SRQT_XRC &&
	    init_attr->srq_type != IB_SRQT_TM)
		return -EOPNOTSUPP;

	/* Sanity check SRQ size before proceeding */
	if (init_attr->attr.max_wr >= max_srq_wqes) {
		mlx5_ib_dbg(dev, "max_wr %d, cap %d\n",
			    init_attr->attr.max_wr,
			    max_srq_wqes);
	/* Sanity check SRQ and sge size before proceeding */
	if (init_attr->attr.max_wr >= max_srq_wqes ||
	    init_attr->attr.max_sge > max_sge_sz) {
		mlx5_ib_dbg(dev, "max_wr %d,wr_cap %d,max_sge %d, sge_cap:%d\n",
			    init_attr->attr.max_wr, max_srq_wqes,
			    init_attr->attr.max_sge, max_sge_sz);
		return -EINVAL;
	}

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