Commit ffe68b2d authored by Shaoqin Huang's avatar Shaoqin Huang Committed by Marc Zyngier
Browse files

KVM: arm64: Disable fields that KVM doesn't know how to handle in ID_AA64PFR1_EL1 



For some of the fields in the ID_AA64PFR1_EL1 register, KVM doesn't know
how to handle them right now. So explicitly disable them in the register
accessor, then those fields value will be masked to 0 even if on the
hardware the field value is 1. This is safe because from a UAPI point of
view that read_sanitised_ftr_reg() doesn't yet return a nonzero value
for any of those fields.

This will benifit the migration if the host and VM have different values
when restoring a VM.

Those fields include RNDR_trap, NMI, MTE_frac, GCS, THE, MTEX, DF2, PFAR.

Signed-off-by: default avatarShaoqin Huang <shahuang@redhat.com>
Link: https://lore.kernel.org/r/20240723072004.1470688-2-shahuang@redhat.com


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 980c41f5

arch/arm64/kvm/sys_regs.c

+8 −0
Original line number Diff line number Diff line
@@ -1538,6 +1538,14 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu, 
			val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);



		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2);

		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR);

		break;

	case SYS_ID_AA64ISAR1_EL1:

		if (!vcpu_has_ptrauth(vcpu))