Commit fff010c7 authored by Guodong Xu's avatar Guodong Xu Committed by Conor Dooley
Browse files

dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt 

The descriptions for h, svinval, svnapot, and svpbmt extensions currently
reference the "20191213 version of the privileged ISA specification".
While an Unprivileged ISA document exists with that date, there is no
corresponding ratified Privileged ISA specification.

These extensions were ratified in the RISC-V Instruction Set Manual,
Volume II: Privileged Architecture, Version 20211203. Update the
descriptions to reference the correct specification version.

RISC-V International hosts a website [1] for ratified specifications.
Following the "Ratified ISA Specifications", historical versions of
Volume II Privileged ISA can be found.

Link: https://riscv.org/specifications/ratified/

 [1]
Fixes: aeb71e42 ("dt-bindings: riscv: deprecate riscv,isa")
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarGuodong Xu <guodong@riscstar.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 4297ddbf

Documentation/devicetree/bindings/riscv/extensions.yaml

+11 −8
Original line number Diff line number Diff line
@@ -117,8 +117,9 @@ properties: 


        - const: h

          description:

            The standard H extension for hypervisors as ratified in the 20191213

            version of the privileged ISA specification.

            The standard H extension for hypervisors as ratified in the RISC-V

            Instruction Set Manual, Volume II Privileged Architecture,

            Document Version 20211203.



        # multi-letter extensions, sorted alphanumerically

        - const: smaia
@@ -202,20 +203,22 @@ properties: 
        - const: svinval

          description:

            The standard Svinval supervisor-level extension for fine-grained

            address-translation cache invalidation as ratified in the 20191213

            version of the privileged ISA specification.

            address-translation cache invalidation as ratified in the RISC-V

            Instruction Set Manual, Volume II Privileged Architecture,

            Document Version 20211203.



        - const: svnapot

          description:

            The standard Svnapot supervisor-level extensions for napot

            translation contiguity as ratified in the 20191213 version of the

            privileged ISA specification.

            translation contiguity as ratified in the RISC-V Instruction Set

            Manual, Volume II Privileged Architecture, Document Version

            20211203.



        - const: svpbmt

          description:

            The standard Svpbmt supervisor-level extensions for page-based

            memory types as ratified in the 20191213 version of the privileged

            ISA specification.

            memory types as ratified in the RISC-V Instruction Set Manual,

            Volume II Privileged Architecture, Document Version 20211203.



        - const: svrsw60t59b

          description: