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drm/msm/a8xx: Add support for Adreno X2-85 GPU
Adreno X2-85 GPU is found in the next generation of Qualcomm's compute series chipset called Snapdragon X2 Elite (a.k.a Glymur). It is based on the new A8x slice architecture and features up to 4 slices. Due to the wider 12 channel DDR support, there is higher DDR bandwidth available than previous generation to improve performance. Add a new entry in the catalog along with the necessary register configurations to enable support for it. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689026/ Message-ID: <20251118-kaana-gpu-support-v4-18-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Akhil P Oommen
committed by
Rob Clark
Rob Clark
parent
60a4e18e0e
commit
01ff3bf272
@@ -1650,6 +1650,108 @@ static const struct adreno_info a7xx_gpus[] = {
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};
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DECLARE_ADRENO_GPULIST(a7xx);
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static const struct adreno_reglist_pipe x285_nonctxt_regs[] = {
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{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
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{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_RB_GC_GMEM_PROTECT, 0x15000000, BIT(PIPE_BR) },
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{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
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{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
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{ REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
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{ REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
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{ REG_A7XX_SP_CHICKEN_BITS_2, 0x00820800, BIT(PIPE_NONE) },
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{ REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
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{ REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
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/* Disable CS dead batch merge */
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{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(31), BIT(PIPE_NONE) },
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{ REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
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{ REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
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{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) },
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/* BIT(26): Disable final clamp for bicubic filtering */
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{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000720, BIT(PIPE_NONE) },
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{ REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
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{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
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{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
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{ REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
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{ REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
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{ REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
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{ },
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};
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static const u32 x285_protect_regs[] = {
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A6XX_PROTECT_RDONLY(0x00008, 0x039b),
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A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
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A6XX_PROTECT_NORDWR(0x00440, 0x001f),
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A6XX_PROTECT_RDONLY(0x00580, 0x005f),
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A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
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A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
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A6XX_PROTECT_RDONLY(0x00759, 0x0026),
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A6XX_PROTECT_RDONLY(0x00789, 0x0000),
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A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
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A6XX_PROTECT_NORDWR(0x00800, 0x0029),
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A6XX_PROTECT_NORDWR(0x0082c, 0x0000),
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A6XX_PROTECT_NORDWR(0x00837, 0x00af),
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A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
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A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
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A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
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A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
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A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
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A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
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A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
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A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
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A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
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A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
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A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
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A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
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A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
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A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
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A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
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A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
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A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
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A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
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A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
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A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
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A6XX_PROTECT_NORDWR(0x0ae00, 0x0006),
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A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
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A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
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A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
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A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
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A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
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A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
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A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
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A6XX_PROTECT_NORDWR(0x18400, 0x003f),
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A6XX_PROTECT_RDONLY(0x18440, 0x013f),
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A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
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A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
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A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
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A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
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A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
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A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
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A6XX_PROTECT_NORDWR(0x27800, 0x007f),
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A6XX_PROTECT_RDONLY(0x27880, 0x0385),
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A6XX_PROTECT_NORDWR(0x27882, 0x000a),
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A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
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};
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DECLARE_ADRENO_PROTECT(x285_protect, 64);
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static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
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{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
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{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
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@@ -1782,6 +1884,36 @@ static const struct adreno_reglist a840_gbif[] = {
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static const struct adreno_info a8xx_gpus[] = {
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{
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.chip_ids = ADRENO_CHIP_IDS(0x44070001),
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.family = ADRENO_8XX_GEN2,
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.fw = {
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[ADRENO_FW_SQE] = "gen80100_sqe.fw",
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[ADRENO_FW_GMU] = "gen80100_gmu.bin",
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},
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.gmem = 21 * SZ_1M,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
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ADRENO_QUIRK_HAS_HW_APRIV,
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.funcs = &a8xx_gpu_funcs,
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.a6xx = &(const struct a6xx_info) {
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.protect = &x285_protect,
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.nonctxt_reglist = x285_nonctxt_regs,
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.gbif_cx = a840_gbif,
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.max_slices = 4,
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.gmu_chipid = 0x8010100,
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.bcms = (const struct a6xx_bcm[]) {
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{ .name = "SH0", .buswidth = 16 },
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{ .name = "MC0", .buswidth = 4 },
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{
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.name = "ACV",
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.fixed = true,
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.perfmode = BIT(2),
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.perfmode_bw = 16500000,
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},
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{ /* sentinel */ },
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},
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},
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}, {
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.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
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.family = ADRENO_8XX_GEN2,
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.fw = {
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@@ -190,6 +190,9 @@ static void a8xx_set_hwcg(struct msm_gpu *gpu, bool state)
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struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
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u32 val;
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if (adreno_is_x285(adreno_gpu) && state)
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gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702);
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gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
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state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
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gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
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@@ -580,6 +580,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
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return gpu->info->family >= ADRENO_8XX_GEN1;
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}
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static inline int adreno_is_x285(struct adreno_gpu *gpu)
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{
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return gpu->info->chip_ids[0] == 0x44070001;
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}
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static inline int adreno_is_a840(struct adreno_gpu *gpu)
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{
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return gpu->info->chip_ids[0] == 0x44050a01;
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