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drm/amdgpu: split amdgpu_device_access_vram() into two small parts
split amdgpu_device_access_vram() 1. amdgpu_device_mm_access(): using MM_INDEX/MM_DATA to access vram 2. amdgpu_device_aper_access(): using vram aperature to access vram (option) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -287,7 +287,7 @@ bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
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*/
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/**
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* amdgpu_device_vram_access - read/write a buffer in vram
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* amdgpu_device_mm_access - access vram by MM_INDEX/MM_DATA
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*
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* @adev: amdgpu_device pointer
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* @pos: offset of the buffer in vram
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@@ -295,22 +295,65 @@ bool amdgpu_device_supports_smart_shift(struct drm_device *dev)
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* @size: read/write size, sizeof(@buf) must > @size
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* @write: true - write to vram, otherwise - read from vram
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*/
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void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
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uint32_t *buf, size_t size, bool write)
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void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
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void *buf, size_t size, bool write)
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{
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unsigned long flags;
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uint32_t hi = ~0;
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uint32_t hi = ~0, tmp = 0;
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uint32_t *data = buf;
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uint64_t last;
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int idx;
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if (!drm_dev_enter(&adev->ddev, &idx))
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return;
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BUG_ON(!IS_ALIGNED(pos, 4) || !IS_ALIGNED(size, 4));
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spin_lock_irqsave(&adev->mmio_idx_lock, flags);
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for (last = pos + size; pos < last; pos += 4) {
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tmp = pos >> 31;
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WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
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if (tmp != hi) {
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WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
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hi = tmp;
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}
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if (write)
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WREG32_NO_KIQ(mmMM_DATA, *data++);
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else
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*data++ = RREG32_NO_KIQ(mmMM_DATA);
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}
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spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
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drm_dev_exit(idx);
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}
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/**
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* amdgpu_device_vram_access - access vram by vram aperature
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*
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* @adev: amdgpu_device pointer
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* @pos: offset of the buffer in vram
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* @buf: virtual address of the buffer in system memory
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* @size: read/write size, sizeof(@buf) must > @size
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* @write: true - write to vram, otherwise - read from vram
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*
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* The return value means how many bytes have been transferred.
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*/
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size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
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void *buf, size_t size, bool write)
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{
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#ifdef CONFIG_64BIT
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void __iomem *addr;
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size_t count = 0;
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uint64_t last;
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if (!adev->mman.aper_base_kaddr)
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return 0;
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last = min(pos + size, adev->gmc.visible_vram_size);
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if (last > pos) {
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void __iomem *addr = adev->mman.aper_base_kaddr + pos;
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size_t count = last - pos;
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addr = adev->mman.aper_base_kaddr + pos;
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count = last - pos;
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if (write) {
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memcpy_toio(addr, buf, count);
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@@ -322,35 +365,37 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
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memcpy_fromio(buf, addr, count);
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}
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if (count == size)
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goto exit;
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}
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return count;
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#else
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return 0;
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#endif
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}
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/**
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* amdgpu_device_vram_access - read/write a buffer in vram
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*
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* @adev: amdgpu_device pointer
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* @pos: offset of the buffer in vram
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* @buf: virtual address of the buffer in system memory
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* @size: read/write size, sizeof(@buf) must > @size
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* @write: true - write to vram, otherwise - read from vram
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*/
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void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
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void *buf, size_t size, bool write)
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{
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size_t count;
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/* try to using vram apreature to access vram first */
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count = amdgpu_device_aper_access(adev, pos, buf, size, write);
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size -= count;
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if (size) {
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/* using MM to access rest vram */
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pos += count;
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buf += count / 4;
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size -= count;
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buf += count;
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amdgpu_device_mm_access(adev, pos, buf, size, write);
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}
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#endif
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spin_lock_irqsave(&adev->mmio_idx_lock, flags);
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for (last = pos + size; pos < last; pos += 4) {
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uint32_t tmp = pos >> 31;
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WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x80000000);
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if (tmp != hi) {
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WREG32_NO_KIQ(mmMM_INDEX_HI, tmp);
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hi = tmp;
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}
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if (write)
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WREG32_NO_KIQ(mmMM_DATA, *buf++);
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else
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*buf++ = RREG32_NO_KIQ(mmMM_DATA);
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}
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spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
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#ifdef CONFIG_64BIT
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exit:
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#endif
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drm_dev_exit(idx);
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}
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/*
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