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Merge drm/drm-next into drm-misc-next

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Backmerging to get a late RC of v6.10 before moving into v6.11.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
This commit is contained in:
Thomas Zimmermann
2024-07-29 09:35:54 +02:00
parent 0c3f3a83c7 d4ef5d2b7e
commit 0e8655b4e8
2694 changed files with 387715 additions and 28887 deletions
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55
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
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@@ -50,7 +50,7 @@
#define AMDGPU_DM_MAX_NUM_EDP 2
#define AMDGPU_DMUB_NOTIFICATION_MAX 5
#define AMDGPU_DMUB_NOTIFICATION_MAX 6
#define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A
#define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40
@@ -137,6 +137,20 @@ struct vblank_control_work {
bool enable;
};
/**
* struct idle_workqueue - Work data for periodic action in idle
* @work: Kernel work data for the work event
* @dm: amdgpu display manager device
* @enable: true if idle worker is enabled
* @running: true if idle worker is running
*/
struct idle_workqueue {
struct work_struct work;
struct amdgpu_display_manager *dm;
bool enable;
bool running;
};
/**
* struct amdgpu_dm_backlight_caps - Information about backlight
*
@@ -173,6 +187,14 @@ struct amdgpu_dm_backlight_caps {
* @aux_support: Describes if the display supports AUX backlight.
*/
bool aux_support;
/**
* @ac_level: the default brightness if booted on AC
*/
u8 ac_level;
/**
* @dc_level: the default brightness if booted on DC
*/
u8 dc_level;
};
/**
@@ -488,6 +510,13 @@ struct amdgpu_display_manager {
*/
struct workqueue_struct *vblank_control_workqueue;
/**
* @idle_workqueue:
*
* Periodic work for idle events.
*/
struct idle_workqueue *idle_workqueue;
struct drm_atomic_state *cached_state;
struct dc_state *cached_dc_state;
@@ -570,6 +599,13 @@ struct amdgpu_display_manager {
* Guards access to DPIA AUX
*/
struct mutex dpia_aux_lock;
/**
* @bb_from_dmub:
*
* Bounding box data read from dmub during early initialization for DCN4+
*/
struct dml2_soc_bb *bb_from_dmub;
};
enum dsc_clock_force_state {
@@ -678,7 +714,6 @@ struct amdgpu_dm_connector {
* value is set to zero when there is no FreeSync support.
*/
int max_vfreq ;
int pixel_clock_mhz;
/* Audio instance - protected by audio_lock. */
int audio_inst;
@@ -822,6 +857,11 @@ struct dm_plane_state {
enum amdgpu_transfer_function blend_tf;
};
enum amdgpu_dm_cursor_mode {
DM_CURSOR_NATIVE_MODE = 0,
DM_CURSOR_OVERLAY_MODE,
};
struct dm_crtc_state {
struct drm_crtc_state base;
struct dc_stream_state *stream;
@@ -852,6 +892,8 @@ struct dm_crtc_state {
* encoding.
*/
enum amdgpu_transfer_function regamma_tf;
enum amdgpu_dm_cursor_mode cursor_mode;
};
#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
@@ -958,4 +1000,13 @@ amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
struct drm_crtc *crtc);
int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth);
struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev);
void *dm_allocate_gpu_mem(struct amdgpu_device *adev,
enum dc_gpu_mem_alloc_type type,
size_t size,
long long *addr);
bool amdgpu_dm_is_headless(struct amdgpu_device *adev);
#endif /* __AMDGPU_DM_H__ */