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synced 2026-04-06 08:47:40 -04:00
drm/msm/dsi/phy: Add support for SM8750
Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an incompatible hardware interface change: ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their offsets were just switched. Currently these registers are not used in the driver, so the easiest is to document both but keep them commented out to avoid conflict. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/659616/ Link: https://lore.kernel.org/r/20250618-b4-sm8750-display-v7-6-a591c609743d@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Krzysztof Kozlowski
committed by
Dmitry Baryshkov
Dmitry Baryshkov
parent
6b93840116
commit
1337d7ebfb
@@ -597,6 +597,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
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.data = &dsi_phy_4nm_8550_cfgs },
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{ .compatible = "qcom,sm8650-dsi-phy-4nm",
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.data = &dsi_phy_4nm_8650_cfgs },
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{ .compatible = "qcom,sm8750-dsi-phy-3nm",
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.data = &dsi_phy_3nm_8750_cfgs },
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#endif
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{}
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};
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@@ -63,6 +63,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
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extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs;
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struct msm_dsi_dphy_timing {
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u32 clk_zero;
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@@ -51,6 +51,8 @@
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#define DSI_PHY_7NM_QUIRK_V4_3 BIT(3)
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/* Hardware is V5.2 */
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#define DSI_PHY_7NM_QUIRK_V5_2 BIT(4)
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/* Hardware is V7.0 */
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#define DSI_PHY_7NM_QUIRK_V7_0 BIT(5)
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struct dsi_pll_config {
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bool enable_ssc;
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@@ -129,9 +131,30 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
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dec_multiple = div_u64(pll_freq * multiplier, divider);
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dec = div_u64_rem(dec_multiple, multiplier, &frac);
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if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
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if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) {
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config->pll_clock_inverters = 0x28;
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else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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} else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
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if (pll_freq < 163000000ULL)
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config->pll_clock_inverters = 0xa0;
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else if (pll_freq < 175000000ULL)
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config->pll_clock_inverters = 0x20;
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else if (pll_freq < 325000000ULL)
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config->pll_clock_inverters = 0xa0;
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else if (pll_freq < 350000000ULL)
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config->pll_clock_inverters = 0x20;
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else if (pll_freq < 650000000ULL)
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config->pll_clock_inverters = 0xa0;
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else if (pll_freq < 700000000ULL)
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config->pll_clock_inverters = 0x20;
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else if (pll_freq < 1300000000ULL)
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config->pll_clock_inverters = 0xa0;
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else if (pll_freq < 2500000000ULL)
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config->pll_clock_inverters = 0x20;
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else if (pll_freq < 4000000000ULL)
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config->pll_clock_inverters = 0x00;
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else
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config->pll_clock_inverters = 0x40;
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} else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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if (pll_freq <= 1300000000ULL)
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config->pll_clock_inverters = 0xa0;
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else if (pll_freq <= 2500000000ULL)
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@@ -250,7 +273,8 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
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vco_config_1 = 0x01;
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}
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if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
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(pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
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if (pll->vco_current_rate < 1557000000ULL)
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vco_config_1 = 0x08;
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else
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@@ -620,6 +644,7 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
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static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
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{
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struct dsi_pll_7nm *pll_7nm = to_pll_7nm(phy->vco_hw);
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void __iomem *base = phy->base;
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u32 data = 0x0; /* internal PLL */
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DBG("DSI PLL%d", pll_7nm->phy->id);
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@@ -629,6 +654,9 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
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break;
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case MSM_DSI_PHY_MASTER:
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pll_7nm->slave = pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX];
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/* v7.0: Enable ATB_EN0 and alternate clock output to external phy */
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if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)
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writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5);
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break;
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case MSM_DSI_PHY_SLAVE:
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data = 0x1; /* external PLL */
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@@ -907,7 +935,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
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/* Request for REFGEN READY */
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
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writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
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udelay(500);
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}
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@@ -941,7 +970,20 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
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lane_ctrl0 = 0x1f;
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}
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
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if (phy->cphy_mode) {
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/* TODO: different for second phy */
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vreg_ctrl_0 = 0x57;
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vreg_ctrl_1 = 0x41;
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glbl_rescode_top_ctrl = 0x3d;
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glbl_rescode_bot_ctrl = 0x38;
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} else {
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vreg_ctrl_0 = 0x56;
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vreg_ctrl_1 = 0x19;
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glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c : 0x03;
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glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 : 0x3c;
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}
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} else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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if (phy->cphy_mode) {
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vreg_ctrl_0 = 0x45;
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vreg_ctrl_1 = 0x41;
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@@ -1003,6 +1045,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
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/* program CMN_CTRL_4 for minor_ver 2 chipsets*/
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) ||
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(readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
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writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4);
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@@ -1117,7 +1160,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
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/* Turn off REFGEN Vote */
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if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
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(phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) {
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writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10);
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wmb();
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/* Delay to ensure HW removes vote before PHY shut down */
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@@ -1384,3 +1428,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = {
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.num_dsi_phy = 2,
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.quirks = DSI_PHY_7NM_QUIRK_V5_2,
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};
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const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs = {
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.has_phy_lane = true,
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.regulator_data = dsi_phy_7nm_98000uA_regulators,
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.num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
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.ops = {
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.enable = dsi_7nm_phy_enable,
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.disable = dsi_7nm_phy_disable,
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.pll_init = dsi_pll_7nm_init,
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.save_pll_state = dsi_7nm_pll_save_state,
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.restore_pll_state = dsi_7nm_pll_restore_state,
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.set_continuous_clock = dsi_7nm_set_continuous_clock,
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},
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.min_pll_rate = 600000000UL,
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#ifdef CONFIG_64BIT
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.max_pll_rate = 5000000000UL,
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#else
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.max_pll_rate = ULONG_MAX,
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#endif
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.io_start = { 0xae95000, 0xae97000 },
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.num_dsi_phy = 2,
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.quirks = DSI_PHY_7NM_QUIRK_V7_0,
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};
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@@ -26,6 +26,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<reg32 offset="0x00028" name="CTRL_1"/>
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<reg32 offset="0x0002c" name="CTRL_2"/>
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<reg32 offset="0x00030" name="CTRL_3"/>
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<reg32 offset="0x001b0" name="CTRL_5"/>
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<reg32 offset="0x00034" name="LANE_CFG0"/>
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<reg32 offset="0x00038" name="LANE_CFG1"/>
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<reg32 offset="0x0003c" name="PLL_CNTRL"/>
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@@ -191,11 +192,24 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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<reg32 offset="0x01b0" name="COMMON_STATUS_ONE"/>
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<reg32 offset="0x01b4" name="COMMON_STATUS_TWO"/>
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<reg32 offset="0x01b8" name="BAND_SEL_CAL"/>
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<!--
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Starting with SM8750, offset moved from 0x01bc to 0x01cc, however
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we keep only one register map. That's not a problem, so far,
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because this register is not used. The register map should be split
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once it is going to be used. Comment out the code to prevent
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any misuse due to the change in the offset.
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<reg32 offset="0x01bc" name="ICODE_ACCUM_STATUS_LOW"/>
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<reg32 offset="0x01cc" name="ICODE_ACCUM_STATUS_LOW"/>
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-->
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<reg32 offset="0x01c0" name="ICODE_ACCUM_STATUS_HIGH"/>
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<reg32 offset="0x01c4" name="FD_OUT_LOW"/>
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<reg32 offset="0x01c8" name="FD_OUT_HIGH"/>
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<!--
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Starting with SM8750, offset moved from 0x01cc to 0x01bc, however
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we keep only one register map. See above comment.
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<reg32 offset="0x01cc" name="ALOG_OBSV_BUS_STATUS_1"/>
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<reg32 offset="0x01bc" name="ALOG_OBSV_BUS_STATUS_1"/>
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-->
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<reg32 offset="0x01d0" name="PLL_MISC_CONFIG"/>
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<reg32 offset="0x01d4" name="FLL_CONFIG"/>
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<reg32 offset="0x01d8" name="FLL_FREQ_ACQ_TIME"/>
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