Loading include/asm-x86/sync_bitops.h +28 −28 Original line number Diff line number Diff line Loading @@ -28,7 +28,7 @@ */ static inline void sync_set_bit(int nr, volatile unsigned long *addr) { __asm__ __volatile__("lock; btsl %1,%0" asm volatile("lock; btsl %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); Loading @@ -46,7 +46,7 @@ static inline void sync_set_bit(int nr, volatile unsigned long * addr) */ static inline void sync_clear_bit(int nr, volatile unsigned long *addr) { __asm__ __volatile__("lock; btrl %1,%0" asm volatile("lock; btrl %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); Loading @@ -63,7 +63,7 @@ static inline void sync_clear_bit(int nr, volatile unsigned long * addr) */ static inline void sync_change_bit(int nr, volatile unsigned long *addr) { __asm__ __volatile__("lock; btcl %1,%0" asm volatile("lock; btcl %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); Loading @@ -81,7 +81,7 @@ static inline int sync_test_and_set_bit(int nr, volatile unsigned long * addr) { int oldbit; __asm__ __volatile__("lock; btsl %2,%1\n\tsbbl %0,%0" asm volatile("lock; btsl %2,%1\n\tsbbl %0,%0" : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory"); return oldbit; Loading @@ -99,7 +99,7 @@ static inline int sync_test_and_clear_bit(int nr, volatile unsigned long * addr) { int oldbit; __asm__ __volatile__("lock; btrl %2,%1\n\tsbbl %0,%0" asm volatile("lock; btrl %2,%1\n\tsbbl %0,%0" : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory"); return oldbit; Loading @@ -117,7 +117,7 @@ static inline int sync_test_and_change_bit(int nr, volatile unsigned long* addr) { int oldbit; __asm__ __volatile__("lock; btcl %2,%1\n\tsbbl %0,%0" asm volatile("lock; btcl %2,%1\n\tsbbl %0,%0" : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory"); return oldbit; Loading Loading
include/asm-x86/sync_bitops.h +28 −28 Original line number Diff line number Diff line Loading @@ -28,7 +28,7 @@ */ static inline void sync_set_bit(int nr, volatile unsigned long *addr) { __asm__ __volatile__("lock; btsl %1,%0" asm volatile("lock; btsl %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); Loading @@ -46,7 +46,7 @@ static inline void sync_set_bit(int nr, volatile unsigned long * addr) */ static inline void sync_clear_bit(int nr, volatile unsigned long *addr) { __asm__ __volatile__("lock; btrl %1,%0" asm volatile("lock; btrl %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); Loading @@ -63,7 +63,7 @@ static inline void sync_clear_bit(int nr, volatile unsigned long * addr) */ static inline void sync_change_bit(int nr, volatile unsigned long *addr) { __asm__ __volatile__("lock; btcl %1,%0" asm volatile("lock; btcl %1,%0" : "+m" (ADDR) : "Ir" (nr) : "memory"); Loading @@ -81,7 +81,7 @@ static inline int sync_test_and_set_bit(int nr, volatile unsigned long * addr) { int oldbit; __asm__ __volatile__("lock; btsl %2,%1\n\tsbbl %0,%0" asm volatile("lock; btsl %2,%1\n\tsbbl %0,%0" : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory"); return oldbit; Loading @@ -99,7 +99,7 @@ static inline int sync_test_and_clear_bit(int nr, volatile unsigned long * addr) { int oldbit; __asm__ __volatile__("lock; btrl %2,%1\n\tsbbl %0,%0" asm volatile("lock; btrl %2,%1\n\tsbbl %0,%0" : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory"); return oldbit; Loading @@ -117,7 +117,7 @@ static inline int sync_test_and_change_bit(int nr, volatile unsigned long* addr) { int oldbit; __asm__ __volatile__("lock; btcl %2,%1\n\tsbbl %0,%0" asm volatile("lock; btcl %2,%1\n\tsbbl %0,%0" : "=r" (oldbit), "+m" (ADDR) : "Ir" (nr) : "memory"); return oldbit; Loading