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Merge tag 'drm-fixes-for-v4.9-rc2' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Just had a couple of amdgpu fixes and one core fix I wanted to get out early to fix some regressions. I'm sure I'll have more stuff this week for -rc2" * tag 'drm-fixes-for-v4.9-rc2' of git://people.freedesktop.org/~airlied/linux: (22 commits) drm: Print device information again in debugfs drm/amd/powerplay: fix bug stop dpm can't work on Vi. drm/amd/powerplay: notify smu no display by default. drm/amdgpu/dpm: implement thermal sensor for CZ/ST drm/amdgpu/powerplay: implement thermal sensor for CZ/ST drm/amdgpu: disable smu hw first on tear down drm/amdgpu: fix amdgpu_need_full_reset (v2) drm/amdgpu/si_dpm: Limit clocks on HD86xx part drm/amd/powerplay: fix static checker warnings in smu7_hwmgr.c drm/amdgpu: potential NULL dereference in debugfs code drm/amd/powerplay: fix static checker warnings in smu7_hwmgr.c drm/amd/powerplay: fix static checker warnings in iceland_smc.c drm/radeon: change vblank_time's calculation method to reduce computational error. drm/amdgpu: change vblank_time's calculation method to reduce computational error. drm/amdgpu: clarify UVD/VCE special handling for CG drm/amd/amdgpu: enable clockgating only after late init drm/radeon: allow TA_CS_BC_BASE_ADDR on SI drm/amdgpu: initialize the context reset_counter in amdgpu_ctx_init drm/amdgpu/gfx8: fix CGCG_CGLS handling drm/radeon: fix modeset tear down code ...
This commit is contained in:
@@ -1408,16 +1408,6 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!adev->ip_block_status[i].valid)
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continue;
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if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_UVD ||
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adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_VCE)
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continue;
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/* enable clockgating to save power */
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r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
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AMD_CG_STATE_GATE);
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if (r) {
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DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);
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return r;
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}
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if (adev->ip_blocks[i].funcs->late_init) {
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r = adev->ip_blocks[i].funcs->late_init((void *)adev);
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if (r) {
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@@ -1426,6 +1416,18 @@ static int amdgpu_late_init(struct amdgpu_device *adev)
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}
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adev->ip_block_status[i].late_initialized = true;
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}
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/* skip CG for VCE/UVD, it's handled specially */
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if (adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_UVD &&
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adev->ip_blocks[i].type != AMD_IP_BLOCK_TYPE_VCE) {
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/* enable clockgating to save power */
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r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
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AMD_CG_STATE_GATE);
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if (r) {
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DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
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adev->ip_blocks[i].funcs->name, r);
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return r;
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}
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}
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}
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return 0;
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@@ -1435,6 +1437,30 @@ static int amdgpu_fini(struct amdgpu_device *adev)
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{
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int i, r;
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/* need to disable SMC first */
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!adev->ip_block_status[i].hw)
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continue;
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if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) {
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/* ungate blocks before hw fini so that we can shutdown the blocks safely */
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r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
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AMD_CG_STATE_UNGATE);
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if (r) {
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DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
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adev->ip_blocks[i].funcs->name, r);
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return r;
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}
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r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
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/* XXX handle errors */
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if (r) {
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DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
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adev->ip_blocks[i].funcs->name, r);
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}
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adev->ip_block_status[i].hw = false;
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break;
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}
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}
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for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
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if (!adev->ip_block_status[i].hw)
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continue;
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@@ -2073,7 +2099,8 @@ static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
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if (!adev->ip_block_status[i].valid)
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continue;
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if (adev->ip_blocks[i].funcs->check_soft_reset)
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adev->ip_blocks[i].funcs->check_soft_reset(adev);
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adev->ip_block_status[i].hang =
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adev->ip_blocks[i].funcs->check_soft_reset(adev);
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if (adev->ip_block_status[i].hang) {
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DRM_INFO("IP block:%d is hang!\n", i);
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asic_hang = true;
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@@ -2102,12 +2129,20 @@ static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
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static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
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{
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if (adev->ip_block_status[AMD_IP_BLOCK_TYPE_GMC].hang ||
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_SMC].hang ||
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_ACP].hang ||
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adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang) {
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DRM_INFO("Some block need full reset!\n");
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return true;
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int i;
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for (i = 0; i < adev->num_ip_blocks; i++) {
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if (!adev->ip_block_status[i].valid)
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continue;
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if ((adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) ||
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(adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_SMC) ||
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(adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_ACP) ||
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(adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_DCE)) {
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if (adev->ip_block_status[i].hang) {
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DRM_INFO("Some block need full reset!\n");
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return true;
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}
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}
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}
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return false;
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}
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