mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/
synced 2026-04-23 08:55:56 -04:00
Merge tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "Summary below. i915 starts to add support for DG2 GPUs, enables DG1 and ADL-S support by default, lots of work to enable DisplayPort 2.0 across drivers. Lots of documentation updates and fixes across the board. core: - improve dma_fence, lease and resv documentation - shmem-helpers: allocate WC pages on x86, use vmf_insert_pin - sched fixes/improvements - allow empty drm leases - add dma resv iterator - add more DP 2.0 headers - DP MST helper improvements for DP2.0 dma-buf: - avoid warnings, remove fence trace macros bridge: - new helper to get rid of panels - probe improvements for it66121 - enable DSI EOTP for anx7625 fbdev: - efifb: release runtime PM on destroy ttm: - kerneldoc switch - helper to clear all DMA mappings - pool shrinker optimizaton - remove ttm_tt_destroy_common - update ttm_move_memcpy for async use panel: - add new panel-edp driver amdgpu: - Initial DP 2.0 support - Initial USB4 DP tunnelling support - Aldebaran MCE support - Modifier support for DCC image stores for GFX 10.3 - Display rework for better FP code handling - Yellow Carp/Cyan Skillfish updates - Cyan Skillfish display support - convert vega/navi to IP discovery asic enumeration - validate IP discovery table - RAS improvements - Lots of fixes i915: - DG1 PCI IDs + LMEM discovery/placement - DG1 GuC submission by default - ADL-S PCI IDs updated + enabled by default - ADL-P (XE_LPD) fixed and updates - DG2 display fixes - PXP protected object support for Gen12 integrated - expose multi-LRC submission interface for GuC - export logical engine instance to user - Disable engine bonding on Gen12+ - PSR cleanup - PSR2 selective fetch by default - DP 2.0 prep work - VESA vendor block + MSO use of it - FBC refactor - try again to fix fast-narrow vs slow-wide eDP training - use THP when IOMMU enabled - LMEM backup/restore for suspend/resume - locking simplification - GuC major reworking - async flip VT-D workaround changes - DP link training improvements - misc display refactorings bochs: - new PCI ID rcar-du: - Non-contiguious buffer import support for rcar-du - r8a779a0 support prep omapdrm: - COMPILE_TEST fixes sti: - COMPILE_TEST fixes msm: - fence ordering improvements - eDP support in DP sub-driver - dpu irq handling cleanup - CRC support for making igt happy - NO_CONNECTOR bridge support - dsi: 14nm phy support for msm8953 - mdp5: msm8x53, sdm450, sdm632 support stm: - layer alpha + zpo support v3d: - fix Vulkan CTS failure - support multiple sync objects gud: - add R8/RGB332/RGB888 pixel formats vc4: - convert to new bridge helpers vgem: - use shmem helpers virtio: - support mapping exported vram zte: - remove obsolete driver rockchip: - use bridge attach no connector for LVDS/RGB" * tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drm: (1259 commits) drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bits drm/amd/display: MST support for DPIA drm/amdgpu: Fix even more out of bound writes from debugfs drm/amdgpu/discovery: add SDMA IP instance info for soc15 parts drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 parts drm/amdgpu/UAPI: rearrange header to better align related items drm/amd/display: Enable dpia in dmub only for DCN31 B0 drm/amd/display: Fix USB4 hot plug crash issue drm/amd/display: Fix deadlock when falling back to v2 from v3 drm/amd/display: Fallback to clocks which meet requested voltage on DCN31 drm/amd/display: move FPU associated DCN301 code to DML folder drm/amd/display: fix link training regression for 1 or 2 lane drm/amd/display: add two lane settings training options drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings drm/amd/display: implement decide lane settings drm/amd/display: adopt DP2.0 LT SCR revision 8 drm/amd/display: FEC configuration for dpia links in MST mode drm/amd/display: FEC configuration for dpia links drm/amd/display: Add workaround flag for EDID read on certain docks drm/amd/display: Set phy_mux_sel bit in dmub scratch register ...
This commit is contained in:
Linus Torvalds
@@ -97,9 +97,11 @@
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||||
* - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
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||||
* - 3.41.0 - Add video codec query
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||||
* - 3.42.0 - Add 16bpc fixed point display support
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||||
* - 3.43.0 - Add device hot plug/unplug support
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||||
* - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
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||||
*/
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||||
#define KMS_DRIVER_MAJOR 3
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||||
#define KMS_DRIVER_MINOR 42
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||||
#define KMS_DRIVER_MINOR 44
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||||
#define KMS_DRIVER_PATCHLEVEL 0
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||||
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int amdgpu_vram_limit;
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||||
@@ -628,7 +630,7 @@ module_param_named(mcbp, amdgpu_mcbp, int, 0444);
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||||
/**
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||||
* DOC: discovery (int)
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||||
* Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
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||||
* (-1 = auto (default), 0 = disabled, 1 = enabled)
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||||
* (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
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||||
*/
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||||
MODULE_PARM_DESC(discovery,
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||||
"Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
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||||
@@ -876,7 +878,7 @@ module_param_named(reset_method, amdgpu_reset_method, int, 0444);
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||||
* result in the GPU entering bad status when the number of total
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||||
* faulty pages by ECC exceeds the threshold value.
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||||
*/
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||||
MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)");
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MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
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module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
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||||
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||||
MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
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||||
@@ -891,6 +893,636 @@ MODULE_PARM_DESC(smu_pptable_id,
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||||
"specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
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module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
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||||
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||||
/* These devices are not supported by amdgpu.
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* They are supported by the mach64, r128, radeon drivers
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||||
*/
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||||
static const u16 amdgpu_unsupported_pciidlist[] = {
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/* mach64 */
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0x4354,
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/* r128 */
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0x4c45,
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||||
/* radeon */
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||||
0x3150,
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0x7291,
|
||||
0x7293,
|
||||
0x7297,
|
||||
0x7834,
|
||||
0x7835,
|
||||
0x791e,
|
||||
0x791f,
|
||||
0x793f,
|
||||
0x7941,
|
||||
0x7942,
|
||||
0x796c,
|
||||
0x796d,
|
||||
0x796e,
|
||||
0x796f,
|
||||
0x9400,
|
||||
0x9401,
|
||||
0x9402,
|
||||
0x9403,
|
||||
0x9405,
|
||||
0x940A,
|
||||
0x940B,
|
||||
0x940F,
|
||||
0x94A0,
|
||||
0x94A1,
|
||||
0x94A3,
|
||||
0x94B1,
|
||||
0x94B3,
|
||||
0x94B4,
|
||||
0x94B5,
|
||||
0x94B9,
|
||||
0x9440,
|
||||
0x9441,
|
||||
0x9442,
|
||||
0x9443,
|
||||
0x9444,
|
||||
0x9446,
|
||||
0x944A,
|
||||
0x944B,
|
||||
0x944C,
|
||||
0x944E,
|
||||
0x9450,
|
||||
0x9452,
|
||||
0x9456,
|
||||
0x945A,
|
||||
0x945B,
|
||||
0x945E,
|
||||
0x9460,
|
||||
0x9462,
|
||||
0x946A,
|
||||
0x946B,
|
||||
0x947A,
|
||||
0x947B,
|
||||
0x9480,
|
||||
0x9487,
|
||||
0x9488,
|
||||
0x9489,
|
||||
0x948A,
|
||||
0x948F,
|
||||
0x9490,
|
||||
0x9491,
|
||||
0x9495,
|
||||
0x9498,
|
||||
0x949C,
|
||||
0x949E,
|
||||
0x949F,
|
||||
0x94C0,
|
||||
0x94C1,
|
||||
0x94C3,
|
||||
0x94C4,
|
||||
0x94C5,
|
||||
0x94C6,
|
||||
0x94C7,
|
||||
0x94C8,
|
||||
0x94C9,
|
||||
0x94CB,
|
||||
0x94CC,
|
||||
0x94CD,
|
||||
0x9500,
|
||||
0x9501,
|
||||
0x9504,
|
||||
0x9505,
|
||||
0x9506,
|
||||
0x9507,
|
||||
0x9508,
|
||||
0x9509,
|
||||
0x950F,
|
||||
0x9511,
|
||||
0x9515,
|
||||
0x9517,
|
||||
0x9519,
|
||||
0x9540,
|
||||
0x9541,
|
||||
0x9542,
|
||||
0x954E,
|
||||
0x954F,
|
||||
0x9552,
|
||||
0x9553,
|
||||
0x9555,
|
||||
0x9557,
|
||||
0x955f,
|
||||
0x9580,
|
||||
0x9581,
|
||||
0x9583,
|
||||
0x9586,
|
||||
0x9587,
|
||||
0x9588,
|
||||
0x9589,
|
||||
0x958A,
|
||||
0x958B,
|
||||
0x958C,
|
||||
0x958D,
|
||||
0x958E,
|
||||
0x958F,
|
||||
0x9590,
|
||||
0x9591,
|
||||
0x9593,
|
||||
0x9595,
|
||||
0x9596,
|
||||
0x9597,
|
||||
0x9598,
|
||||
0x9599,
|
||||
0x959B,
|
||||
0x95C0,
|
||||
0x95C2,
|
||||
0x95C4,
|
||||
0x95C5,
|
||||
0x95C6,
|
||||
0x95C7,
|
||||
0x95C9,
|
||||
0x95CC,
|
||||
0x95CD,
|
||||
0x95CE,
|
||||
0x95CF,
|
||||
0x9610,
|
||||
0x9611,
|
||||
0x9612,
|
||||
0x9613,
|
||||
0x9614,
|
||||
0x9615,
|
||||
0x9616,
|
||||
0x9640,
|
||||
0x9641,
|
||||
0x9642,
|
||||
0x9643,
|
||||
0x9644,
|
||||
0x9645,
|
||||
0x9647,
|
||||
0x9648,
|
||||
0x9649,
|
||||
0x964a,
|
||||
0x964b,
|
||||
0x964c,
|
||||
0x964e,
|
||||
0x964f,
|
||||
0x9710,
|
||||
0x9711,
|
||||
0x9712,
|
||||
0x9713,
|
||||
0x9714,
|
||||
0x9715,
|
||||
0x9802,
|
||||
0x9803,
|
||||
0x9804,
|
||||
0x9805,
|
||||
0x9806,
|
||||
0x9807,
|
||||
0x9808,
|
||||
0x9809,
|
||||
0x980A,
|
||||
0x9900,
|
||||
0x9901,
|
||||
0x9903,
|
||||
0x9904,
|
||||
0x9905,
|
||||
0x9906,
|
||||
0x9907,
|
||||
0x9908,
|
||||
0x9909,
|
||||
0x990A,
|
||||
0x990B,
|
||||
0x990C,
|
||||
0x990D,
|
||||
0x990E,
|
||||
0x990F,
|
||||
0x9910,
|
||||
0x9913,
|
||||
0x9917,
|
||||
0x9918,
|
||||
0x9919,
|
||||
0x9990,
|
||||
0x9991,
|
||||
0x9992,
|
||||
0x9993,
|
||||
0x9994,
|
||||
0x9995,
|
||||
0x9996,
|
||||
0x9997,
|
||||
0x9998,
|
||||
0x9999,
|
||||
0x999A,
|
||||
0x999B,
|
||||
0x999C,
|
||||
0x999D,
|
||||
0x99A0,
|
||||
0x99A2,
|
||||
0x99A4,
|
||||
};
|
||||
|
||||
static const struct pci_device_id pciidlist[] = {
|
||||
#ifdef CONFIG_DRM_AMDGPU_SI
|
||||
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
|
||||
@@ -1240,6 +1872,16 @@ static const struct pci_device_id pciidlist[] = {
|
||||
{0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
|
||||
{0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
|
||||
|
||||
{ PCI_DEVICE(0x1002, PCI_ANY_ID),
|
||||
.class = PCI_CLASS_DISPLAY_VGA << 8,
|
||||
.class_mask = 0xffffff,
|
||||
.driver_data = CHIP_IP_DISCOVERY },
|
||||
|
||||
{ PCI_DEVICE(0x1002, PCI_ANY_ID),
|
||||
.class = PCI_CLASS_DISPLAY_OTHER << 8,
|
||||
.class_mask = 0xffffff,
|
||||
.driver_data = CHIP_IP_DISCOVERY },
|
||||
|
||||
{0, 0, 0}
|
||||
};
|
||||
|
||||
@@ -1253,9 +1895,20 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
|
||||
struct drm_device *ddev;
|
||||
struct amdgpu_device *adev;
|
||||
unsigned long flags = ent->driver_data;
|
||||
int ret, retry = 0;
|
||||
int ret, retry = 0, i;
|
||||
bool supports_atomic = false;
|
||||
|
||||
/* skip devices which are owned by radeon */
|
||||
for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
|
||||
if (amdgpu_unsupported_pciidlist[i] == pdev->device)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (flags == 0) {
|
||||
DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (amdgpu_virtual_display ||
|
||||
amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
|
||||
supports_atomic = true;
|
||||
@@ -1510,6 +2163,10 @@ static int amdgpu_pmops_resume(struct device *dev)
|
||||
struct amdgpu_device *adev = drm_to_adev(drm_dev);
|
||||
int r;
|
||||
|
||||
/* Avoids registers access if device is physically gone */
|
||||
if (!pci_device_is_present(adev->pdev))
|
||||
adev->no_hw_access = true;
|
||||
|
||||
r = amdgpu_device_resume(drm_dev, true);
|
||||
if (amdgpu_acpi_is_s0ix_active(adev))
|
||||
adev->in_s0ix = false;
|
||||
|
||||
Reference in New Issue
Block a user