From dff552ac9cdaa94b6d10d8707c8c24255a4cbdb0 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sat, 27 Sep 2025 08:56:31 +0100 Subject: [PATCH 001/757] arm64: dts: broadcom: bcm2712: Enable RNG The RNG is the same IP as in the bcm2711 so add the device tree block to enable the device. Signed-off-by: Peter Robinson Reviewed-by: Stefan Wahren Link: https://lore.kernel.org/r/20250927075643.716179-1-pbrobinson@gmail.com Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index e77a66adc22a..f97b42d91a1c 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -283,6 +283,12 @@ reg = <0x7d510700 0x20>; }; + random: rng@7d208000 { + compatible = "brcm,bcm2711-rng200"; + reg = <0x7d208000 0x28>; + status = "okay"; + }; + interrupt-controller@7d517000 { compatible = "brcm,bcm7271-l2-intc"; reg = <0x7d517000 0x10>; From 37c3a91e9730e274fe2eca9703033ae0f154cb62 Mon Sep 17 00:00:00 2001 From: Stanimir Varbanov Date: Fri, 31 Oct 2025 20:33:09 +0200 Subject: [PATCH 002/757] arm64: dts: broadcom: bcm2712: Add watchdog DT node Add watchdog device-tree node for bcm2712 SoC. Signed-off-by: Stanimir Varbanov Link: https://lore.kernel.org/r/20251031183309.1163384-5-svarbanov@suse.de Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index f97b42d91a1c..f5b04f360369 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -250,6 +250,15 @@ status = "disabled"; }; + pm: watchdog@7d200000 { + compatible = "brcm,bcm2712-pm", "brcm,bcm2835-pm-wdt"; + reg = <0x7d200000 0x604>; + reg-names = "pm"; + #power-domain-cells = <1>; + #reset-cells = <1>; + system-power-controller; + }; + pinctrl: pinctrl@7d504100 { compatible = "brcm,bcm2712c0-pinctrl"; reg = <0x7d504100 0x30>; From 7c0b8360a4e2892bc1748aca77c0825af82f3dcd Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 28 Oct 2025 16:51:26 +0000 Subject: [PATCH 003/757] dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs Add clock definitions for XSPI0/1 to both R9A09G077 and R9A09G087 SoCs. These definitions are required for describing XSPI devices in DT Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251028165127.991351-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 2 ++ include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 2a805e06487b..9eaedca6a616 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -31,5 +31,7 @@ #define R9A09G077_ETCLKC 19 #define R9A09G077_ETCLKD 20 #define R9A09G077_ETCLKE 21 +#define R9A09G077_XSPI_CLK0 22 +#define R9A09G077_XSPI_CLK1 23 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 09da0ad33be6..606468ac49a4 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -31,5 +31,7 @@ #define R9A09G087_ETCLKC 19 #define R9A09G087_ETCLKD 20 #define R9A09G087_ETCLKE 21 +#define R9A09G087_XSPI_CLK0 22 +#define R9A09G087_XSPI_CLK1 23 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ From 5435398f67173ffb5ffdd003800976cf0975b518 Mon Sep 17 00:00:00 2001 From: Cosmo Chou Date: Sat, 18 Oct 2025 12:33:09 +0800 Subject: [PATCH 004/757] ARM: dts: aspeed: bletchley: remove WDTRST1 assertion from wdt1 Remove the external signal configuration from wdt1 to prevent the WDTRST1 pin from being asserted during watchdog resets. The WDTRST1 pin was originally configured to reset the TPM during watchdog events. However, the pin is incorrectly routed to SRST# on the hardware, causing unintended system resets. Since the TPM is not currently utilized on this platform, remove the external signal configuration to avoid the incorrect reset behavior. Signed-off-by: Cosmo Chou Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index 24969c82d05e..abdb1562115a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -1080,11 +1080,5 @@ &wdt1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; aspeed,reset-type = "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration = <256>; }; From 124b74e42ed3c4f1a72abbf71ff0a1a8f168ad6f Mon Sep 17 00:00:00 2001 From: Daniel Hsu Date: Fri, 17 Oct 2025 21:44:02 +0800 Subject: [PATCH 005/757] ARM: dts: aspeed: harma: add fanboard presence sgpio Add the SGPIO definition for detecting fanboard presence on the Harma platform. This allows the BMC to determine whether the fanboard is attached. Signed-off-by: Daniel Hsu Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts index 1c50e4a367b2..5602a502d07b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-harma.dts @@ -822,9 +822,13 @@ "irq-pvddcore1-ocp-alert","", "","", /*O4-O7 line 232-239*/ - "","","","","","","","", + "","","","", + "presence-lower-fanboard1","", + "presence-lower-fanboard2","", /*P0-P3 line 240-247*/ - "","","","","","","","", + "presence-upper-fanboard1","", + "presence-upper-fanboard2","", + "","","","", /*P4-P7 line 248-255*/ "","","","","","","",""; }; From 033089ff268b825316183aea655b0c8e99b11faf Mon Sep 17 00:00:00 2001 From: Leo Wang Date: Tue, 21 Oct 2025 11:15:39 +0800 Subject: [PATCH 006/757] ARM: dts: aspeed: clemente: Add EEPROMs for boot and data drive FRUs Add EEPROM devices on the I2C buses used for the boot and data NVMe drives. These EEPROMs store FRU information for each drive, allowing the BMC to identify. Signed-off-by: Leo Wang Signed-off-by: Andrew Jeffery --- .../aspeed/aspeed-bmc-facebook-clemente.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts index 450446913e36..885c50a7d665 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -311,6 +311,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + + // HDD NVMe SSD FRU 0 + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux0ch1mux0ch1: i2c@1 { @@ -323,6 +329,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; + + // HDD NVMe SSD FRU 1 + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux0ch1mux0ch3: i2c@3 { @@ -493,6 +505,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; + + // HDD NVMe SSD FRU 2 + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux3ch1mux0ch1: i2c@1 { @@ -505,6 +523,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; + + // HDD NVMe SSD FRU 3 + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux3ch1mux0ch3: i2c@3 { @@ -619,6 +643,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; + + // BOOT DRIVE FRU + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + }; }; i2c0mux5ch2: i2c@2 { From 22f8985f9594f0ee4d450e90095ed9cb612488fe Mon Sep 17 00:00:00 2001 From: Fred Chen Date: Tue, 25 Nov 2025 21:59:30 +0800 Subject: [PATCH 007/757] ARM: dts: aspeed: santabarbara: Add swb IO expander and gpio line names Add IO expander emulated by the switch board CPLD to handle UART and SPI mux control signals. Also add SGPIO labels with FM_MODULE_PWR_EN_N_* signals, which control power to each ASIC module individually. Signed-off-by: Fred Chen Signed-off-by: Andrew Jeffery --- .../aspeed-bmc-facebook-santabarbara.dts | 22 +++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts index f74f463cc878..4312ead311df 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts @@ -1328,6 +1328,20 @@ &i2c12 { status = "okay"; + gpio@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "PEX0_MODE_SEL1_R","PEX0_MODE_SEL2_R", + "PEX0_MODE_SEL3_R","PEX0_MODE_SEL4_R", + "","","","", + "UART_MUX_SEL","RST_SMB_NIC_R_N", + "RST_SMB_N","RST_CP2102N_N", + "SPI_MUX_SEL","","",""; + }; + // SWB FRU eeprom@52 { compatible = "atmel,24c64"; @@ -1758,11 +1772,11 @@ "","BIOS_DEBUG_MODE", /*H0-H3 line 112-119*/ "FM_IOEXP_U538_INT_N","", - "FM_IOEXP_U539_INT_N","", - "FM_IOEXP_U540_INT_N","", - "FM_IOEXP_U541_INT_N","", + "FM_IOEXP_U539_INT_N","FM_MODULE_PWR_EN_N_1B", + "FM_IOEXP_U540_INT_N","FM_MODULE_PWR_EN_N_2B", + "FM_IOEXP_U541_INT_N","FM_MODULE_PWR_EN_N_3B", /*H4-H7 line 120-127*/ - "FM_IOEXP_PDB2_U1003_INT_N","", + "FM_IOEXP_PDB2_U1003_INT_N","FM_MODULE_PWR_EN_N_4B", "","", "","", "FM_MAIN_PWREN_RMC_EN_ISO_R","", From 0cf964501fae7bda82c7f120f2ed8f848018b244 Mon Sep 17 00:00:00 2001 From: Fred Chen Date: Tue, 25 Nov 2025 21:59:31 +0800 Subject: [PATCH 008/757] ARM: dts: aspeed: santabarbara: Enable ipmb device for OCP debug card Add an IPMB node for OCP debug card to support IPMI communication. Signed-off-by: Fred Chen Signed-off-by: Andrew Jeffery --- .../boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts index 4312ead311df..0a3e2e241063 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-santabarbara.dts @@ -845,7 +845,14 @@ }; &i2c7 { + multi-master; status = "okay"; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; }; &i2c8 { From f3eb4690e5a61c71adc57d28788c8004aa5665a3 Mon Sep 17 00:00:00 2001 From: Kimi Chen Date: Tue, 25 Nov 2025 13:42:50 +0800 Subject: [PATCH 009/757] ARM: dts: aspeed: clemente: add gpio line name to io expander The chassis power cycle process requires a forced shutdown before cutting off the standby power. The SCM CPLD implements a hard shutdown host function that is controlled through the IO expander in the Clemente platform. This change adds a new GPIO line named "shdn_force_l_cpld" to the PCA9555 IO expander's gpio-line-names at index 10. When asserted, this GPIO signals the CPLD to pull the HPM's SHDN_FORCE_L pin low, which triggers a forced host shutdown. Signed-off-by: Kimi Chen Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts index 885c50a7d665..dfe8f6d0eeef 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -1013,7 +1013,7 @@ "", "", "", - "", + "shdn_force_l_cpld", "", "", "", From b89bbf3e5154d0ad024eabb994dabde3fb9e1d6c Mon Sep 17 00:00:00 2001 From: Alex Wang Date: Thu, 27 Nov 2025 17:44:51 +0800 Subject: [PATCH 010/757] ARM: dts: aspeed: clemente: move hdd_led to its own gpio-leds group The gpio-leds driver requires all GPIOs in a group to be available; if any GPIO in the group is not available the whole group will not be created. The hdd_led GPIO is only present after standby power is enabled, which can prevent other LEDs in the same group from being created and blocks properly setting 'bmc_ready_noled'. Move the 'hdd_led' node into a separate gpio-leds group so that other LEDs are not blocked and the 'bmc_ready_noled' flag can be set correctly. Fixes: b5dd16228216 ("ARM: dts: aspeed: clemente: Add HDD LED GPIO") Signed-off-by: Alex Wang Link: https://patch.msgid.link/20251127-leo-dts-add-shunt-resistor-v2-1-c77dfbfb826c@fii-foxconn.com [arj: Fix patch subject, add Fixes: tag] Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts index dfe8f6d0eeef..ea1bf6f402bd 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -96,7 +96,12 @@ gpios = <&gpio0 ASPEED_GPIO(P, 5) (GPIO_ACTIVE_HIGH|GPIO_TRANSITORY)>; }; - led-hdd { + }; + + hdd-leds { + compatible = "gpio-leds"; + + led-0 { label = "hdd_led"; gpios = <&io_expander13 1 GPIO_ACTIVE_LOW>; }; From 1daabbd6ff20a8b7e87e5eebe74bc7afeb855613 Mon Sep 17 00:00:00 2001 From: Marc Olberding Date: Wed, 26 Nov 2025 16:43:06 -0800 Subject: [PATCH 011/757] dt-bindings: arm: aspeed: Add NVIDIA MSX4 board Adds a compatible string for NVIDIA's MSX4 BMC board. Acked-by: Conor Dooley Signed-off-by: Marc Olberding Link: https://patch.msgid.link/20251126-msx1_devicetree-v5-1-e508d13e2dda@nvidia.com [arj: Consistent capitalisation in subject, grammar] Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 9298c1a75dd1..8a190819e066 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -107,6 +107,7 @@ properties: - inventec,transformer-bmc - jabil,rbp-bmc - nvidia,gb200nvl-bmc + - nvidia,msx4-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc - ufispace,ncplite-bmc From f28674fab34f07fff9612c3f390d3699bfe8ed90 Mon Sep 17 00:00:00 2001 From: Marc Olberding Date: Wed, 26 Nov 2025 16:43:07 -0800 Subject: [PATCH 012/757] ARM: dts: aspeed: Add NVIDIA MSX4 HPM The NVIDIA MSX4 HPM (host platform module) is a reference board for managing up to 8 PCIe connected NVIDIA GPUs via ConnectX-8 (CX8) SuperNICs. The BMC manages all GPUs and CX8s for both telemetry and firmware update via MCTP over USB. The host CPUs are dual socket Intel Granite Rapids processors. For more detail on this architecture: https://developer.nvidia.com/blog/nvidia-connectx-8-supernics-advance-ai-platform-architecture-with-pcie-gen6-connectivity/ Signed-off-by: Marc Olberding Link: https://patch.msgid.link/20251126-msx1_devicetree-v5-2-e508d13e2dda@nvidia.com [arj: Reflow text to wrap at limit, whitespace, grammar] Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts | 246 ++++++++++++++++++ 2 files changed, 247 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index 9adf9278dc94..ed25fec25fc4 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-nvidia-gb200nvl-bmc.dtb \ + aspeed-bmc-nvidia-msx4-bmc.dtb \ aspeed-bmc-opp-lanyang.dtb \ aspeed-bmc-opp-mowgli.dtb \ aspeed-bmc-opp-nicole.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts new file mode 100644 index 000000000000..44f95a3986cb --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-msx4-bmc.dts @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "AST2600 MSX4 BMC"; + compatible = "nvidia,msx4-bmc", "aspeed,ast2600"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + chosen { + stdout-path = "uart5:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + compatible = "shared-dma-pool"; + size = <0x01000000>; + alignment = <0x01000000>; + reusable; + }; + + video_engine_memory: jpegbuffer { + compatible = "shared-dma-pool"; + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + reusable; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + label = "bmc"; + status = "okay"; + #include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + compatible = "jedec,spi-nor"; + label = "alt-bmc"; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + status = "okay"; + }; +}; + +&gfx { + memory-region = <&gfx_memory>; + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "ASSERT_BMC_READY","","","","","","","", + /*C0-C7*/ "MON_PWR_GOOD","","","","","","","FP_ID_LED_N", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","","","","", + /*G0-G7*/ "","","FP_LED_STATUS_GREEN_N","FP_LED_STATUS_AMBER_N", + "","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "MON_PWR_BTN_L","ASSERT_PWR_BTN_L","MON_RST_BTN_L", + "ASSERT_RST_BTN_L","","ASSERT_NMI_BTN_L","","", + /*Q0-Q7*/ "","","MEMORY_HOT_0","MEMORY_HOT_1","","","","", + /*R0-R7*/ "ID_BTN","","","","","VBAT_GPIO","","", + /*S0-S7*/ "","","RST_PCA_MUX","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","","","","",""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ "","","","","","","","", + /*18B0-18B7*/ "","","","","","","","", + /*18C0-18C7*/ "","","","","","","","", + /*18D0-18D7*/ "","","","","","","","", + /*18E0-18E3*/ "","","BMC_INIT_DONE",""; +}; + +// Devices on these busses are available after POST +// however there isn't a great way to defer probing +// until that point today, as the BMC doesn't +// have direct control over when the host completes +// POST, especially from the kernel. +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c256"; + reg = <0x51>; + pagesize = <64>; + label = "sku"; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&kcs1 { + aspeed,lpc-io-reg = <0xca0>; + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8>; + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + status = "okay"; +}; + +&lpc_reset { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sgpiom0 { + ngpios = <80>; + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&video { + memory-region = <&video_engine_memory>; + status = "okay"; +}; From 64a55c5ee1fb359c31b8bcfae38334ec293f19cb Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 11 Dec 2025 17:45:49 +0900 Subject: [PATCH 013/757] ARM: dts: aspeed: Remove sdhci-drive-type property from AST2600 EVB The property isn't specified in the bindings and is not used by the corresponding driver, so drop it. Reviewed-by: Ulf Hansson Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts index de83c0eb1d6e..3eba676e57f1 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts @@ -314,7 +314,6 @@ status = "okay"; bus-width = <4>; max-frequency = <100000000>; - sdhci-drive-type = /bits/ 8 <3>; sdhci-caps-mask = <0x7 0x0>; sdhci,wp-inverted; vmmc-supply = <&vcc_sdhci0>; @@ -326,7 +325,6 @@ status = "okay"; bus-width = <4>; max-frequency = <100000000>; - sdhci-drive-type = /bits/ 8 <3>; sdhci-caps-mask = <0x7 0x0>; sdhci,wp-inverted; vmmc-supply = <&vcc_sdhci1>; From eedad0256832c5c1a851adac029d7bc97fbb2080 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 11 Dec 2025 17:45:50 +0900 Subject: [PATCH 014/757] ARM: dts: aspeed: Use specified wp-inverted property for AST2600 EVB While sdhci-pltfm supports sdhci,wp-inverted, it also supports the un-prefixed and specified wp-inverted property. Switch the EVB devicetree to use the specified property to remove warnings when checking the DTB. Reviewed-by: Ulf Hansson Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts index 3eba676e57f1..c51977dcb56b 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts @@ -315,7 +315,7 @@ bus-width = <4>; max-frequency = <100000000>; sdhci-caps-mask = <0x7 0x0>; - sdhci,wp-inverted; + wp-inverted; vmmc-supply = <&vcc_sdhci0>; vqmmc-supply = <&vccq_sdhci0>; clk-phase-sd-hs = <7>, <200>; @@ -326,7 +326,7 @@ bus-width = <4>; max-frequency = <100000000>; sdhci-caps-mask = <0x7 0x0>; - sdhci,wp-inverted; + wp-inverted; vmmc-supply = <&vcc_sdhci1>; vqmmc-supply = <&vccq_sdhci1>; clk-phase-sd-hs = <7>, <200>; From 938fb014f324b19b6e7105e1986a79d22eb0d2c3 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 11 Dec 2025 17:45:53 +0900 Subject: [PATCH 015/757] ARM: dts: aspeed: Drop syscon compatible from EDAC in g6 dtsi Its presence is not required by the binding, its addition was not discussed in commit aac82707fa45 ("ARM: dts: aspeed: Add AST2600 EDAC into common devicetree"), and its inconsistent with the g4 and g5 dtsis. Further, the corresponding driver instantiates its own regmap rather than fetching the syscon regmap, in theory breaking any users of the syscon, but of which there appear to be none in-tree. Drop it for now, and we can add it back with the necessary rework if it's ever required. Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index f8662c8ac089..0ddca4bfffd3 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -74,7 +74,7 @@ }; edac: sdram@1e6e0000 { - compatible = "aspeed,ast2600-sdram-edac", "syscon"; + compatible = "aspeed,ast2600-sdram-edac"; reg = <0x1e6e0000 0x174>; interrupts = ; }; From a9360cbd6189666b0b4e10ca63a4b137ed5362ba Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 11 Dec 2025 17:45:54 +0900 Subject: [PATCH 016/757] ARM: dts: aspeed: g6: Drop unspecified aspeed,ast2600-udma node There's neither a binding defined nor a driver that matches on the compatible, so drop it from the devicetree until someone is motivated to solve the problems. Signed-off-by: Andrew Jeffery --- .../arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts | 4 ---- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 9 --------- 2 files changed, 13 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts index ea1bf6f402bd..2aff21442f11 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts @@ -1293,10 +1293,6 @@ use-ncsi; }; -&udma { - status = "okay"; -}; - &uart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 0ddca4bfffd3..bcb4ebcfcc67 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -866,15 +866,6 @@ interrupt-controller; status = "disabled"; }; - - udma: dma-controller@1e79e000 { - compatible = "aspeed,ast2600-udma"; - reg = <0x1e79e000 0x1000>; - interrupts = ; - dma-channels = <28>; - #dma-cells = <1>; - status = "disabled"; - }; }; }; }; From 41aca6b6d4f6541dbe37b85ef0c59660e538db56 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 11 Dec 2025 17:45:55 +0900 Subject: [PATCH 017/757] ARM: dts: aspeed: ast2600-evb: Tidy up A0 work-around for UART5 Changing the compatible changes the properties allowed - snps,dw-apb-uart doesn't specify no-loopback-test, so remove it. Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts index c51977dcb56b..3f2ca9da0be2 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-ast2600-evb.dts @@ -205,6 +205,7 @@ &uart5 { // Workaround for A0 compatible = "snps,dw-apb-uart"; + /delete-property/ no-loopback-test; }; &i2c0 { From e0808393bf81b437eac734edc9d812fd30f12190 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 11 Dec 2025 17:45:57 +0900 Subject: [PATCH 018/757] ARM: dts: aspeed: g6: Drop clocks property from arm,armv7-timer The property is not specified by the binding, nor used by the driver. Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index bcb4ebcfcc67..189bc3bbb47c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -68,7 +68,6 @@ , , ; - clocks = <&syscon ASPEED_CLK_HPLL>; arm,cpu-registers-not-fw-configured; always-on; }; From 796010d53f992efcb549381d4055d5ff7226154c Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 1 Oct 2025 19:31:13 +0100 Subject: [PATCH 019/757] arm64: dts: xilinx: add soc-specific spi compatibles for zynqmp/versal-net Unlike zynq, which has a specific compatible for the Cadence spi controller, zynqmp and versal-net do not have specific compatibles. In order to "encourage" people to use soc-specific compatibles for new devices using this IP, add specific compatibles for these devices, with a fallback to the existing compatible for the r1p6 version of the IP so that there will be no functional change. Signed-off-by: Conor Dooley Acked-by: Michal Simek Link: https://lore.kernel.org/r/20251001-cheesy-shucking-c55431bbcae3@spud Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/versal-net.dtsi | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi index 412af9a394aa..15f767608e67 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -1018,7 +1018,7 @@ }; spi0: spi@f1960000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; @@ -1026,7 +1026,7 @@ }; spi1: spi@f1970000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 938b014ca923..4486c67b2a30 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -1080,7 +1080,7 @@ }; spi0: spi@ff040000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = ; @@ -1092,7 +1092,7 @@ }; spi1: spi@ff050000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = ; From 801c03446205af4c94736b4892805c10697e6f61 Mon Sep 17 00:00:00 2001 From: Harini T Date: Thu, 30 Jan 2025 17:32:33 +0530 Subject: [PATCH 020/757] dt-bindings: watchdog: xlnx,versal-wwdt: Add optional power-domains property AMD/Xilinx Versal Window Watchdog Timer has its own power domain, so add an optional property to describe it. Signed-off-by: Harini T Acked-by: Conor Dooley Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20250130120233.742879-1-harini.t@amd.com --- .../devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml b/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml index 14b069599740..fccfc785a077 100644 --- a/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml @@ -32,6 +32,9 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg From 138cb5c1bc67058542ea83109dd6e2d0d2451528 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Tue, 11 Nov 2025 07:05:55 +0000 Subject: [PATCH 021/757] arm64: dts: xilinx: fix zynqmp opp-table-cpu Since the following commit, the zynqmp clk driver uses the common divider_round_rate() when determining the appropriate clock divider for a requested clock frequency: https://github.com/torvalds/linux/commit/1fe15be1fb613534ecbac5f8c3f8744f757d237d This means that all the calculations will be in kHz when determining the appropriate clock divider for a given cpufreq request. The problem with this is that the zynqmp.dtsi and zynqmp-clk-ccf.dtsi files have frequency definitions in Hz, so when dividing requested values in kHz, errors can occur with the rounding. For example, the current pss_ref_clk frequency is 33333333 Hz which generates a cpufreq parent clock frequency of 1199999988 Hz which is the same as the highest opp-table-cpu frequency in the zynqmp.dtsi. But if a user requests the value 1199999 kHz as recommended in the available frequencies: root@zynqmp:/sys/kernel/tracing# cat /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies 299999 399999 599999 1199999 root@zynqmp:/ # echo 1199999 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed The calculation will be: 1199999988 / 1199999000 = 1.000001 This will get rounded up to a divider value of 2 giving the following result. root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq 599999 Also, if a user tries to work around this calculation by using any larger values, it still will not fix the problem because the driver will use the largest opp in kHz which leads to the same calculation error. User requests 1200000 root@zynqmp:/ # echo 1200000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed Driver converts any value greater than 1199999 to the largest opp which is 1199999 and then calculates the divider value with the same calculation. The calculation will still be: 1199999988 / 1199999000 = 1.000001 This will get rounded up to a divider value of 2 giving the following result. root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq 599999 This means there is no way to configure the zynqmp for the fastest opp using the current dtsi files. To fix this issue, this patch updates the zynqmp opp-table-cpu and pss_ref_clk, so the clock rates are calculated correctly. root@zynqmp:/sys/kernel/tracing# cat /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies 300000 400000 600000 1200000 root@zynqmp:/ # echo 1200000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq 1200000 Signed-off-by: Neal Frager Acked-by: Jay Buddhabhatti Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20251111070555.1169130-1-neal.frager@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 52e122fc7c9e..482f432ba7f3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -14,7 +14,7 @@ bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <33333333>; + clock-frequency = <33333000>; clock-output-names = "pss_ref_clk"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 4486c67b2a30..4dfcaa9927b0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -103,23 +103,23 @@ cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; - opp00 { - opp-hz = /bits/ 64 <1199999988>; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp01 { - opp-hz = /bits/ 64 <599999994>; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp02 { - opp-hz = /bits/ 64 <399999996>; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp03 { - opp-hz = /bits/ 64 <299999997>; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; From 01a23e376e2afd578c5ecb8c8263e107de3240b9 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Tue, 27 May 2025 13:55:39 +0100 Subject: [PATCH 022/757] arm64: dts: morello: Add CMN PMU Although CMN-Skeena is mildly modified for the Morello hardware architecture, it still identifies itself as CMN-600 r3p1. Since there are also no documented changes to its PMU functionality, we can make the PMU accessible via the standard CMN-600 binding. In general, PMU registers are non-functional on CMN Fast Models, so this is only meaningful for the real SDP hardware. Signed-off-by: Robin Murphy Acked-by: Vincenzo Frascino Message-Id: Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/morello-sdp.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts index cee49dee7571..42c85f450fa9 100644 --- a/arch/arm64/boot/dts/arm/morello-sdp.dts +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -108,6 +108,13 @@ dma-coherent; }; + pmu@50000000 { + compatible = "arm,cmn-600"; + reg = <0x0 0x50000000 0x0 0x4000000>; + interrupts = ; + arm,root-node = <0x804000>; + }; + pcie_ctlr: pcie@28c0000000 { device_type = "pci"; compatible = "pci-host-ecam-generic"; From 87c83a27b80062d0ca5dca408b7a7db42027a582 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 16 Sep 2025 16:02:43 +0100 Subject: [PATCH 023/757] arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes Add USB3 PHY/Host nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250916150255.4231-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 7a469de3bb62..d1bf16c6ff6b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -853,6 +853,36 @@ interrupts = ; }; + xhci: usb@15850000 { + compatible = "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy: usb-phy@15870000 { + compatible = "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G047_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G047_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; From 6ea91acf0f67a7e6dd1e899955346e00778d7b0f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 16 Sep 2025 16:02:44 +0100 Subject: [PATCH 024/757] arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST Enable USB3.2 Gen2 Host controller(a.k.a USB3HOST) on the RZ/G3E SMARC EVK platform. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250916150255.4231-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 10 ++++++++++ arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 08e814c03fa8..0fd90d79b020 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -164,6 +164,11 @@ ; /* SD1DAT3 */ }; }; + + usb3_pins: usb3 { + pinmux = , /* USB30_VBUSEN */ + ; /* USB30_OVRCURN */ + }; }; &scif0 { @@ -179,3 +184,8 @@ vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sd1_pvdd>; }; + +&xhci { + pinctrl-0 = <&usb3_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index 58561da3007a..8b3765b8267d 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -106,3 +106,11 @@ status = "okay"; }; + +&usb3_phy { + status = "okay"; +}; + +&xhci { + status = "okay"; +}; From e74470cf3101da79666f20186c9406192223e9a8 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Fri, 5 Sep 2025 16:19:25 +0000 Subject: [PATCH 025/757] ARM: dts: rockchip: Add vdec node for RK3288 RK3288 contains a Rockchip VDEC block that only support HEVC decoding. Add a vdec node for this. Signed-off-by: Alex Bee Signed-off-by: Jonas Karlman Link: https://patch.msgid.link/20250905161942.3759717-8-jonas@kwiboo.se Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi index 7477fc5da3ec..4e5e7509de48 100644 --- a/arch/arm/boot/dts/rockchip/rk3288.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi @@ -1288,6 +1288,21 @@ power-domains = <&power RK3288_PD_VIDEO>; }; + hevc: video-codec@ff9c0000 { + compatible = "rockchip,rk3288-vdec"; + reg = <0x0 0xff9c0000 0x0 0x440>; + interrupts = ; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, + <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; + assigned-clock-rates = <400000000>, <100000000>, + <300000000>, <300000000>; + iommus = <&hevc_mmu>; + power-domains = <&power RK3288_PD_HEVC>; + }; + hevc_mmu: iommu@ff9c0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; @@ -1295,7 +1310,7 @@ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3288_PD_HEVC>; }; gpu: gpu@ffa30000 { From 47b5d3697f6b9f53a0db30a99656a2f8f919e246 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 2 Dec 2025 13:54:31 +0400 Subject: [PATCH 026/757] arm64: dts: rockchip: Add overlay for the PCIe slot on RK3576 EVB1 Rockchip RK3576 EVB1 has an onboard PCIe slot (PCIe 2.1, x4 mechanically, x1 electrically), but it shares pins and PHY with the only USB3 Type-A port. There is a physical switch next to the slot to transfer respective pins connection from the USB3 port to the PCIe slot, but apart from flipping the switch one must also disable the USB3 host controller to prevent it from claiming the PHY before the PCIe slot can become usable. Add an overlay to disable the USB3 host port and instead enable the PCIe slot, along with its pin configs. The physical switch must still be flipped to the "ON - PCIe1" position for this to work. Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251202-evb1-pcie1-v2-1-810693b1b72f@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 +++ .../dts/rockchip/rk3576-evb1-v10-pcie1.dtso | 31 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index dbdda9783e93..3fdd1e4832e1 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-100ask-dshanpi-a1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb @@ -259,6 +260,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtb rk3576-armsom-sige5-v1.2-wifibt-dtbs := rk3576-armsom-sige5.dtb \ rk3576-armsom-sige5-v1.2-wifibt.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtb +rk3576-evb1-v10-pcie1-dtbs := rk3576-evb1-v10.dtb \ + rk3576-evb1-v10-pcie1.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \ rk3588-edgeble-neu6a-wifi.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso new file mode 100644 index 000000000000..dccf4a5debdb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to enable the onboard PCIe x1 slot, which shares pins and the PHY + * with the USB3 host port. + * To use the PCIe slot, apply this overlay and flip the Dial_Switch_1 right + * next to the PCIe slot to low state (labeled "ON - PCIe1"). USB3 host port + * will be unusable (not even in 2.0 mode) + */ + +/dts-v1/; +/plugin/; + +#include + +&pcie1 { + pinctrl-0 = <&pcie1m0_pins &pcie1_rst>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pinctrl { + pcie1 { + pcie1_rst: pcie1-rst { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&usb_drd1_dwc3 { + status = "disabled"; +}; From 2cc30da80a28a8a5d1337230c3586eb2f9580120 Mon Sep 17 00:00:00 2001 From: Torsten Duwe Date: Mon, 24 Nov 2025 19:30:56 +0100 Subject: [PATCH 027/757] arm64: dts: rockchip: Enable SPDIF audio on Rock 5 ITX The Rock5 ITX has an S/PDIF (TOSLINK) socket in its I/O-shield, whose TX signal is wired to GPIO4 C1. Activate SPDIF TX unit 1 and select the proper pinmux (M2). Signed-off-by: Torsten Duwe Link: https://patch.msgid.link/20251124183056.B853068C4E@verein.lst.de Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-rock-5-itx.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts index 172aeabba72a..de154adb1497 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts @@ -147,6 +147,24 @@ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; }; + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; + typec_vin: regulator-typec-vin { compatible = "regulator-fixed"; enable-active-high; @@ -854,6 +872,11 @@ }; }; +&spdif_tx1 { + pinctrl-0 = <&spdif1m2_tx>; + status = "okay"; +}; + &spi2 { status = "okay"; assigned-clocks = <&cru CLK_SPI2>; From abd9bb7ad5bdbbf76316013cda3812c2719a0210 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 24 Nov 2025 19:47:01 -0800 Subject: [PATCH 028/757] arm64: dts: rockchip: Add accelerometer sensor to Pinephone Pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pinephone Pro uses mpu6500 according to the schematic. This was verified via `monitor-sensor --accel`. While rotating the device, the output was correct (eg. when it was face up, left edge was up, vertical, etc.). Co-developed-by: Martijn Braam Signed-off-by: Martijn Braam Co-developed-by: Kamil Trzciński Signed-off-by: Kamil Trzciński Signed-off-by: Ondrej Jirman Signed-off-by: Rudraksha Gupta Reviewed-by: Pavel Machek Link: https://patch.msgid.link/20251124-ppp_light_accel_mag_vol-down-v5-2-f9a10a0a50eb@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 2dca1dca20b8..5e9867e934d2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -533,7 +533,13 @@ reg = <0x68>; interrupt-parent = <&gpio1>; interrupts = ; + vdd-supply = <&vcc_1v8>; vddio-supply = <&vcc_1v8>; + + mount-matrix = + "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; }; }; From c197179990124f991fca220d97fac56779a02c6d Mon Sep 17 00:00:00 2001 From: Tomas Melin Date: Tue, 25 Nov 2025 09:53:54 +0200 Subject: [PATCH 029/757] Revert "arm64: zynqmp: Add an OP-TEE node to the device tree" This reverts commit 06d22ed6b6635b17551f386b50bb5aaff9b75fbe. OP-TEE logic in U-Boot automatically injects a reserved-memory node along with optee firmware node to kernel device tree. The injection logic is dependent on that there is no manually defined optee node. Having the node in zynqmp.dtsi effectively breaks OP-TEE's insertion of the reserved-memory node, causing memory access violations during runtime. Signed-off-by: Tomas Melin Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20251125-revert-zynqmp-optee-v1-1-d2ce4c0fcaf6@vaisala.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 4dfcaa9927b0..29058e633fe9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -192,11 +192,6 @@ }; firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; From af8dbb88188784cfcdc215487e0173a6f62caf52 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 Dec 2025 07:35:47 +0100 Subject: [PATCH 030/757] arm64: dts: toshiba: tmpv7708: Align node names with DT bindings DT bindings expect node names to follow certain pattern, dtbs_check warnings: tmpv7708-rm-mbrc.dtb: pmux@24190000 (toshiba,tmpv7708-pinctrl): 'pwm_mux' does not match any of the regexes: '-pins$', '^pinctrl-[0-9]+$' tmpv7708-rm-mbrc.dtb pmux@24190000 (toshiba,tmpv7708-pinctrl): $nodename:0: 'pmux@24190000' does not match '^(pinctrl|pinmux)(@[0-9a-f]+)?$' tmpv7708-rm-mbrc.dtb: wdt@28330000 (toshiba,visconti-wdt): $nodename:0: 'wdt@28330000' does not match '^(timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$' Reviewed-by: Nobuhiro Iwamatsu Link: https://patch.msgid.link/20251022133616.74492-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 4 ++-- arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 9aa7b1872bd6..88e38d6efcaa 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -161,7 +161,7 @@ <0 0x24006000 0 0x2000>; }; - pmux: pmux@24190000 { + pmux: pinctrl@24190000 { compatible = "toshiba,tmpv7708-pinctrl"; reg = <0 0x24190000 0 0x10000>; }; @@ -463,7 +463,7 @@ status = "disabled"; }; - wdt: wdt@28330000 { + wdt: watchdog@28330000 { compatible = "toshiba,visconti-wdt"; reg = <0 0x28330000 0 0x1000>; clocks = <&pismu TMPV770X_CLK_WDTCLK>; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi index a480c6ba5f5d..5ea835fe08a8 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708_pins.dtsi @@ -91,7 +91,7 @@ bias-pull-up; }; - pwm_mux: pwm_mux { + pwm_mux: pwm-pins { function = "pwm"; }; From d9465635e051ddc0d9ebb312174ace55d38d2d40 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 24 Oct 2025 17:57:34 +0000 Subject: [PATCH 031/757] dt-bindings: rng: add google,gs101-trng compatible Add support for the TRNG found on GS101. It works well with the current exynos850 TRNG support. The TRNG controller can be part of a power domain, allow the relevant property 'power-domains'. Signed-off-by: Tudor Ambarus Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251024-gs101-trng-v3-1-5d3403738f39@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/rng/samsung,exynos5250-trng.yaml | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml b/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml index 1a71935d8a19..699831927932 100644 --- a/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml +++ b/Documentation/devicetree/bindings/rng/samsung,exynos5250-trng.yaml @@ -12,9 +12,13 @@ maintainers: properties: compatible: - enum: - - samsung,exynos5250-trng - - samsung,exynos850-trng + oneOf: + - enum: + - samsung,exynos5250-trng + - samsung,exynos850-trng + - items: + - const: google,gs101-trng + - const: samsung,exynos850-trng clocks: minItems: 1 @@ -24,6 +28,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + reg: maxItems: 1 From d45eafec01fa31fb9ab30902de35fbbe70f63411 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 24 Oct 2025 17:57:35 +0000 Subject: [PATCH 032/757] arm64: dts: exynos: gs101: add TRNG node Define the TRNG node. GS101 TRNG works well with the current Exynos850 TRNG support. Specify the Google specific compatible in front of the Exynos one. Signed-off-by: Tudor Ambarus Link: https://patch.msgid.link/20251024-gs101-trng-v3-2-5d3403738f39@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index d06d1d05f364..380f7e70910a 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -630,6 +630,15 @@ status = "disabled"; }; + trng: rng@10141400 { + compatible = "google,gs101-trng", + "samsung,exynos850-trng"; + reg = <0x10141400 0x100>; + clocks = <&cmu_misc CLK_GOUT_MISC_SSS_I_ACLK>, + <&cmu_misc CLK_GOUT_MISC_SSS_I_PCLK>; + clock-names = "secss", "pclk"; + }; + gic: interrupt-controller@10400000 { compatible = "arm,gic-v3"; #address-cells = <0>; From 411727d9182d7a067fdd16a125d2069f52e8bb7f Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 14 Nov 2025 12:00:16 +0000 Subject: [PATCH 033/757] dt-bindings: soc: samsung: exynos-pmu: remove syscon for google,gs101-pmu Since commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes without a "syscon" compatible") it is possible to register a regmap without the syscon compatible in the node. Update the bindings for google,gs101-pmu so that the syscon compatible is no longer required. As it isn't really correct to claim we are compatible with syscon (as a mmio regmap created by syscon will not work on gs101). Additionally (with the benefit of hindsight) PMU register writes were never working with a MMIO syscon on gs101, so the ABI break is justified. Signed-off-by: Peter Griffin Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251114-remove-pmu-syscon-compat-v2-1-9496e8c496c7@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 6de47489ee42..936352a6110f 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -34,9 +34,10 @@ select: properties: compatible: oneOf: + - enum: + - google,gs101-pmu - items: - enum: - - google,gs101-pmu - samsung,exynos3250-pmu - samsung,exynos4210-pmu - samsung,exynos4212-pmu From a21d38b5e209c60e73f81e467cc53ad57b5d4080 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Fri, 14 Nov 2025 12:00:17 +0000 Subject: [PATCH 034/757] arm64: dts: exynos: gs101: remove syscon compatible from pmu node Since commit ba5095ebbc7a ("mfd: syscon: Allow syscon nodes without a "syscon" compatible") it is possible to register a regmap without the syscon compatible in the node. As mentioned in that commit, it's not correct to claim we are compatible with syscon, as a MMIO regmap created by syscon won't work. Removing the syscon compatible means syscon driver won't ever create a mmio regmap. Note this isn't usually an issue today as exynos-pmu runs at an early initcall so the custom regmap will have been registered first. However changes proposed in [1] will bring -EPROBE_DEFER support to syscon allowing this mechanism to be more robust, especially in highly modularized systems. Technically this is a ABI break but no other platforms are affected. Additionally (with the benefit of hindsight) a MMIO syscon has never worked for PMU register writes, thus the ABI break is justified. Link: https://lore.kernel.org/lkml/aQdHmrchkmOr34r3@stanley.mountain/ [1] Signed-off-by: Peter Griffin Link: https://patch.msgid.link/20251114-remove-pmu-syscon-compat-v2-2-9496e8c496c7@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 380f7e70910a..9b38c2248016 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1714,7 +1714,7 @@ }; pmu_system_controller: system-controller@17460000 { - compatible = "google,gs101-pmu", "syscon"; + compatible = "google,gs101-pmu"; reg = <0x17460000 0x10000>; google,pmu-intr-gen-syscon = <&pmu_intr_gen>; From d468b7b8a6fe3d21df5a186d04f9d6124ef66d4d Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Mon, 24 Nov 2025 01:08:41 -0800 Subject: [PATCH 035/757] arm64: dts: ti: k3-am62-phycore-som: Add bootphase tag to cpsw_mac_syscon Add the "bootph-all" boot phase property to cpsw_mac_syscon. This fuse region contains the internal MAC address. Without this syscon node enabled, this interface will get a random MAC during network boot. This is problematic because the AM62x network boot is using BOOTP protocol for some binaries and this protocol does not support dynamic lease expiration. Therefore, the DHCP server can run out of free IP addresses. Signed-off-by: Daniel Schultz Reviewed-by: Wadim Egorov Link: https://patch.msgid.link/20251124090842.3377294-1-d.schultz@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 878d267bc663..b7eb538b19b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -220,6 +220,10 @@ bootph-all; }; +&cpsw_mac_syscon { + bootph-all; +}; + &cpsw3g_mdio { pinctrl-names = "default"; pinctrl-0 = <&main_mdio1_pins_default>; From a9bd8d35a88e0bf72ebf5a803eb4c7f8e4731e3e Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Mon, 24 Nov 2025 01:08:42 -0800 Subject: [PATCH 036/757] arm64: dts: ti: k3-am62a-phycore-som: Add bootphase tag to cpsw_mac_syscon Add the "bootph-all" property to cpsw_mac_syscon. This fuse region contains the internal MAC address. Without this syscon node enabled, this interface will get a random MAC during network boot. This is problematic because the AM62Ax network boot is using BOOTP protocol for some binaries and this protocol does not support dynamic lease expiration. Therefore, the DHCP server can run out of free IP addresses. Signed-off-by: Daniel Schultz Reviewed-by: Wadim Egorov Link: https://patch.msgid.link/20251124090842.3377294-2-d.schultz@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index b24a63feeab8..24afbfe44659 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -197,6 +197,10 @@ bootph-all; }; +&cpsw_mac_syscon { + bootph-all; +}; + &cpsw3g_mdio { pinctrl-names = "default"; pinctrl-0 = <&main_mdio1_pins_default>; From e05f6566bc778bc1215283e667e18692d16b25f5 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Mon, 24 Nov 2025 17:05:48 +0100 Subject: [PATCH 037/757] arm64: dts: ti: k3-am62(a)-phycore-som: Add bootphase tag to phy_gmii_sel Add the bootph-all property to the phy_gmii_sel node to ensure it is available during all boot phases. This is required when the bootloader is getting booted via network. Signed-off-by: Wadim Egorov Link: https://patch.msgid.link/20251124160548.2273931-1-w.egorov@phytec.de Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index b7eb538b19b7..e15da771bc07 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -363,6 +363,10 @@ }; }; +&phy_gmii_sel { + bootph-all; +}; + &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 24afbfe44659..de4048a3564b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -354,6 +354,10 @@ }; }; +&phy_gmii_sel { + bootph-all; +}; + &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&main_mmc0_pins_default>; From 36ee9f8b1ae07fe82885a7a3553a5be347d3f978 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 4 Dec 2025 14:42:18 +0100 Subject: [PATCH 038/757] arm64: dts: ti: k3-am69-aquila-dev: Fix USB-C Sink PDO Change USB-C Sink PDO and the amount of power that the device can sink to zero to maximize compatibility with other USB peers (the Aquila Development Board is not sinking any current, it is self powered). Fixes: 39ac6623b1d8 ("arm64: dts: ti: Add Aquila AM69 Support") Signed-off-by: Francesco Dolcini Link: https://patch.msgid.link/20251204134220.129304-2-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts b/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts index c7ce804eac70..f48601ae38b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-dev.dts @@ -399,8 +399,8 @@ try-power-role = "sink"; self-powered; source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <1000000>; + sink-pdos = ; + op-sink-microwatt = <0>; ports { #address-cells = <1>; From b548f3949937b55ee19ab418343f05700fdf7009 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 4 Dec 2025 14:42:19 +0100 Subject: [PATCH 039/757] arm64: dts: ti: k3-am69-aquila-clover: Fix USB-C Sink PDO Change USB-C Sink PDO and the amount of power that the device can sink to zero to maximize compatibility with other USB peers (the Aquila Clover Board is not sinking any current, it is self powered). Fixes: 9f748a6177e1 ("arm64: dts: ti: am69-aquila: Add Clover") Signed-off-by: Francesco Dolcini Link: https://patch.msgid.link/20251204134220.129304-3-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts index 55fd214a82e4..c816ba3bfbdf 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts @@ -280,8 +280,8 @@ try-power-role = "sink"; self-powered; source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <1000000>; + sink-pdos = ; + op-sink-microwatt = <0>; ports { #address-cells = <1>; From de86dbc0fb00bd3773db4b05d9f5926f0faa2244 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 09:41:25 +0100 Subject: [PATCH 040/757] arm64: dts: ti: am62p-verdin: Fix SD regulator startup delay The power switch used to power the SD card interface might have more than 2ms turn-on time, increase the startup delay to 20ms to prevent failures. Fixes: 87f95ea316ac ("arm64: dts: ti: Add Toradex Verdin AM62P") Cc: stable@vger.kernel.org Signed-off-by: Francesco Dolcini Link: https://patch.msgid.link/20251209084126.33282-1-francesco@dolcini.it Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index 5e050cbb9eaf..ec9dd931fe92 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -112,7 +112,7 @@ regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; + startup-delay-us = <20000>; }; reg_sd1_vqmmc: regulator-sdhci1-vqmmc { From faf317d4c705b426018fa29a14e411ec037b7560 Mon Sep 17 00:00:00 2001 From: Sven Peter Date: Mon, 15 Dec 2025 19:37:50 +1000 Subject: [PATCH 041/757] arm64: dts: apple: t8103,t60xx,t8112: Add SMC RTC node The System Manager Controller of all M1/M2 SoCs supports the RTC sub-device. Reviewed-by: Neal Gompa Signed-off-by: James Calligeros Link: https://patch.msgid.link/20251215-macsmc-subdevs-v6-6-0518cb5f28ae@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-die0.dtsi | 6 ++++++ arch/arm64/boot/dts/apple/t602x-die0.dtsi | 6 ++++++ arch/arm64/boot/dts/apple/t8103.dtsi | 6 ++++++ arch/arm64/boot/dts/apple/t8112.dtsi | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi index 3603b276a2ab..f715b19efd16 100644 --- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi @@ -44,6 +44,12 @@ nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; smc_mbox: mbox@290408000 { diff --git a/arch/arm64/boot/dts/apple/t602x-die0.dtsi b/arch/arm64/boot/dts/apple/t602x-die0.dtsi index 2e7d2bf08ddc..8622ddea7b44 100644 --- a/arch/arm64/boot/dts/apple/t602x-die0.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-die0.dtsi @@ -121,6 +121,12 @@ nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; pinctrl_smc: pinctrl@2a2820000 { diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 8b7b27887968..59f2678639cf 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -916,6 +916,12 @@ nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; smc_mbox: mbox@23e408000 { diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index 3f79878b25af..6bc3f58b06f7 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -919,6 +919,12 @@ nvmem-cell-names = "shutdown_flag", "boot_stage", "boot_error_count", "panic_count"; }; + + rtc { + compatible = "apple,smc-rtc"; + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "rtc_offset"; + }; }; smc_mbox: mbox@23e408000 { From 7d1974ce80fc386834e5667b0f579c2c766c4faa Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Thu, 11 Dec 2025 14:19:45 +0530 Subject: [PATCH 042/757] arm64: dts: qcom: x1e80100: Add crypto engine On X Elite, there is a crypto engine IP block similar to ones found on SM8x50 platforms. Describe the crypto engine and its BAM. Tested-by: Wenjia Zhang Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20251211-crypto_dt_node_x1e80100-v6-1-03830ed53352@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index a17900eacb20..bb7c14d473c9 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3845,6 +3845,32 @@ status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0x0 0x01dc4000 0x0 0x28000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + qcom,ee = <0>; + qcom,controlled-remotely; + num-channels = <20>; + qcom,num-ees = <4>; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", + "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>; From 9f76530e52b51a93643dfd2aa893caf00047a563 Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:03 +0100 Subject: [PATCH 043/757] dt-bindings: vendor-prefixes: Add prefix for TUXEDO Computers GmbH TUXEDO Computers GmbH is a German supplier for computers. Signed-off-by: Georg Gottleuber Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251204155212.230058-2-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..07b024dcff90 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1697,6 +1697,8 @@ patternProperties: description: Theobroma Systems Design und Consulting GmbH "^turing,.*": description: Turing Machines, Inc. + "^tuxedo,.*": + description: TUXEDO Computers GmbH "^tyan,.*": description: Tyan Computer Corporation "^tyhx,.*": From 32d68e51bf492580bc2b84adcad8a20427d4b2a0 Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:04 +0100 Subject: [PATCH 044/757] dt-bindings: arm: qcom: Add TUXEDO Computers device Introduce new binding for the TUXEDO Elite 14 Gen1 laptop with X1E78100 SoC. Signed-off-by: Georg Gottleuber Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251204155212.230058-3-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index d84bd3bca201..52ec9e6bd14d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1067,6 +1067,12 @@ properties: - const: qcom,x1e78100 - const: qcom,x1e80100 + - items: + - enum: + - tuxedo,elite14gen1 + - const: qcom,x1e78100 + - const: qcom,x1e80100 + - items: - enum: - asus,vivobook-s15 From a4c5af1a94c401e99d7eb22707dd848d54bff80d Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:05 +0100 Subject: [PATCH 045/757] dt-bindings: vendor-prefixes: Add Medion AG Add Medion AG, a German electronics company, to the list of vendor prefixes. Link: https://www.medion.com/ Signed-off-by: Georg Gottleuber Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251204155212.230058-4-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 07b024dcff90..b7c6c528e018 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -995,6 +995,8 @@ patternProperties: description: Mustek Limited "^mediatek,.*": description: MediaTek Inc. + "^medion,.*": + description: Medion AG "^megachips,.*": description: MegaChips "^mele,.*": From 5851f2a20c60dd5aa39b99e4872e96ce358598b6 Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:06 +0100 Subject: [PATCH 046/757] dt-bindings: arm: qcom: Add Medion SPRCHRGD device Introduce new binding for the Medion SPRCHRGD 14 S1 notebook with X1E78100 SoC. Signed-off-by: Georg Gottleuber Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251204155212.230058-5-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 52ec9e6bd14d..13ca0cf5ac7e 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1069,6 +1069,7 @@ properties: - items: - enum: + - medion,sprchrgd14s1 - tuxedo,elite14gen1 - const: qcom,x1e78100 - const: qcom,x1e80100 From 8cf65490cdb03c0254448a54f9098686bf9029ec Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:07 +0100 Subject: [PATCH 047/757] arm64: dts: qcom: Add dts for Medion SPRCHRGD 14 S1 Initial support for the Medion SPRCHRGD 14 S1, which is based on the Qualcomm Snapdragon X Elite SoC (X1E78100). Working: * Touchpad * Keyboard * eDP * NVMe * USB Type-C port * USB-C DP altmode * HDMI-A port * WiFi * Bluetooth * GPU * Video decoding * USB Type-A * Audio, speakers, microphones - 4x speakers. - 2x dmic - headset * Camera * Fingerprint reader Co-developed-by: Srinivas Kandagatla Signed-off-by: Srinivas Kandagatla Co-developed-by: Ettore Chimenti Signed-off-by: Ettore Chimenti Signed-off-by: Georg Gottleuber Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251204155212.230058-6-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../qcom/x1e80100-medion-sprchrgd-14-s1.dts | 1515 +++++++++++++++++ 2 files changed, 1517 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6f34d5ed331c..0b4d29d08783 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -346,6 +346,8 @@ x1e80100-hp-omnibook-x14-el2-dtbs := x1e80100-hp-omnibook-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-hp-omnibook-x14.dtb x1e80100-hp-omnibook-x14-el2.dtb x1e80100-lenovo-yoga-slim7x-el2-dtbs := x1e80100-lenovo-yoga-slim7x.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-lenovo-yoga-slim7x.dtb x1e80100-lenovo-yoga-slim7x-el2.dtb +x1e80100-medion-sprchrgd-14-s1-el2-dtbs := x1e80100-medion-sprchrgd-14-s1.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1e80100-medion-sprchrgd-14-s1.dtb x1e80100-medion-sprchrgd-14-s1-el2.dtb x1e80100-microsoft-romulus13-el2-dtbs := x1e80100-microsoft-romulus13.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1e80100-microsoft-romulus13.dtb x1e80100-microsoft-romulus13-el2.dtb x1e80100-microsoft-romulus15-el2-dtbs := x1e80100-microsoft-romulus15.dtb x1-el2.dtbo diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts new file mode 100644 index 000000000000..9155435484fb --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -0,0 +1,1515 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 TUXEDO Computers GmbH + */ + +/dts-v1/; + +#include +#include + +#include "hamoa.dtsi" +#include "hamoa-pmics.dtsi" + +/* + * This device tree also works for the TUXEDO Elite 14 Gen1 notebook + * prototype. + */ + +/ { + model = "Medion SPRCHRGD 14 S1"; + compatible = "medion,sprchrgd14s1", "qcom,x1e78100", "qcom,x1e80100"; + + aliases { + serial0 = &uart21; + serial1 = &uart14; + }; + + wcd938x: audio-codec { + compatible = "qcom,wcd9385-codec"; + + pinctrl-0 = <&wcd_default>; + pinctrl-names = "default"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>; + + vdd-buck-supply = <&vreg_l15b_1p8>; + vdd-rxtx-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l15b_1p8>; + vdd-mic-bias-supply = <&vreg_bob1>; + + #sound-dai-cells = <1>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + }; + }; + + hdmi-bridge { + compatible = "asl-tek,cs5263"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + /* + * TODO: These two regulators are actually part of the removable M.2 + * card and not the mainboard. Need to describe this differently. + * Functionally it works correctly, because all we need to do is to + * turn on the actual 3.3V supply above. + */ + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-MEDION-SPRCHRGD-14-S1"; + audio-routing = "WooferLeft IN", "WSA WSA_SPK1 OUT", + "TweeterLeft IN", "WSA WSA_SPK2 OUT", + "WooferRight IN", "WSA2 WSA_SPK2 OUT", + "TweeterRight IN", "WSA2 WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "TX SWR_INPUT1", "ADC2_OUTPUT"; + + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name = "WCD Capture"; + + codec { + sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_woofer>, <&left_tweeter>, + <&swr0 0>, <&lpass_wsamacro 0>, + <&right_woofer>, <&right_tweeter>, + <&swr3 0>, <&lpass_wsa2macro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name = "vreg_l7b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p9: ldo3 { + regulator-name = "vreg_l3c_0p9"; + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_l1j_0p9: ldo1 { + regulator-name = "vreg_l1j_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/x1e80100/medion/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + + status = "okay"; + + touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + + hid-descr-addr = <0x20>; + interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&tpad_default>; + pinctrl-names = "default"; + + wakeup-source; + }; + + keyboard@3a { + compatible = "hid-over-i2c"; + reg = <0x3a>; + + hid-descr-addr = <0x1>; + interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&kybd_default>; + pinctrl-names = "default"; + + wakeup-source; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + + vddio-supply = <&vreg_rtmr0_1p8>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + eusb5_repeater: redriver@43 { + compatible = "nxp,ptn3222"; + reg = <0x43>; + #phy-cells = <0>; + + vdd1v8-supply = <&vreg_l4b_1p8>; + vdd3v3-supply = <&vreg_l13b_3p0>; + + reset-gpios = <&tlmm 184 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb5_reset_n>; + pinctrl-names = "default"; + }; + + eusb3_repeater: redriver@47 { + compatible = "nxp,ptn3222"; + reg = <0x47>; + #phy-cells = <0>; + + vdd1v8-supply = <&vreg_l4b_1p8>; + vdd3v3-supply = <&vreg_l13b_3p0>; + + reset-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb3_reset_n>; + pinctrl-names = "default"; + }; + + eusb6_repeater: redriver@4f { + compatible = "nxp,ptn3222"; + reg = <0x4f>; + #phy-cells = <0>; + + vdd1v8-supply = <&vreg_l4b_1p8>; + vdd3v3-supply = <&vreg_l13b_3p0>; + + reset-gpios = <&tlmm 111 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&eusb6_reset_n>; + pinctrl-names = "default"; + }; +}; + +&iris { + firmware-name = "qcom/x1e80100/medion/qcvss8380.mbn"; + + status = "okay"; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + sound-name-prefix = "DisplayPort0"; + + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp2 { + sound-name-prefix = "DisplayPort2"; + + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + /delete-property/ #sound-dai-cells; + + pinctrl-0 = <&edp0_hpd_default>; + pinctrl-names = "default"; + + status = "okay"; + + aux-bus { + panel { + compatible = "edp-panel"; + power-supply = <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/medion/qcadsp8380.mbn", + "qcom/x1e80100/medion/adsp_dtbs.elf"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/medion/qccdsp8380.mbn", + "qcom/x1e80100/medion/cdsp_dtbs.elf"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&swr1 { + status = "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr3 { + status = "okay"; + + pinctrl-0 = <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "WooferRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "TweeterRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins = "gpio54"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; + + eusb3_reset_n: eusb3-reset-n-state { + pins = "gpio124"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + eusb6_reset_n: eusb6-reset-n-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + eusb5_reset_n: eusb5-reset-n-state { + pins = "gpio184"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + hall_int_n_default: hall-int-n-state { + pins = "gpio92"; + function = "gpio"; + bias-disable; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins = "gpio67"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins = "gpio3"; + function = "gpio"; + bias-disable; + }; + + wcd_default: wcd-reset-n-active-state { + pins = "gpio191"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p9>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; +}; + +/* Camera */ +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb5_repeater>; + + status = "okay"; +}; + +&usb_mp { + status = "okay"; +}; + +/* Right side USB-A (eUSB 3) */ +&usb_mp_hsphy0 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb3_repeater>; + + status = "okay"; +}; + +/* Left side USB-A (eUSB 6) */ +&usb_mp_hsphy1 { + vdd-supply = <&vreg_l2e_0p8>; + vdda12-supply = <&vreg_l3e_1p2>; + + phys = <&eusb6_repeater>; + + status = "okay"; +}; + +/* Right side USB-A (USB-SS 3) */ +&usb_mp_qmpphy0 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p9>; + + status = "okay"; +}; + +/* Left side USB-A (USB-SS 4) */ +&usb_mp_qmpphy1 { + vdda-phy-supply = <&vreg_l3e_1p2>; + vdda-pll-supply = <&vreg_l3c_0p9>; + + status = "okay"; +}; From 23ec0d891e09441b3d0353b56b73e35e3f3c5dad Mon Sep 17 00:00:00 2001 From: Georg Gottleuber Date: Thu, 4 Dec 2025 16:52:08 +0100 Subject: [PATCH 048/757] firmware: qcom: scm: QSEECOM on Medion SPRCHRGD 14 S1 This is needed to access EFI variables from Linux. Signed-off-by: Ettore Chimenti Signed-off-by: Georg Gottleuber Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251204155212.230058-7-ggo@tuxedocomputers.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom/qcom_scm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 1a6f85e463e0..ff0f7101dfe2 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2005,6 +2005,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = { { .compatible = "lenovo,thinkpad-t14s" }, { .compatible = "lenovo,thinkpad-x13s", }, { .compatible = "lenovo,yoga-slim7x" }, + { .compatible = "medion,sprchrgd14s1" }, { .compatible = "microsoft,arcata", }, { .compatible = "microsoft,blackrock" }, { .compatible = "microsoft,romulus13", }, From 6ac23b72cadac23657d466939c4d06cbfdf411cf Mon Sep 17 00:00:00 2001 From: Cosmo Chou Date: Wed, 17 Dec 2025 10:39:34 +0800 Subject: [PATCH 049/757] ARM: dts: aspeed: bletchley: Use generic node names Use generic node names to fix dt-schema warnings: - spi1_gpio: rename to generic "spi" node name - LED nodes: rename to led-N and move names to label properties - GPIO key nodes: add "-switch" suffix to node names Signed-off-by: Cosmo Chou Signed-off-by: Andrew Jeffery --- .../aspeed/aspeed-bmc-facebook-bletchley.dts | 77 ++++++++++++------- 1 file changed, 49 insertions(+), 28 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index abdb1562115a..9cb01381e482 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -34,7 +34,7 @@ <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; }; - spi1_gpio: spi1-gpio { + spi1_gpio: spi { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; @@ -54,7 +54,8 @@ front_gpio_leds { compatible = "gpio-leds"; - sys_log_id { + led-0 { + label = "sys_log_id"; default-state = "off"; gpios = <&front_leds 0 GPIO_ACTIVE_LOW>; }; @@ -62,42 +63,50 @@ fan_gpio_leds { compatible = "gpio-leds"; - fan0_blue { + led-0 { + label = "fan0_blue"; retain-state-shutdown; default-state = "on"; gpios = <&fan_leds 8 GPIO_ACTIVE_HIGH>; }; - fan1_blue { + led-1 { + label = "fan1_blue"; retain-state-shutdown; default-state = "on"; gpios = <&fan_leds 9 GPIO_ACTIVE_HIGH>; }; - fan2_blue { + led-2 { + label = "fan2_blue"; retain-state-shutdown; default-state = "on"; gpios = <&fan_leds 10 GPIO_ACTIVE_HIGH>; }; - fan3_blue { + led-3 { + label = "fan3_blue"; retain-state-shutdown; default-state = "on"; gpios = <&fan_leds 11 GPIO_ACTIVE_HIGH>; }; - fan0_amber { + led-4 { + label = "fan0_amber"; retain-state-shutdown; default-state = "off"; gpios = <&fan_leds 12 GPIO_ACTIVE_HIGH>; }; - fan1_amber { + led-5 { + label = "fan1_amber"; retain-state-shutdown; default-state = "off"; gpios = <&fan_leds 13 GPIO_ACTIVE_HIGH>; }; - fan2_amber { + led-6 { + label = "fan2_amber"; retain-state-shutdown; default-state = "off"; gpios = <&fan_leds 14 GPIO_ACTIVE_HIGH>; }; - fan3_amber { + led-7 { + label = "fan3_amber"; retain-state-shutdown; default-state = "off"; gpios = <&fan_leds 15 GPIO_ACTIVE_HIGH>; @@ -106,12 +115,14 @@ sled1_gpio_leds { compatible = "gpio-leds"; - sled1_amber { + led-0 { + label = "sled1_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; }; - sled1_blue { + led-1 { + label = "sled1_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; @@ -120,12 +131,14 @@ sled2_gpio_leds { compatible = "gpio-leds"; - sled2_amber { + led-0 { + label = "sled2_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; }; - sled2_blue { + led-1 { + label = "sled2_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; @@ -134,12 +147,14 @@ sled3_gpio_leds { compatible = "gpio-leds"; - sled3_amber { + led-0 { + label = "sled3_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; }; - sled3_blue { + led-1 { + label = "sled3_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; @@ -148,12 +163,14 @@ sled4_gpio_leds { compatible = "gpio-leds"; - sled4_amber { + led-0 { + label = "sled4_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; }; - sled4_blue { + led-1 { + label = "sled4_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; @@ -162,12 +179,14 @@ sled5_gpio_leds { compatible = "gpio-leds"; - sled5_amber { + led-0 { + label = "sled5_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; }; - sled5_blue { + led-1 { + label = "sled5_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; @@ -176,12 +195,14 @@ sled6_gpio_leds { compatible = "gpio-leds"; - sled6_amber { + led-0 { + label = "sled6_amber"; retain-state-shutdown; default-state = "keep"; gpios = <&sled6_leds 0 GPIO_ACTIVE_LOW>; }; - sled6_blue { + led-1 { + label = "sled6_blue"; retain-state-shutdown; default-state = "keep"; gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>; @@ -191,32 +212,32 @@ gpio-keys { compatible = "gpio-keys"; - presence-sled1 { + presence-sled1-switch { label = "presence-sled1"; gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>; linux,code = ; }; - presence-sled2 { + presence-sled2-switch { label = "presence-sled2"; gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; linux,code = ; }; - presence-sled3 { + presence-sled3-switch { label = "presence-sled3"; gpios = <&gpio0 ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; linux,code = ; }; - presence-sled4 { + presence-sled4-switch { label = "presence-sled4"; gpios = <&gpio0 ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>; linux,code = ; }; - presence-sled5 { + presence-sled5-switch { label = "presence-sled5"; gpios = <&gpio0 ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; linux,code = ; }; - presence-sled6 { + presence-sled6-switch { label = "presence-sled6"; gpios = <&gpio0 ASPEED_GPIO(H, 7) GPIO_ACTIVE_LOW>; linux,code = ; From 9d2c128ec56696cd7729845f17a4eaf537ae4438 Mon Sep 17 00:00:00 2001 From: Cosmo Chou Date: Wed, 17 Dec 2025 10:39:35 +0800 Subject: [PATCH 050/757] ARM: dts: aspeed: bletchley: Fix SPI GPIO property names Update SPI GPIO properties to use "-gpios" suffix: - gpio-sck -> sck-gpios - gpio-mosi -> mosi-gpios - gpio-miso -> miso-gpios Signed-off-by: Cosmo Chou Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index 9cb01381e482..5919a5046078 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -39,9 +39,9 @@ #address-cells = <1>; #size-cells = <0>; - gpio-sck = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - gpio-mosi = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - gpio-miso = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; num-chipselects = <1>; cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; From ca6730c4702e9719f4d8621bc76ca31c9bfe2c57 Mon Sep 17 00:00:00 2001 From: Cosmo Chou Date: Wed, 17 Dec 2025 10:39:36 +0800 Subject: [PATCH 051/757] ARM: dts: aspeed: bletchley: Remove unused pca9539 properties Remove unused #address-cells and #size-cells properties from pca9539 nodes to fix dt-schema warnings. Signed-off-by: Cosmo Chou Signed-off-by: Andrew Jeffery --- .../dts/aspeed/aspeed-bmc-facebook-bletchley.dts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index 5919a5046078..8df145d2bcfd 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -373,8 +373,6 @@ sled1_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -462,8 +460,6 @@ sled2_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -551,8 +547,6 @@ sled3_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -640,8 +634,6 @@ sled4_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -729,8 +721,6 @@ sled5_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; @@ -818,8 +808,6 @@ sled6_ioexp: pca9539@76 { compatible = "nxp,pca9539"; reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; gpio-controller; #gpio-cells = <2>; From 7c98d5c619c44e772402028dd852079aa8950842 Mon Sep 17 00:00:00 2001 From: Cosmo Chou Date: Wed, 17 Dec 2025 10:39:37 +0800 Subject: [PATCH 052/757] ARM: dts: aspeed: bletchley: Remove unused i2c13 property Remove 'aspeed,hw-timeout-ms' property which is not supported by the driver and causes dt-schema warnings. Signed-off-by: Cosmo Chou Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index 8df145d2bcfd..123e2d1891f6 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -962,7 +962,6 @@ &i2c13 { multi-master; - aspeed,hw-timeout-ms = <1000>; status = "okay"; //USB Debug Connector From 459a5aa171c0f13fcd78faa9594dc4aa5a95770b Mon Sep 17 00:00:00 2001 From: Cosmo Chou Date: Wed, 17 Dec 2025 10:39:38 +0800 Subject: [PATCH 053/757] ARM: dts: aspeed: bletchley: Fix ADC vref property names Replace non-functional 'vref' with 'aspeed,int-vref-microvolt' using the default 2.5V that the driver was already applying. Signed-off-by: Cosmo Chou Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index 123e2d1891f6..7c27bf6bb51d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -1032,7 +1032,7 @@ }; &adc0 { - vref = <1800>; + aspeed,int-vref-microvolt = <2500000>; status = "okay"; pinctrl-names = "default"; @@ -1043,7 +1043,7 @@ }; &adc1 { - vref = <2500>; + aspeed,int-vref-microvolt = <2500000>; status = "okay"; pinctrl-names = "default"; From 1b06942cda6e83c055e4530fec8227f6e2aba13e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Aug 2025 15:17:27 +0200 Subject: [PATCH 054/757] arm64: dts: nuvoton: npcm845: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250819131725.86770-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi index 383938dcd3ce..8239d9a9f0d2 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi @@ -64,8 +64,8 @@ }; psci { - compatible = "arm,psci-1.0"; - method = "smc"; + compatible = "arm,psci-1.0"; + method = "smc"; }; timer { From 725ba2d0e0b9ac1f0bc0c0c166db03201feaa203 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 15 Dec 2025 01:07:21 -0800 Subject: [PATCH 055/757] dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards Document the Kaanapali SoC binding and the boards which use it. Acked-by: Krzysztof Kozlowski Signed-off-by: Jingyi Wang Link: https://lore.kernel.org/r/20251215-knp-dts-v4-1-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 13ca0cf5ac7e..4eb0a7a9ee4a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -327,6 +327,12 @@ properties: - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 + - items: + - enum: + - qcom,kaanapali-mtp + - qcom,kaanapali-qrd + - const: qcom,kaanapali + - description: Sierra Wireless MangOH Green with WP8548 Module items: - const: swir,mangoh-green-wp8548 From f4a269eb1328d855314c858b5e903eca92ca3b36 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Fri, 31 Oct 2025 00:41:45 -0700 Subject: [PATCH 056/757] arm64: dts: qcom: kaanapali: Add header file for IPCC physical client IDs On earlier platforms, Inter Process Communication Controller (IPCC) used virtual client IDs and performed virtual-to-physical mapping in hardware, so the IDs defined in dt-bindings/mailbox/qcom-ipcc.h are common across platforms. Physical client IDs instead of virtual client IDs are used for qcom new platforms like Kaanapali, which will be parsed by the devicetree and passed to hardware to use Physical client IDs directly. Since physical client IDs could vary across platforms, add a corresponding header file for the Kaanapali platform. Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-2-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali-ipcc.h | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kaanapali-ipcc.h diff --git a/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h new file mode 100644 index 000000000000..125375a4aac0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-ipcc.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_KAANAPALI_MAILBOX_IPCC_H +#define __DTS_KAANAPALI_MAILBOX_IPCC_H + +/* Physical client IDs */ +#define IPCC_MPROC_AOP 0 +#define IPCC_MPROC_TZ 1 +#define IPCC_MPROC_MPSS 2 +#define IPCC_MPROC_LPASS 3 +#define IPCC_MPROC_SDC 4 +#define IPCC_MPROC_CDSP 5 +#define IPCC_MPROC_APSS 6 +#define IPCC_MPROC_SOCCP 13 +#define IPCC_MPROC_DCP 14 +#define IPCC_MPROC_SPSS 15 +#define IPCC_MPROC_TME 16 +#define IPCC_MPROC_WPSS 17 + +#define IPCC_COMPUTE_L0_CDSP 2 +#define IPCC_COMPUTE_L0_APSS 3 +#define IPCC_COMPUTE_L0_GPU 4 +#define IPCC_COMPUTE_L0_CVP 8 +#define IPCC_COMPUTE_L0_CAM 9 +#define IPCC_COMPUTE_L0_CAM1 10 +#define IPCC_COMPUTE_L0_DCP 11 +#define IPCC_COMPUTE_L0_VPU 12 +#define IPCC_COMPUTE_L0_SOCCP 16 + +#define IPCC_COMPUTE_L1_CDSP 2 +#define IPCC_COMPUTE_L1_APSS 3 +#define IPCC_COMPUTE_L1_GPU 4 +#define IPCC_COMPUTE_L1_CVP 8 +#define IPCC_COMPUTE_L1_CAM 9 +#define IPCC_COMPUTE_L1_CAM1 10 +#define IPCC_COMPUTE_L1_DCP 11 +#define IPCC_COMPUTE_L1_VPU 12 +#define IPCC_COMPUTE_L1_SOCCP 16 + +#define IPCC_PERIPH_CDSP 2 +#define IPCC_PERIPH_APSS 3 +#define IPCC_PERIPH_PCIE0 4 +#define IPCC_PERIPH_PCIE1 5 + +#define IPCC_FENCE_CDSP 2 +#define IPCC_FENCE_APSS 3 +#define IPCC_FENCE_GPU 4 +#define IPCC_FENCE_CVP 8 +#define IPCC_FENCE_CAM 8 +#define IPCC_FENCE_CAM1 10 +#define IPCC_FENCE_DCP 11 +#define IPCC_FENCE_VPU 20 +#define IPCC_FENCE_SOCCP 24 + +#endif From e36c38c91f5f3c07e65c58a0143e3124754a9030 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 31 Oct 2025 00:41:46 -0700 Subject: [PATCH 057/757] arm64: dts: qcom: glymur: Add header file for IPCC physical client IDs Physical client IDs are used on Glymur Inter Process Communication Controller (IPCC), add a corresponding header file. Signed-off-by: Sibi Sankar Signed-off-by: Jingyi Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-3-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/glymur-ipcc.h | 68 ++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/glymur-ipcc.h diff --git a/arch/arm64/boot/dts/qcom/glymur-ipcc.h b/arch/arm64/boot/dts/qcom/glymur-ipcc.h new file mode 100644 index 000000000000..700cd7114909 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/glymur-ipcc.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DTS_GLYMUR_MAILBOX_IPCC_H +#define __DTS_GLYMUR_MAILBOX_IPCC_H + +/* Glymur physical client IDs */ +#define IPCC_MPROC_AOP 0 +#define IPCC_MPROC_TZ 1 +#define IPCC_MPROC_MPSS 2 +#define IPCC_MPROC_LPASS 3 +#define IPCC_MPROC_SLPI 4 +#define IPCC_MPROC_SDC 5 +#define IPCC_MPROC_CDSP 6 +#define IPCC_MPROC_NPU 7 +#define IPCC_MPROC_APSS 8 +#define IPCC_MPROC_GPU 9 +#define IPCC_MPROC_ICP 11 +#define IPCC_MPROC_VPU 12 +#define IPCC_MPROC_PCIE0 13 +#define IPCC_MPROC_PCIE1 14 +#define IPCC_MPROC_PCIE2 15 +#define IPCC_MPROC_SPSS 16 +#define IPCC_MPROC_PCIE3 19 +#define IPCC_MPROC_PCIE4 20 +#define IPCC_MPROC_PCIE5 21 +#define IPCC_MPROC_PCIE6 22 +#define IPCC_MPROC_TME 23 +#define IPCC_MPROC_WPSS 24 +#define IPCC_MPROC_PCIE7 44 +#define IPCC_MPROC_SOCCP 46 + +#define IPCC_COMPUTE_L0_LPASS 0 +#define IPCC_COMPUTE_L0_CDSP 1 +#define IPCC_COMPUTE_L0_APSS 2 +#define IPCC_COMPUTE_L0_GPU 3 +#define IPCC_COMPUTE_L0_CVP 6 +#define IPCC_COMPUTE_L0_ICP 7 +#define IPCC_COMPUTE_L0_VPU 8 +#define IPCC_COMPUTE_L0_DPU 9 +#define IPCC_COMPUTE_L0_SOCCP 11 + +#define IPCC_COMPUTE_L1_LPASS 0 +#define IPCC_COMPUTE_L1_CDSP 1 +#define IPCC_COMPUTE_L1_APSS 2 +#define IPCC_COMPUTE_L1_GPU 3 +#define IPCC_COMPUTE_L1_CVP 6 +#define IPCC_COMPUTE_L1_ICP 7 +#define IPCC_COMPUTE_L1_VPU 8 +#define IPCC_COMPUTE_L1_DPU 9 +#define IPCC_COMPUTE_L1_SOCCP 11 + +#define IPCC_PERIPH_LPASS 0 +#define IPCC_PERIPH_APSS 1 +#define IPCC_PERIPH_PCIE0 2 +#define IPCC_PERIPH_PCIE1 3 +#define IPCC_PERIPH_PCIE2 6 +#define IPCC_PERIPH_PCIE3 7 +#define IPCC_PERIPH_PCIE4 8 +#define IPCC_PERIPH_PCIE5 9 +#define IPCC_PERIPH_PCIE6 10 +#define IPCC_PERIPH_PCIE7 11 +#define IPCC_PERIPH_SOCCP 13 +#define IPCC_PERIPH_WPSS 16 + +#endif From 2eeb5767d53f457913d2b378a3bd9e2269a4098d Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 15 Dec 2025 01:07:23 -0800 Subject: [PATCH 058/757] arm64: dts: qcom: Introduce Kaanapali SoC Kaanapali is Snapdragon SoC from Qualcomm. Features added in this patch: - CPUs with PSCI idle states and cpufreq - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect with CPU BWMONs - QuP with UART - SMMU - RPMhPD - UFS with Inline Crypto Engine - LLCC - Watchdog - SD Card - PCIe Written with help from Raviteja Laggyshetty (added interconnect nodes), Taniya Das (added Clock Controllers and cpufreq), Jishnu Prakash (added RPMhPD), Nitin Rawat (added UFS), Gaurav Kashyap (added ICE), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Co-developed-by: Tengfei Fan Signed-off-by: Tengfei Fan Signed-off-by: Jingyi Wang Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251215-knp-dts-v4-3-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1606 +++++++++++++++++++++++ 1 file changed, 1606 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kaanapali.dtsi diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi new file mode 100644 index 000000000000..51f8b3e0749c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -0,0 +1,1606 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "kaanapali-ipcc.h" + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 0>; + }; + + cpu6: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10000>; + enable-method = "psci"; + next-level-cache = <&l2_1>; + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 1>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + cpu7: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,oryon"; + reg = <0x0 0x10100>; + enable-method = "psci"; + next-level-cache = <&l2_1>; + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; + clocks = <&pdp_scmi_perf 1>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + + core1 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cluster0_c4: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "retention"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <93>; + exit-latency-us = <129>; + min-residency-us = <560>; + }; + + cluster1_c4: cpu-sleep-1 { + compatible = "arm,idle-state"; + idle-state-name = "retention"; + arm,psci-suspend-param = <0x00000004>; + entry-latency-us = <172>; + exit-latency-us = <130>; + min-residency-us = <686>; + }; + }; + + domain-idle-states { + cluster_cl5: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x01000054>; + entry-latency-us = <2150>; + exit-latency-us = <1983>; + min-residency-us = <9144>; + }; + + domain_ss3: domain-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x0200c354>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-kaanapali", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; + interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + }; + + scmi: scmi { + compatible = "arm,scmi"; + mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; + mbox-names = "tx", "rx"; + shmem = <&pdp_tx>, <&pdp_rx>; + + #address-cells = <1>; + #size-cells = <0>; + + pdp_scmi_perf: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,kaanapali-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,kaanapali-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster0_c4>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster1_c4>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&cluster1_c4>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_cl5>; + power-domains = <&system_pd>; + }; + + system_pd: power-domain-system { + #power-domain-cells = <0>; + domain-idle-states = <&domain_ss3>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pdp_mem: pdp@81300000 { + reg = <0x0 0x81300000 0x0 0x100000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + smem_mem: smem@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + pdp_ns_shared_mem: pdp-ns-shared@81f00000 { + reg = <0x0 0x81f00000 0x0 0x100000>; + no-map; + }; + + dsm_partition_1_mem: dsm-partition-1@84a00000 { + reg = <0x0 0x84a00000 0x0 0x5500000>; + no-map; + }; + + dsm_partition_2_mem: dsm-partition-2@89f00000 { + reg = <0x0 0x89f00000 0x0 0xa80000>; + no-map; + }; + + mpss_mem: mpss@8aa00000 { + reg = <0x0 0x8aa00000 0x0 0xeb00000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@99500000 { + reg = <0x0 0x99500000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@99580000 { + reg = <0x0 0x99580000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@99590000 { + reg = <0x0 0x99590000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@9959a000 { + reg = <0x0 0x9959a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera@99600000 { + reg = <0x0 0x99600000 0x0 0x800000>; + no-map; + }; + + camera_2_mem: camera-2@99e00000 { + reg = <0x0 0x99e00000 0x0 0x800000>; + no-map; + }; + + video_mem: video@9a600000 { + reg = <0x0 0x9a600000 0x0 0x800000>; + no-map; + }; + + cvp_mem: cvp@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp@9b500000 { + reg = <0x0 0x9b500000 0x0 0x1900000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 { + reg = <0x0 0x9ce00000 0x0 0x80000>; + no-map; + }; + + soccp_mem: soccp@a03d0000 { + reg = <0x0 0xa03d0000 0x0 0x500000>; + no-map; + }; + + soccp_dtb_mem: soccp-dtb@a08d0000 { + reg = <0x0 0xa08d0000 0x0 0x40000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 { + reg = <0x0 0xa1380000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi@a1400000 { + reg = <0x0 0xa1400000 0x0 0x4c00000>; + no-map; + }; + + rmtfs_mem: rmtfs@d7c00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xd7c00000 0x0 0x400000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + gcc: clock-controller@100000 { + compatible = "qcom,kaanapali-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <&pcie0_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <0>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + qupv3_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0xa3 0x0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart7: serial@a9c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a9c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart7_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + ipcc: mailbox@1106000 { + compatible = "qcom,kaanapali-ipcc", "qcom,ipcc"; + reg = <0x0 0x01106000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,kaanapali-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x1a080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,kaanapali-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x6200>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,kaanapali-system-noc"; + reg = <0x0 0x01680000 0x0 0x1f080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,kaanapali-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x11400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + }; + + aggre_noc: interconnect@16e0000 { + compatible = "qcom,kaanapali-aggre-noc"; + reg = <0x0 0x016e0000 0x0 0x42400>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,kaanapali-mmss-noc"; + reg = <0x0 0x01780000 0x0 0x5b800>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + pcie0: pcie@1c00000 { + device_type = "pci"; + compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + + operating-points-v2 = <&pcie0_opp_table>; + + iommu-map = <0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 0x7>; + #interrupt-cells = <1>; + + msi-map = <0x0 &gic_its 0x1400 0x1>, + <0x100 &gic_its 0x1401 0x1>; + msi-map-mask = <0xff00>; + max-link-speed = <3>; + linux,pci-domain = <0>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + + dma-coherent; + + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + }; + + pcie_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy"; + reg = <0x0 0x01c06000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>, + <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_CLKREF_EN>; + + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,kaanapali-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 = <&ufs_opp_table>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x60 0x0>; + dma-coherent; + + lanes-per-direction = <2>; + qcom,ice = <&ice>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + ice: crypto@1d88000 { + compatible = "qcom,kaanapali-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x0 0x01d88000 0x0 0x18000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,kaanapali-tcsr", "syscon"; + reg = <0x0 0x01fc0000 0x0 0x30000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,kaanapali-lpass-lpiaon-noc"; + reg = <0x0 0x07400000 0x0 0x19080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_lpicx_noc: interconnect@7420000 { + compatible = "qcom,kaanapali-lpass-lpicx-noc"; + reg = <0x0 0x07420000 0x0 0x44080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + lpass_ag_noc: interconnect@7f40000 { + compatible = "qcom,kaanapali-lpass-ag-noc"; + reg = <0x0 0x07f40000 0x0 0xe080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + + interconnects = <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + dma-coherent; + + resets = <&gcc GCC_SDCC2_BCR>; + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-peak-kBps = <160000 100000>; + opp-avg-kBps = <50000 0>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + opp-peak-kBps = <200000 120000>; + opp-avg-kBps = <104000 0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,kaanapali-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x10000>, + <0x0 0x179600f0 0x0 0xf4>; + + qcom,pdc-ranges = <0 745 38>, + <40 785 11>, + <51 527 4>, + <58 534 2>, + <61 537 20>, + <84 559 14>, + <98 609 32>, + <130 717 12>, + <142 251 5>, + <147 796 16>, + <163 783 2>, + <165 531 2>, + <167 536 1>, + <168 557 2>, + <170 415 1>, + <171 438 1>, + <172 579 1>, + <173 703 1>, + <174 708 1>, + <175 714 1>, + <176 68 1>, + <177 86 1>, + <178 96 1>, + <179 249 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + + interrupts-extended = <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_MPROC_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,kaanapali-tlmm"; + reg = <0x0 0x0f100000 0x0 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 218>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + qup_uart7_default: qup-uart7-state { + /* TX, RX */ + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + + card-detect-pins { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + + card-detect-pins { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + sram@14680000 { + compatible = "qcom,kaanapali-imem", "mmio-sram"; + reg = <0x0 0x14680000 0x0 0x1000>; + ranges = <0x0 0x0 0x14680000 0x1000>; + + no-memory-wc; + + #address-cells = <1>; + #size-cells = <1>; + + pil-sram@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + + interrupts =, + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17000000 0x0 0x10000>, + <0x0 0x17080000 0x0 0x200000>; + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17040000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + watchdog@17600000 { + compatible = "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt"; + reg = <0x0 0x17600000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + + pdp0_mbox: mailbox@17610000 { + compatible = "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x17610000 0x0 0x8000>, <0x0 0x19980000 0x0 0x8000>; + interrupts = ; + #mbox-cells = <1>; + }; + + timer@17810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17810000 0x0 0x1000>; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x0 0x20000000>; + + frame@17811000 { + reg = <0x0 0x17811000 0x1000>, + <0x0 0x17812000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@17813000 { + reg = <0x0 0x17813000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@17815000 { + reg = <0x0 0x17815000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@17817000 { + reg = <0x0 0x17817000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@17819000 { + reg = <0x0 0x17819000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@1781b000 { + reg = <0x0 0x1781b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@1781d000 { + reg = <0x0 0x1781d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18900000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18900000 0x0 0x10000>, + <0x0 0x18910000 0x0 0x10000>, + <0x0 0x18920000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + interrupts = , + , + ; + + power-domains = <&system_pd>; + label = "apps_rsc"; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,kaanapali-rpmh-clk"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmhpd: power-controller { + compatible = "qcom,kaanapali-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d3: opp-50 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d2_1: opp-51 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1_1: opp-54 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l0: opp-76 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_l2: opp-96 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_svs_l2: opp-224 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l0: opp-400 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l2: opp-432 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l3: opp-448 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l4: opp-452 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l5: opp-456 { + opp-level = ; + }; + + rpmhpd_opp_super_turbo_no_cpr: opp-480 { + opp-level = ; + }; + }; + }; + }; + + nsp_noc: interconnect@260c0000 { + compatible = "qcom,kaanapali-nsp-noc"; + reg = <0x0 0x260c0000 0x0 0x21280>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + /* Cluster 0 */ + pmu@310b3400 { + compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x310b3400 0x0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2188000>; + }; + + opp-1 { + opp-peak-kBps = <5412000>; + }; + + opp-2 { + opp-peak-kBps = <6220000>; + }; + + opp-3 { + opp-peak-kBps = <6832000>; + }; + + opp-4 { + opp-peak-kBps = <8368000>; + }; + + opp-5 { + opp-peak-kBps = <10944000>; + }; + + opp-6 { + opp-peak-kBps = <12748000>; + }; + + opp-7 { + opp-peak-kBps = <14744000>; + }; + + opp-8 { + opp-peak-kBps = <16896000>; + }; + + opp-9 { + opp-peak-kBps = <19120000>; + }; + + opp-10 { + opp-peak-kBps = <21332000>; + }; + }; + }; + + /* Cluster 1 */ + pmu@310b7400 { + compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x310b7400 0x0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + }; + + gem_noc: interconnect@31100000 { + compatible = "qcom,kaanapali-gem-noc"; + reg = <0x0 0x31100000 0x0 0x153080>; + qcom,bcm-voters = <&apps_bcm_voter>; + #interconnect-cells = <2>; + }; + + system-cache-controller@31800000 { + compatible = "qcom,kaanapali-llcc"; + reg = <0x0 0x31800000 0x0 0x200000>, + <0x0 0x32800000 0x0 0x200000>, + <0x0 0x31c00000 0x0 0x200000>, + <0x0 0x32c00000 0x0 0x200000>, + <0x0 0x34800000 0x0 0x200000>, + <0x0 0x34c00000 0x0 0x200000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base", + "llcc_broadcast_and_base"; + + interrupts = ; + }; + + sram: sram@81f08000 { + compatible = "mmio-sram"; + reg = <0x0 0x81f08000 0x0 0x200>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81f08000 0x200>; + + pdp_rx: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + pdp_tx: scp-sram-section@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x80>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = , + , + , + ; + }; +}; From 1cc3a0a0210697a25e96783cf21f93d28a09ebf7 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 15 Dec 2025 01:07:24 -0800 Subject: [PATCH 059/757] arm64: dts: qcom: kaanapali: Add base MTP board Add initial support for Qualcomm Kaanapali MTP board which enables PCIe, SD Card, UFS and booting to shell with UART console. Written with help from Jishnu Prakash (added RPMhPD nodes), Nitin Rawat (added UFS), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251215-knp-dts-v4-4-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 754 +++++++++++++++++++++ 2 files changed, 755 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kaanapali-mtp.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0b4d29d08783..35ca04c6173b 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts new file mode 100644 index 000000000000..32a082598434 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include "kaanapali.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kaanapali MTP"; + compatible = "qcom,kaanapali-mtp", "qcom,kaanapali"; + chassis-type = "handset"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3552000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3048000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3148000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p0: ldo11 { + regulator-name = "vreg_l11b_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1292000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l18b_1p2: ldo18 { + regulator-name = "vreg_l18b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "D_E0"; + + vreg_s10d_1p0: smps10 { + regulator-name = "vreg_s10d_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1d_1p2: ldo1 { + regulator-name = "vreg_l1d_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3d_0p8: ldo3 { + regulator-name = "vreg_l3d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4d_1p2: ldo4 { + regulator-name = "vreg_l4d_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s6f_0p5: smps6 { + regulator-name = "vreg_s6f_0p5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = ; + }; + + vreg_s7f_1p2: smps7 { + regulator-name = "vreg_s7f_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = ; + }; + + vreg_s8f_1p8: smps8 { + regulator-name = "vreg_s8f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p2: ldo1 { + regulator-name = "vreg_l1f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2f_1p2: ldo2 { + regulator-name = "vreg_l2f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3f_0p8: ldo3 { + regulator-name = "vreg_l3f_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4f_0p8: ldo4 { + regulator-name = "vreg_l4f_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "G_E0"; + + vreg_s7g_0p9: smps7 { + regulator-name = "vreg_s7g_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_s9g_1p0: smps9 { + regulator-name = "vreg_s9g_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2g_1p8: ldo2 { + regulator-name = "vreg_l2g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4g_0p9: ldo4 { + regulator-name = "vreg_l4g_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "I_E0"; + + vreg_s7i_0p9: smps7 { + regulator-name = "vreg_s7i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <972000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-5 { + compatible = "qcom,pmh0104-rpmh-regulators"; + qcom,pmic-id = "J_E1"; + + vreg_s1j_0p8: smps1 { + regulator-name = "vreg_s1j_0p8"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s2j_0p8: smps2 { + regulator-name = "vreg_s2j_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_s3j_1p2: smps3 { + regulator-name = "vreg_s3j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_s4j_0p7: smps4 { + regulator-name = "vreg_s4j_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pmr735d-rpmh-regulators"; + qcom,pmic-id = "K_E1"; + + vreg_l1k_0p8: ldo1 { + regulator-name = "vreg_l1k_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2k_0p7: ldo2 { + regulator-name = "vreg_l2k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3k_1p2: ldo3 { + regulator-name = "vreg_l3k_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4k_1p0: ldo4 { + regulator-name = "vreg_l4k_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5k_0p7: ldo5 { + regulator-name = "vreg_l5k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6k_1p7: ldo6 { + regulator-name = "vreg_l6k_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7k_0p7: ldo7 { + regulator-name = "vreg_l7k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <848000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "M_E1"; + + vreg_l1m_1p0: ldo1 { + regulator-name = "vreg_l1m_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2m_1p0: ldo2 { + regulator-name = "vreg_l2m_1p0"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p2: ldo4 { + regulator-name = "vreg_l4m_2p2"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-initial-mode = ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name = "vreg_l7m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "N_E1"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2n_1p2: ldo2 { + regulator-name = "vreg_l2n_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + }; +}; + +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l1d_1p2>; + + status = "okay"; +}; + +&pcie_port0 { + wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ + <74 1>, /* eSE */ + <119 2>, /* SoCCP */ + <144 4>; /* CXM UART */ + + pcie0_default_state: pcie0-default-state { + perst-n-pins { + pins = "gpio102"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + clkreq-n-pins { + pins = "gpio103"; + function = "pcie0_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-n-pins { + pins = "gpio104"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1200000>; + vccq-supply = <&vreg_l4d_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4g_0p9>; + vdda-pll-supply = <&vreg_l1d_1p2>; + + status = "okay"; +}; From 0e31dcfefd21ed76ff1b2d05647cd34336ab9772 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Mon, 15 Dec 2025 01:07:25 -0800 Subject: [PATCH 060/757] arm64: dts: qcom: kaanapali: Add base QRD board Add initial support for Qualcomm Kaanapali QRD board which enables SD Card, UFS and booting to shell with UART console. Written with help from Jishnu Prakash (added RPMhPD nodes), Nitin Rawat (added ufs) and Manish Pandey (added SD Card). Reviewed-by: Dmitry Baryshkov Signed-off-by: Jingyi Wang Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251215-knp-dts-v4-5-1541bebeb89f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/kaanapali-qrd.dts | 712 +++++++++++++++++++++ 2 files changed, 713 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kaanapali-qrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 35ca04c6173b..76cf0115a00a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) += kaanapali-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += kaanapali-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk.dtb lemans-evk-camera-csi1-imx577-dtbs := lemans-evk.dtb lemans-evk-camera-csi1-imx577.dtbo diff --git a/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts new file mode 100644 index 000000000000..66b423a497b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kaanapali-qrd.dts @@ -0,0 +1,712 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include "kaanapali.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kaanapali QRD"; + compatible = "qcom,kaanapali-qrd", "qcom,kaanapali"; + chassis-type = "handset"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pmh0101-rpmh-regulators"; + qcom,pmic-id = "B_E0"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <4000000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3552000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3048000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3148000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p0: ldo11 { + regulator-name = "vreg_l11b_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1292000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l18b_1p2: ldo18 { + regulator-name = "vreg_l18b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-1 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "D_E0"; + + vreg_s10d_1p0: smps10 { + regulator-name = "vreg_s10d_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1d_1p2: ldo1 { + regulator-name = "vreg_l1d_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <958000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3d_0p8: ldo3 { + regulator-name = "vreg_l3d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4d_1p2: ldo4 { + regulator-name = "vreg_l4d_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "F_E0"; + + vreg_s6f_0p5: smps6 { + regulator-name = "vreg_s6f_0p5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <570000>; + regulator-initial-mode = ; + }; + + vreg_s7f_1p2: smps7 { + regulator-name = "vreg_s7f_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1372000>; + regulator-initial-mode = ; + }; + + vreg_s8f_1p8: smps8 { + regulator-name = "vreg_s8f_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1f_1p2: ldo1 { + regulator-name = "vreg_l1f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2f_1p2: ldo2 { + regulator-name = "vreg_l2f_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3f_0p8: ldo3 { + regulator-name = "vreg_l3f_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <936000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4f_0p8: ldo4 { + regulator-name = "vreg_l4f_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "G_E0"; + + vreg_s7g_0p9: smps7 { + regulator-name = "vreg_s7g_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_s9g_1p0: smps9 { + regulator-name = "vreg_s9g_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1g_1p2: ldo1 { + regulator-name = "vreg_l1g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2g_1p8: ldo2 { + regulator-name = "vreg_l2g_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3g_1p2: ldo3 { + regulator-name = "vreg_l3g_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4g_0p9: ldo4 { + regulator-name = "vreg_l4g_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmh0110-rpmh-regulators"; + qcom,pmic-id = "I_E0"; + + vreg_s7i_0p9: smps7 { + regulator-name = "vreg_s7i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <972000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-5 { + compatible = "qcom,pmh0104-rpmh-regulators"; + qcom,pmic-id = "J_E1"; + + vreg_s1j_0p8: smps1 { + regulator-name = "vreg_s1j_0p8"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vreg_s2j_0p8: smps2 { + regulator-name = "vreg_s2j_0p8"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_s3j_1p2: smps3 { + regulator-name = "vreg_s3j_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_s4j_0p7: smps4 { + regulator-name = "vreg_s4j_0p7"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pmr735d-rpmh-regulators"; + qcom,pmic-id = "K_E1"; + + vreg_l1k_0p8: ldo1 { + regulator-name = "vreg_l1k_0p8"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2k_0p7: ldo2 { + regulator-name = "vreg_l2k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3k_1p2: ldo3 { + regulator-name = "vreg_l3k_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l4k_1p0: ldo4 { + regulator-name = "vreg_l4k_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5k_0p7: ldo5 { + regulator-name = "vreg_l5k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l6k_1p7: ldo6 { + regulator-name = "vreg_l6k_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7k_0p7: ldo7 { + regulator-name = "vreg_l7k_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <848000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "M_E1"; + + vreg_l1m_1p0: ldo1 { + regulator-name = "vreg_l1m_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2m_1p0: ldo2 { + regulator-name = "vreg_l2m_1p0"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3m_2p8: ldo3 { + regulator-name = "vreg_l3m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2900000>; + regulator-initial-mode = ; + }; + + vreg_l4m_2p2: ldo4 { + regulator-name = "vreg_l4m_2p2"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-initial-mode = ; + }; + + vreg_l6m_2p8: ldo6 { + regulator-name = "vreg_l6m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7m_2p8: ldo7 { + regulator-name = "vreg_l7m_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + }; + + regulators-8 { + compatible = "qcom,pm8010-rpmh-regulators"; + qcom,pmic-id = "N_E1"; + + vreg_l1n_1p1: ldo1 { + regulator-name = "vreg_l1n_1p1"; + regulator-min-microvolt = <1096000>; + regulator-max-microvolt = <1104000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2n_1p2: ldo2 { + regulator-name = "vreg_l2n_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3n_1p8: ldo3 { + regulator-name = "vreg_l3n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l4n_1p8: ldo4 { + regulator-name = "vreg_l4n_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l5n_2p8: ldo5 { + regulator-name = "vreg_l5n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l6n_2p8: ldo6 { + regulator-name = "vreg_l6n_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l7n_3p3: ldo7 { + regulator-name = "vreg_l7n_3p3"; + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + }; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>; + pinctrl-1 = <&sdc2_sleep>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <36 4>, /* NFC eSE SPI */ + <74 1>, /* eSE */ + <119 2>, /* SoCCP */ + <144 4>; /* CXM UART */ +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 217 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1200000>; + vccq-supply = <&vreg_l4d_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4g_0p9>; + vdda-pll-supply = <&vreg_l1d_1p2>; + + status = "okay"; +}; From f33ccc2316304f3a71e40e53f1568e75042b0a4b Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:53 +0100 Subject: [PATCH 061/757] riscv: dts: spacemit: Enable i2c8 adapter for Milk-V Jupiter The adapter is used to access the SpacemiT P1 PMIC present in this board. Signed-off-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20251206134532.1741648-2-javierm@redhat.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 28afd39b28da..aa425f02c1f4 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -72,6 +72,12 @@ status = "okay"; }; +&i2c8 { + pinctrl-0 = <&i2c8_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; From ae9d03f8aec76c1bff21083b67c211238d7c57b1 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:54 +0100 Subject: [PATCH 062/757] riscv: dts: spacemit: Define fixed regulators for Milk-V Jupiter Define the DC power input and the 4v power as fixed regulator supplies. Signed-off-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20251206134532.1741648-3-javierm@redhat.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-milkv-jupiter.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index aa425f02c1f4..5babed4d7094 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -20,6 +20,25 @@ chosen { stdout-path = "serial0"; }; + + reg_dc_in: dc-in-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_in_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vcc_4v: vcc-4v { + compatible = "regulator-fixed"; + regulator-name = "vcc_4v"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <®_dc_in>; + }; }; ð0 { From 7d307daa12b15a97269f577d5dcf50518758b568 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sat, 6 Dec 2025 14:44:55 +0100 Subject: [PATCH 063/757] riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter Define the SpacemiT P1 PMIC voltage regulators and their constraints. The power management hardware design on the Milk-V Jupiter is identical to the Banana Pi BPI-F3, so the DT Nodes were taken from k1-bananapi-f3.dts. Signed-off-by: Javier Martinez Canillas Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20251206134532.1741648-4-javierm@redhat.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-milkv-jupiter.dts | 110 ++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts index 5babed4d7094..800a112d5d70 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -95,6 +95,116 @@ pinctrl-0 = <&i2c8_cfg>; pinctrl-names = "default"; status = "okay"; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + vin-supply = <®_vcc_4v>; + + regulators { + buck1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck3_1v8: buck3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + buck6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + aldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + aldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + + dldo6 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-always-on; + }; + + dldo7 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; }; &uart0 { From 6f86a41d2162eea97946a952de4032db149d54c8 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 10 Nov 2025 11:23:51 +0000 Subject: [PATCH 064/757] riscv: dts: microchip: fix mailbox description When the binding for the mailbox on PolarFire SoC was originally written, and later modified, mistakes were made - and the precise nature of the later modification should have been a giveaway, but alas I was naive at the time. A more correct modelling of the hardware is to use two syscons and have a single reg entry for the mailbox, containing the mailbox region. The two syscons contain the general control/status registers for the mailbox and the interrupt related registers respectively. The reason for two syscons is that the same mailbox is present on the non-SoC version of the FPGA, which has no interrupt controller, and the shared part of the rtl was unchanged between devices. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 9883ca3554c5..f9d6bf08e717 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -259,6 +259,11 @@ #reset-cells = <1>; }; + sysreg_scb: syscon@20003000 { + compatible = "microchip,mpfs-sysreg-scb", "syscon"; + reg = <0x0 0x20003000 0x0 0x1000>; + }; + ccc_se: clock-controller@38010000 { compatible = "microchip,mpfs-ccc"; reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, @@ -521,10 +526,14 @@ status = "disabled"; }; - mbox: mailbox@37020000 { + control_scb: syscon@37020000 { + compatible = "microchip,mpfs-control-scb", "syscon"; + reg = <0x0 0x37020000 0x0 0x100>; + }; + + mbox: mailbox@37020800 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, - <0x0 0x37020800 0x0 0x100>; + reg = <0x0 0x37020800 0x0 0x1000>; interrupt-parent = <&plic>; interrupts = <96>; #mbox-cells = <1>; From 26535e84449abbf5d207a4b1db12891edf52e35e Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Mon, 10 Nov 2025 11:23:52 +0000 Subject: [PATCH 065/757] riscv: dts: microchip: convert clock and reset to use syscon The "subblock" clocks and reset registers on PolarFire SoC are located in the mss-top-sysreg region, alongside pinctrl and interrupt control functionality. Re-write the devicetree to describe the sys explicitly, as its own node, rather than as a region of the clock node. Correspondingly, the phandles to the reset controller must be updated to the new provider. The drivers will continue to support the old way of doing things. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index f9d6bf08e717..5c2963e269b8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -251,11 +251,9 @@ #dma-cells = <1>; }; - clkcfg: clkcfg@20002000 { - compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks = <&refclk>; - #clock-cells = <1>; + mss_top_sysreg: syscon@20002000 { + compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd"; + reg = <0x0 0x20002000 0x0 0x1000>; #reset-cells = <1>; }; @@ -452,7 +450,7 @@ local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; - resets = <&clkcfg CLK_MAC0>; + resets = <&mss_top_sysreg CLK_MAC0>; status = "disabled"; }; @@ -466,7 +464,7 @@ local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; clock-names = "pclk", "hclk"; - resets = <&clkcfg CLK_MAC1>; + resets = <&mss_top_sysreg CLK_MAC1>; status = "disabled"; }; @@ -550,5 +548,12 @@ clocks = <&scbclk>; status = "disabled"; }; + + clkcfg: clkcfg@3e001000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x3e001000 0x0 0x1000>; + clocks = <&refclk>; + #clock-cells = <1>; + }; }; }; From d2091990c5c1da38e9cc41240f03c420743af1bf Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 12 Dec 2025 13:19:18 -0800 Subject: [PATCH 066/757] dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board Append "starfive,jh7110" compatible to VisionFive 2 Lite and VisionFive 2 Lite eMMC boards in the least-compatible end of the list. Appending "starfive,jh7110" reduces the number of compatible strings to check in the OpenSBI platform driver. JH-7110S SoC on these boards is the same as JH-7110 SoC however rated for thermal, voltage, and frequency characteristics for a maximum of 1.25GHz operation. Link: https://lore.kernel.org/lkml/1f96a267-f5c6-498e-a2c4-7a47a73ea7e7@canonical.com/ Suggested-by: Heinrich Schuchardt Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/starfive.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 9253aab21518..8ba0e10b529a 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -41,6 +41,7 @@ properties: - starfive,visionfive-2-lite - starfive,visionfive-2-lite-emmc - const: starfive,jh7110s + - const: starfive,jh7110 additionalProperties: true From 7c9a5fd6bb19d08d687a416705c494eed0c55134 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 12 Dec 2025 13:19:19 -0800 Subject: [PATCH 067/757] riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board Append "starfive,jh7110" compatible to VisionFive 2 Lite board in the least-compatible end of the list. Appending "starfive,jh7110" reduces the number of compatible strings to check in the OpenSBI platform driver. JH-7110S SoC on this board is the same as JH-7110 SoC however rated for thermal, voltage, and frequency characteristics for a maximum of 1.25GHz operation. Link: https://lore.kernel.org/lkml/1f96a267-f5c6-498e-a2c4-7a47a73ea7e7@canonical.com/ Suggested-by: Heinrich Schuchardt Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- .../boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts index b96eea4fa7d5..b9913991a1b7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts @@ -9,7 +9,7 @@ / { model = "StarFive VisionFive 2 Lite"; - compatible = "starfive,visionfive-2-lite", "starfive,jh7110s"; + compatible = "starfive,visionfive-2-lite", "starfive,jh7110s", "starfive,jh7110"; }; &mmc0 { From 4297ddbf1d148a6007b91b2aec51853454253b96 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 12 Dec 2025 13:19:20 -0800 Subject: [PATCH 068/757] riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board Append "starfive,jh7110" compatible to VisionFive 2 Lite eMMC board in the least-compatible end of the list. Appending "starfive,jh7110" reduces the number of compatible strings to check in the OpenSBI platform driver. JH-7110S SoC on this board is the same as JH-7110 SoC however rated for thermal, voltage, and frequency characteristics for a maximum of 1.25GHz operation. Link: https://lore.kernel.org/lkml/1f96a267-f5c6-498e-a2c4-7a47a73ea7e7@canonical.com/ Suggested-by: Heinrich Schuchardt Signed-off-by: E Shattow Signed-off-by: Conor Dooley --- .../dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts index e27a662d4022..7544efa95de4 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts @@ -9,7 +9,7 @@ / { model = "StarFive VisionFive 2 Lite eMMC"; - compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s"; + compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s", "starfive,jh7110"; }; &mmc0 { From abc6930a3150003e1a436e906ffd1cafd679acfc Mon Sep 17 00:00:00 2001 From: Raghav Sharma Date: Wed, 19 Nov 2025 17:17:44 +0530 Subject: [PATCH 069/757] arm64: dts: exynosautov920: add CMU_MFD clock DT nodes Add required dt node for cmu_mfd block, which provides clocks for MFD IP Signed-off-by: Raghav Sharma Reviewed-by: Alim Akhtar Link: https://patch.msgid.link/20251119114744.1914416-4-raghav.s@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi index 6ee74d260776..02bf2ca52fdc 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1462,6 +1462,17 @@ "wfd"; }; + cmu_mfd: clock-controller@19e00000 { + compatible = "samsung,exynosautov920-cmu-mfd"; + reg = <0x19e00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_MFD_NOC>; + clock-names = "oscclk", + "noc"; + }; + pinctrl_aud: pinctrl@1a460000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>; From 30ae13173704585f2a3f406e94e0dbaa5cfde69a Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 11:59:52 -0600 Subject: [PATCH 070/757] arm64: dts: lg: Use recommended simple-bus node name Update LG LG131x 'amba' bus node name to 'amba-bus' following the standard names for simple-bus nodes. Generally, node names and paths aren't considered ABI, so it is safe to change them. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216175951.2791921-2-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/lg/lg131x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/lg/lg131x.dtsi b/arch/arm64/boot/dts/lg/lg131x.dtsi index 4cb1e4510897..90988770cb5c 100644 --- a/arch/arm64/boot/dts/lg/lg131x.dtsi +++ b/arch/arm64/boot/dts/lg/lg131x.dtsi @@ -102,7 +102,7 @@ clock-output-names = "BUSCLK"; }; - amba { + amba-bus { #address-cells = <2>; #size-cells = <1>; From 714b5a789f957871f18433645aa39d9109f194fb Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 12:00:29 -0600 Subject: [PATCH 071/757] arm64: dts: sprd: Use recommended node names Update Spreadtrum platforms node name to the recommended standard node names. Generally, node names and paths aren't considered ABI, so it is safe to change them. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216180029.2792676-2-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/sprd/sc9860.dtsi | 7 ++++--- arch/arm64/boot/dts/sprd/sc9863a.dtsi | 4 ++-- arch/arm64/boot/dts/sprd/sharkl64.dtsi | 2 +- arch/arm64/boot/dts/sprd/whale2.dtsi | 8 ++++---- 4 files changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index 864ef0a17425..765acde4867c 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -115,7 +115,7 @@ idle-states { entry-method = "psci"; - CORE_PD: core_pd { + CORE_PD: cpu-pd { compatible = "arm,idle-state"; entry-latency-us = <1000>; exit-latency-us = <700>; @@ -124,7 +124,7 @@ arm,psci-suspend-param = <0x00010002>; }; - CLUSTER_PD: cluster_pd { + CLUSTER_PD: cluster-pd { compatible = "arm,idle-state"; entry-latency-us = <1000>; exit-latency-us = <1000>; @@ -276,7 +276,8 @@ reg = <0 0x10003000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; - out-ports { + + in-ports { port { etb_in: endpoint { remote-endpoint = diff --git a/arch/arm64/boot/dts/sprd/sc9863a.dtsi b/arch/arm64/boot/dts/sprd/sc9863a.dtsi index e97000e560e7..31799579d7f2 100644 --- a/arch/arm64/boot/dts/sprd/sc9863a.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9863a.dtsi @@ -110,7 +110,7 @@ idle-states { entry-method = "psci"; - CORE_PD: core-pd { + CORE_PD: cpu-pd { compatible = "arm,idle-state"; entry-latency-us = <4000>; exit-latency-us = <4000>; @@ -545,7 +545,7 @@ }; }; - ap-ahb { + ahb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/sprd/sharkl64.dtsi b/arch/arm64/boot/dts/sprd/sharkl64.dtsi index bf58702c4e07..1c8c23e04136 100644 --- a/arch/arm64/boot/dts/sprd/sharkl64.dtsi +++ b/arch/arm64/boot/dts/sprd/sharkl64.dtsi @@ -16,7 +16,7 @@ #size-cells = <2>; ranges; - ap-apb { + apb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi index 2ecaa56001b8..87a834d4640c 100644 --- a/arch/arm64/boot/dts/sprd/whale2.dtsi +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi @@ -81,7 +81,7 @@ #clock-cells = <1>; }; - ap-apb@70000000 { + apb@70000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -136,7 +136,7 @@ }; }; - ap-ahb { + ahb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -183,7 +183,7 @@ }; }; - aon { + aon-bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -285,7 +285,7 @@ }; }; - agcp { + agcp-bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; From 22fbe6e21450d629642e4bdc8d8d329219abeb46 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 12:00:54 -0600 Subject: [PATCH 072/757] arm64: dts: toshiba: Use recommended node names Update Toshiba TMPV7708 node name to the recommended standard node names. Generally, node names and paths aren't considered ABI, so it is safe to change them. Signed-off-by: Rob Herring (Arm) Reviewed-by: Nobuhiro Iwamatsu Link: https://patch.msgid.link/20251216180055.2793215-2-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 2 +- arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts | 2 +- arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index d209fdc98597..8d099b237025 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -43,7 +43,7 @@ phy-handle = <&phy0>; phy-mode = "rgmii-id"; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts index ed7aa7e457b1..4439b3e8acbb 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts @@ -43,7 +43,7 @@ phy-handle = <&phy0>; phy-mode = "rgmii-id"; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index 0c8321022a73..af406f7285c4 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -26,7 +26,7 @@ &spi0 { status = "okay"; - mmc-slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; gpios = <&gpio 15 GPIO_ACTIVE_LOW>; From 15e3ce53673289624bab4e6a60207af4775f4a38 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 12:01:37 -0600 Subject: [PATCH 073/757] arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk" The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The Thunder2 SoC is missing the core "uartclk". In this case, the Linux driver uses single clock for both clock inputs. Let's assume that's how the h/w is wired and make the DT reflect that. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216180136.2794105-2-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index cc860a80af51..70430cb2b053 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -401,16 +401,16 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x24000000 0x0 0x1000>; interrupts = <1 21 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk50mhz>, <&refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; }; uaa1: serial@87e025000000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x87e0 0x25000000 0x0 0x1000>; interrupts = <1 22 4>; - clocks = <&refclk50mhz>; - clock-names = "apb_pclk"; + clocks = <&refclk50mhz>, <&refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; }; }; }; From f25aa20e92305c7ab7a6387b8ef7b6e83f8a49fb Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 12:02:02 -0600 Subject: [PATCH 074/757] arm64: dts: cavium: Drop thunder2 The Cavium thunder2 DT support is incomplete. It consists of 4 cores (out of 128) and only a serial port. The thunder2 specific drivers in the kernel don't have DT support either. The few remaining users of this platform likely use ACPI. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216180202.2794695-2-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/cavium/Makefile | 1 - arch/arm64/boot/dts/cavium/thunder2-99xx.dts | 30 ---- arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 144 ------------------ 3 files changed, 175 deletions(-) delete mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dts delete mode 100644 arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi diff --git a/arch/arm64/boot/dts/cavium/Makefile b/arch/arm64/boot/dts/cavium/Makefile index c178f7e06e18..8a1854380993 100644 --- a/arch/arm64/boot/dts/cavium/Makefile +++ b/arch/arm64/boot/dts/cavium/Makefile @@ -1,3 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb -dtb-$(CONFIG_ARCH_THUNDER2) += thunder2-99xx.dtb diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts b/arch/arm64/boot/dts/cavium/thunder2-99xx.dts deleted file mode 100644 index 89fc4107a0c4..000000000000 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dts file for Cavium ThunderX2 CN99XX Evaluation Platform - * - * Copyright (c) 2017 Cavium Inc. - * Copyright (c) 2013-2016 Broadcom - */ - -/dts-v1/; - -#include "thunder2-99xx.dtsi" - -/ { - model = "Cavium ThunderX2 CN99XX"; - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - - memory@80000000 { - device_type = "memory"; - reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ - <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ - }; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi deleted file mode 100644 index 966fb57280f3..000000000000 --- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * dtsi file for Cavium ThunderX2 CN99XX processor - * - * Copyright (c) 2017 Cavium Inc. - * Copyright (c) 2013-2016 Broadcom - * Author: Zi Shen Lim - */ - -#include - -/ { - model = "Cavium ThunderX2 CN99XX"; - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - /* just 4 cpus now, 128 needed in full config */ - cpus { - #address-cells = <0x2>; - #size-cells = <0x0>; - - cpu@0 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x0>; - enable-method = "psci"; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x1>; - enable-method = "psci"; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x2>; - enable-method = "psci"; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "cavium,thunder2", "brcm,vulcan"; - reg = <0x0 0x3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - gic: interrupt-controller@4000080000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - interrupt-controller; - #redistributor-regions = <1>; - reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ - <0x04 0x01000000 0x0 0x1000000>; /* GICR */ - interrupts = ; - - gicits: msi-controller@4000100000 { - compatible = "arm,gic-v3-its"; - msi-controller; - reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "brcm,vulcan-pmu"; - interrupts = ; /* PMU overflow */ - }; - - clk125mhz: uart_clk125mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <125000000>; - clock-output-names = "clk125mhz"; - }; - - pcie@30000000 { - compatible = "pci-host-ecam-generic"; - device_type = "pci"; - #interrupt-cells = <1>; - #address-cells = <3>; - #size-cells = <2>; - - /* ECAM at 0x3000_0000 - 0x4000_0000 */ - reg = <0x0 0x30000000 0x0 0x10000000>; - - /* - * PCI ranges: - * IO no supported - * MEM 0x4000_0000 - 0x6000_0000 - * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 - */ - ranges = - <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 - 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; - bus-range = <0 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = - /* addr pin ic icaddr icintr */ - <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH - 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH - 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH - 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&gicits>; - dma-coherent; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - uart0: serial@402020000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x04 0x02020000 0x0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - clocks = <&clk125mhz>, <&clk125mhz>; - clock-names = "uartclk", "apb_pclk"; - }; - }; - -}; From 7dd84bbec273345bd5735f6917b93eb2a7d9c0c3 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 13:12:12 -0600 Subject: [PATCH 075/757] ARM: dts: vexpress/v2m-rs1: Use documented arm,vexpress,config-bus child node names Update the arm,vexpress,config-bus child node names to use the documented ones. Most of these were updated a while back, but I missed these. Signed-off-by: Rob Herring (Arm) Reviewed-by: Liviu Dudau Link: https://patch.msgid.link/20251216191212.2879226-2-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi index 158b3923eae3..248b8e492d43 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi @@ -420,7 +420,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0 { + clock-controller-0 { /* MCC static memory clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -429,7 +429,7 @@ clock-output-names = "v2m:oscclk0"; }; - v2m_oscclk1: oscclk1 { + v2m_oscclk1: clock-controller-1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -438,7 +438,7 @@ clock-output-names = "v2m:oscclk1"; }; - v2m_oscclk2: oscclk2 { + v2m_oscclk2: clock-controller-2 { /* IO FPGA peripheral clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -447,7 +447,7 @@ clock-output-names = "v2m:oscclk2"; }; - volt-vio { + regulator-vio { /* Logic level voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; From 21bd5fb461eb485768cef99e0ff531a6b84b67d8 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 14:27:48 -0600 Subject: [PATCH 076/757] arm64: dts: apm/shadowcat: More clock clean-ups A fixed-factor-clock only provides 1 clock, so "#clock-cells" must be 0. The "snps,designware-i2c" node is not a clock provider, so drop "#clock-cells. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216-dt-apm-v1-1-0bf2bf8b982c@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 5bbedb0a7107..032d37a32193 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -295,7 +295,7 @@ socplldiv2: socplldiv2 { compatible = "fixed-factor-clock"; - #clock-cells = <1>; + #clock-cells = <0>; clocks = <&socpll 0>; clock-mult = <1>; clock-div = <2>; @@ -305,7 +305,7 @@ ahbclk: ahbclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "div-reg"; divider-offset = <0x164>; @@ -329,7 +329,7 @@ sdioclk: sdioclk@1f2ac000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2ac000 0x0 0x1000 0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg", "div-reg"; @@ -346,7 +346,7 @@ pcie0clk: pcie0clk@1f2bc000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2bc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie0clk"; @@ -355,7 +355,7 @@ pcie1clk: pcie1clk@1f2cc000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f2cc000 0x0 0x1000>; reg-names = "csr-reg"; clock-output-names = "pcie1clk"; @@ -364,7 +364,7 @@ xge0clk: xge0clk@1f61c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f61c000 0x0 0x1000>; reg-names = "csr-reg"; enable-mask = <0x3>; @@ -375,7 +375,7 @@ xge1clk: xge1clk@1f62c000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x1f62c000 0x0 0x1000>; reg-names = "csr-reg"; enable-mask = <0x3>; @@ -386,7 +386,7 @@ rngpkaclk: rngpkaclk@17000000 { compatible = "apm,xgene-device-clock"; #clock-cells = <1>; - clocks = <&socplldiv2 0>; + clocks = <&socplldiv2>; reg = <0x0 0x17000000 0x0 0x2000>; reg-names = "csr-reg"; csr-offset = <0xc>; @@ -799,7 +799,6 @@ compatible = "snps,designware-i2c"; reg = <0x0 0x10511000 0x0 0x1000>; interrupts = <0 0x45 0x4>; - #clock-cells = <1>; clocks = <&sbapbclk 0>; }; From cae405d73986579a88bfb956f1ae9b514c23a7bc Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 14:27:49 -0600 Subject: [PATCH 077/757] arm64: dts: apm: Use recommended i2c node names Use the recommended node name of 'i2c' for the 'i2cslimpro' nodes. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216-dt-apm-v1-2-0bf2bf8b982c@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 2 +- arch/arm64/boot/dts/apm/apm-storm.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 032d37a32193..95281268fb7f 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -224,7 +224,7 @@ clock-frequency = <50000000>; }; - i2cslimpro { + i2c { compatible = "apm,xgene-slimpro-i2c"; mboxes = <&mailbox 0>; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 4ca0ead120c1..85ad18b63038 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -134,7 +134,7 @@ interrupts = <1 12 0xff04>; }; - i2cslimpro { + i2c { compatible = "apm,xgene-slimpro-i2c"; mboxes = <&mailbox 0>; }; From a1176f7c5b990244e9a0ee2bdd93c9a36e5fe666 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 14:27:50 -0600 Subject: [PATCH 078/757] arm64: dts: apm: Add "reg" to "syscon-reboot" and "syscon-poweroff" As the nodes already have a unit-address, add the corresponding "reg" entry which is preferred over "offset". Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216-dt-apm-v1-3-0bf2bf8b982c@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/apm/apm-merlin.dts | 1 + arch/arm64/boot/dts/apm/apm-mustang.dts | 1 + arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 1 + arch/arm64/boot/dts/apm/apm-storm.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-merlin.dts b/arch/arm64/boot/dts/apm/apm-merlin.dts index b1160780a2a6..4ec05886dd41 100644 --- a/arch/arm64/boot/dts/apm/apm-merlin.dts +++ b/arch/arm64/boot/dts/apm/apm-merlin.dts @@ -38,6 +38,7 @@ poweroff: poweroff@10548010 { compatible = "syscon-poweroff"; + reg = <0x0 0x10548010 0x0 0x4>; regmap = <&poweroff_mbox>; offset = <0x10>; mask = <0x1>; diff --git a/arch/arm64/boot/dts/apm/apm-mustang.dts b/arch/arm64/boot/dts/apm/apm-mustang.dts index 2ef658796746..8f7eeba56dc4 100644 --- a/arch/arm64/boot/dts/apm/apm-mustang.dts +++ b/arch/arm64/boot/dts/apm/apm-mustang.dts @@ -38,6 +38,7 @@ poweroff: poweroff@10548010 { compatible = "syscon-poweroff"; + reg = <0x0 0x10548010 0x0 0x4>; regmap = <&poweroff_mbox>; offset = <0x10>; mask = <0x1>; diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 95281268fb7f..e930f2f26f4b 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -417,6 +417,7 @@ reboot: reboot@17000014 { compatible = "syscon-reboot"; + reg = <0x0 0x17000014 0x0 0x4>; regmap = <&scu>; offset = <0x14>; mask = <0x1>; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 85ad18b63038..3bb59704fcb2 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -462,6 +462,7 @@ reboot: reboot@17000014 { compatible = "syscon-reboot"; + reg = <0x0 0x17000014 0x0 0x4>; regmap = <&scu>; offset = <0x14>; mask = <0x1>; From 5cd532f7f017460395836d8f129ad3ee5ae63110 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 14:27:51 -0600 Subject: [PATCH 079/757] arm64: dts: apm: Drop "dma" device_type The only supported cases of otherwise deprecated for FDT "device_type" property are memory, cpu, and pci. "dma" is not valid, so drop it. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251216-dt-apm-v1-4-0bf2bf8b982c@kernel.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/apm/apm-storm.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 3bb59704fcb2..4c4938faffb1 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -1083,7 +1083,6 @@ dma: dma@1f270000 { compatible = "apm,xgene-storm-dma"; - device_type = "dma"; reg = <0x0 0x1f270000 0x0 0x10000>, <0x0 0x1f200000 0x0 0x10000>, <0x0 0x1b000000 0x0 0x400000>, From 01272f05aae5f6aca4337eb52e6b9290ce12e9f7 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 22 Dec 2025 10:22:13 +0000 Subject: [PATCH 080/757] arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes With the exception of cmu_top, each CMU has a corresponding sysreg bank that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers. The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of bus components and MEMCLK gates the sram clock. Now the clock driver supports automatic clock mode, provide the samsung,sysreg property so the driver can enable dynamic root clock gating of bus components and gate sram clock. Note without the property specified the driver simply falls back to previous behaviour of not configuring these registers so it is not an ABI break. Signed-off-by: Peter Griffin Link: https://patch.msgid.link/20251222-automatic-clocks-v7-2-fec86fa89874@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 9b38c2248016..2e25eeb0c259 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -578,6 +578,7 @@ clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>, <&cmu_top CLK_DOUT_CMU_MISC_SSS>; clock-names = "bus", "sss"; + samsung,sysreg = <&sysreg_misc>; }; sysreg_misc: syscon@10030000 { @@ -671,6 +672,7 @@ <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC0_IP>; clock-names = "oscclk", "bus", "ip"; + samsung,sysreg = <&sysreg_peric0>; }; sysreg_peric0: syscon@10820000 { @@ -1217,6 +1219,7 @@ <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, <&cmu_top CLK_DOUT_CMU_PERIC1_IP>; clock-names = "oscclk", "bus", "ip"; + samsung,sysreg = <&sysreg_peric1>; }; sysreg_peric1: syscon@10c20000 { @@ -1575,6 +1578,7 @@ <&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>; clock-names = "oscclk", "bus", "dpgtc", "usb31drd", "usbdpdbg"; + samsung,sysreg = <&sysreg_hsi0>; }; sysreg_hsi0: syscon@11020000 { @@ -1646,6 +1650,7 @@ <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>, <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>; clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + samsung,sysreg = <&sysreg_hsi2>; }; sysreg_hsi2: syscon@14420000 { @@ -1706,6 +1711,7 @@ clocks = <&ext_24_5m>; clock-names = "oscclk"; + samsung,sysreg = <&sysreg_apm>; }; sysreg_apm: syscon@17420000 { From 3fc7029d3009682b27be2fa2cd2269bc6f104c2e Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 20 Dec 2025 18:00:08 +0800 Subject: [PATCH 081/757] arm64: dts: rockchip: remove rtc regulator for ArmSoM Sige5 According to the schematic, RTC is powered by vcc_3v3_s3. The vcc_3v3_rtc_s5 regulator does not exist, remove it. Signed-off-by: Chukun Pan Reviewed-by: Sebastian Reichel Link: https://patch.msgid.link/20251220100010.26643-1-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 3386084f6318..392ba83ab05a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -156,16 +156,6 @@ vin-supply = <&vcc_5v0_sys>; }; - vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_rtc_s5"; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v0_sys>; - }; - vcc_3v3_s0: regulator-vcc-3v3-s0 { compatible = "regulator-fixed"; regulator-name = "vcc_3v3_s0"; From 341735d92ff868eb4c46beafb313d66f015809be Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 20 Dec 2025 18:00:09 +0800 Subject: [PATCH 082/757] arm64: dts: rockchip: fix hp-det pin for ArmSoM Sige5 Although the hp_det pin is not used, according to the schematic, the headphone detection pin is GPIO4_B0. Fix the incorrect pin. Signed-off-by: Chukun Pan Reviewed-by: Sebastian Reichel Link: https://patch.msgid.link/20251220100010.26643-2-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index 392ba83ab05a..a0d8f52a706f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -812,8 +812,8 @@ }; headphone { - hp_det: hp-det { - rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + hp_det_l: hp-det-l { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; From 3025d360f03515d3f6396a5cec339e776d62b2da Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Sat, 20 Dec 2025 18:00:10 +0800 Subject: [PATCH 083/757] arm64: dts: rockchip: enable saradc for ArmSoM Sige5 Add ADC support to ArmSoM Sige5 board. Signed-off-by: Chukun Pan Link: https://patch.msgid.link/20251220100010.26643-3-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts index a0d8f52a706f..d372ba252af8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts @@ -897,6 +897,11 @@ status = "okay"; }; +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + &sdhci { bus-width = <8>; full-pwr-cycle-in-suspend; From f8a1d7d136f734e8e20e414eaf8aff74e6e0d55c Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 4 Dec 2025 08:50:28 +0800 Subject: [PATCH 084/757] arm64: dts: rockchip: Add PCIe clkreq stuff for RK3588 EVB1 Add supports-clkreq and pinmux for PCIe ASPM L1 substates. Signed-off-by: Shawn Lin Acked-by: Manivannan Sadhasivam Reviewed-by: Hans Zhang Link: https://patch.msgid.link/1764809428-183623-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index ff1ba5ed56ef..c9d284cb738b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -522,6 +522,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>, <&wifi_host_wake_irq>; reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + supports-clkreq; vpcie3v3-supply = <&vcc3v3_wlan>; status = "okay"; @@ -545,7 +546,8 @@ &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; - pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; + pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>, <&pcie30x1m1_1_clkreqn>; + supports-clkreq; status = "okay"; }; @@ -555,7 +557,8 @@ &pcie3x4 { pinctrl-names = "default"; - pinctrl-0 = <&pcie3_reset>; + pinctrl-0 = <&pcie3_reset>, <&pcie30x4m1_clkreqn>; + supports-clkreq; reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; From 1b2d6b75e2b3374157c9015435381b217a887145 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Tue, 2 Dec 2025 08:49:40 +0000 Subject: [PATCH 085/757] arm64: dts: rockchip: Add EEPROMs for Radxa ROCK 4 boards The BL24C04A EEPROM is found in the schematics for Radxa ROCK Pi 4A+ and 4B+. [1] [2] The BL24C16A EEPROM is found in the schematics for Radxa ROCK 4C+, 4SE, Radxa ROCK Pi 4A, 4B, and 4C. [3] [4] [5] [6] [7] However, newer boards/batches should have the BL24C16A, but older ones may have the BL24C04A. (the ROCK Pi 4B+ I own has a 16Kb EEPROM) For the ROCK Pi 4s (except the relatively new ROCK 4SE), add the BL24C04A eeprom node for backward compatibility. For the ROCK 4SE, add the BL24C16A eeprom node. These are designed to have data written during factory programming (regardless of whether data is actually written or not), and we at Radxa permit users to read the data but not write to it. [8] Therefore, we will add a read-only property to the eeprom node. [1] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/4ap/radxa_rock_4ap_v1730_schematic.pdf p.17 [2] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/4bp/radxa_rock_4bp_v1730_schematic.pdf p.17 [3] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/ROCK-4C+-V1.411-SCH.pdf p.22 [4] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/ROCK-4-SE-V1.53-SCH.pdf p.17 [5] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/4a/ROCK_4A_V1.52_SCH.pdf p.17 [6] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/4b/ROCK_4B_v1.52_SCH.pdf p.17 [7] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4c_v12_sch_20200620.pdf p.17 [8] https://github.com/radxa/u-boot/blob/next-dev-v2024.10/drivers/misc/radxa-i2c-eeprom.c Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251202084941.1785-3-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts | 12 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 8 ++++++++ 3 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts index 74160cf89188..f95fd92d58ba 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts @@ -453,6 +453,14 @@ regulator-off-in-suspend; }; }; + + eeprom@50 { + compatible = "belling,bl24c04a", "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0_s0>; + }; }; &i2c3 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts index a8b8d4acc337..c0b931b3c640 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts @@ -8,6 +8,8 @@ #include "rk3399-t.dtsi" #include "rk3399-rock-pi-4.dtsi" +/delete-node/ &eeprom; + / { model = "Radxa ROCK 4SE"; compatible = "radxa,rock-4se", "rockchip,rk3399"; @@ -17,6 +19,16 @@ }; }; +&i2c0 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0>; + }; +}; + &sdio0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 046dbe329017..a8ab043e4062 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -456,6 +456,14 @@ regulator-off-in-suspend; }; }; + + eeprom: eeprom@50 { + compatible = "belling,bl24c04a", "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v0>; + }; }; &i2c1 { From e3b12fc3336240e7dee4989b9e8634be3c959c94 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Tue, 2 Dec 2025 08:49:41 +0000 Subject: [PATCH 086/757] arm64: dts: rockchip: Add EEPROMs for Radxa rk35xx boards The BL24C16A EEPROM is found in the schematics for Radxa CM3I, Radxa ROCK 3A, 3B, 5B+, and 5T. [1] [2] [3] [4] [5] The BL24C16F EEPROM is found in the schematic for Radxa ROCK 4D. [6] Add these eeprom nodes. These are designed to have data written during factory programming (regardless of whether data is actually written or not), and we at Radxa permit users to read the data but not write to it. [8] Therefore, we will add a read-only property to the eeprom node. [1] https://dl.radxa.com/cm3i/docs/hw/radxa_cm3i_v1310_schematic.pdf p.8 [2] https://dl.radxa.com/rock3/docs/hw/3a/radxa_rock_3a_v1310_schematic.pdf p.7 [3] https://dl.radxa.com/rock3/docs/hw/3b/Radxa_ROCK_3B_V1.51_SCH.pdf p.35 [4] https://dl.radxa.com/rock5/5b+/docs/hw/radxa_rock5bp_v1.2_schematic.pdf p.29 [5] https://dl.radxa.com/rock5/5t/docs/hw/radxa_rock5t_schematic_v1.2_20250109.pdf p.36 [6] https://dl.radxa.com/rock4/4d/docs/hw/Radxa_ROCK_4D_SCH_V1.12.pdf p.23 [7] https://github.com/radxa/u-boot/blob/next-dev-v2024.10/drivers/misc/radxa-i2c-eeprom.c Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251202084941.1785-4-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 10 +++++++++- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts | 8 ++++++++ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 14 ++++++++++++++ .../boot/dts/rockchip/rk3588-rock-5b-plus.dts | 10 ++++++++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts | 10 ++++++++++ 6 files changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi index 729e38b9f620..f97a0eb7f7c0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi @@ -321,7 +321,7 @@ }; }; - vcc_3v3: SWITCH_REG1 { + gpio_vref: vcc_3v3: SWITCH_REG1 { regulator-name = "vcc_3v3"; regulator-always-on; regulator-boot-on; @@ -340,6 +340,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&gpio_vref>; + }; }; &pinctrl { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 44cfdfeed668..9214e38648f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -532,6 +532,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc3v3_pmu>; + }; }; &i2c3 { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts index 3d0c1ccfaa79..69001e453732 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts @@ -480,6 +480,14 @@ }; }; }; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc3v3_sys>; + }; }; &i2c5 { diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts index 7023dc326d0e..899a84b1fbf9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -682,6 +682,20 @@ }; }; +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16f", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &mdio0 { rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts index 07a840d9b385..30d15c7e860a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts @@ -69,6 +69,16 @@ }; }; +&i2c1 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &pcie30phy { data-lanes = <1 1 2 2>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts index 0dd90c744380..425036146b6d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts @@ -60,6 +60,16 @@ status = "okay"; }; +&i2c1 { + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&vcc_3v3_s3>; + }; +}; + &pcie2x1l1 { pinctrl-names = "default"; pinctrl-0 = <&pcie2_1_rst>; From 2d6fcdcaf42671dd3fb281d7a2e5ea985af11ce5 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 28 Nov 2025 15:09:22 +0800 Subject: [PATCH 087/757] arm64: dts: rockchip: add dma-coherent for pcie and gmac of RK3576 The RK3576 SoC employs ARM CCI for maintaining cache coherency between the CPU cluster and high-speed peripherals including USB3, SATA, GMAC, and PCIe controllers. While the USB3 and SATA controllers were correctly marked as dma-coherent, the GMAC and PCIe nodes were overlooked. Without dma-coherent, the kernel falls back to software cache maintenance for DMA operations, requiring explicit cache flushing and invalidating. This adds significant overhead that degrades performance in high-throughput workloads. Add the missing dma-coherent properties to enable hardware coherency and avoid unnecessary software cache management overhead. Signed-off-by: Shawn Lin Link: https://patch.msgid.link/1764313762-78063-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index a86fc6b4e8c4..792857aee4f7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -680,6 +680,7 @@ "aclk_dbi", "pclk", "aux"; device_type = "pci"; + dma-coherent; interrupts = , , , @@ -734,6 +735,7 @@ "aclk_dbi", "pclk", "aux"; device_type = "pci"; + dma-coherent; interrupts = , , , @@ -1696,6 +1698,7 @@ clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref"; + dma-coherent; interrupts = , ; interrupt-names = "macirq", "eth_wake_irq"; @@ -1743,6 +1746,7 @@ clock-names = "stmmaceth", "clk_mac_ref", "pclk_mac", "aclk_mac", "ptp_ref"; + dma-coherent; interrupts = , ; interrupt-names = "macirq", "eth_wake_irq"; From 396870f53c4e736366b4ed2e127874c30ce2f965 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 20 Oct 2025 12:07:55 +0200 Subject: [PATCH 088/757] arm64: dts: rockchip: add gmac reset property to rk3368 Add the reset of the gmac controller block. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20251020100757.3669681-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index ce4b112b082b..4c391e2341c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -498,6 +498,8 @@ "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac"; + resets = <&cru SRST_MAC>; + reset-names = "stmmaceth"; status = "disabled"; }; From bce933a74b8e785a8090da74bee8ec3f38be40b7 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 20 Oct 2025 12:07:56 +0200 Subject: [PATCH 089/757] arm64: dts: rockchip: add mdio subnode to gmac on rk3368 This is needed to actually describe the per-board phys connected to the gmac when needed. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20251020100757.3669681-3-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index 4c391e2341c5..f9e24b25274b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -501,6 +501,12 @@ resets = <&cru SRST_MAC>; reset-names = "stmmaceth"; status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; }; usb_host0_ehci: usb@ff500000 { From 1cb0958a26aeffe315a60b3cbbc56b94246cc25a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 20 Oct 2025 12:07:57 +0200 Subject: [PATCH 090/757] arm64: dts: rockchip: Correctly describe the ethernet phy on rk3368-lion So far, the board used the phy implicitly using the deprecated snps reset properties. Improve that and describe the PHY correctly under the new mdio node. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20251020100757.3669681-4-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 22 ++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi index 8ccc3184a836..61c52bd91784 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -154,13 +154,11 @@ assigned-clocks = <&cru SCLK_MAC>; assigned-clock-parents = <&ext_gmac>; clock_in_out = "input"; + phy-handle = <&vsc8531_2>; phy-supply = <&vcc33_io>; phy-mode = "rgmii"; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 50000>; - snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; tx_delay = <0x10>; rx_delay = <0x10>; status = "okay"; @@ -285,7 +283,25 @@ status = "okay"; }; +&mdio { + vsc8531_2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&phy_rst>; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + &pinctrl { + ethernet { + phy_rst: phy-rst { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { module_led_pins: module-led-pins { rockchip,pins = From 9c68a9483e31a9ad25c5399bb5f066b2e4980ad5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rapha=C3=ABl=20Jakse?= Date: Sun, 30 Nov 2025 17:12:59 +0100 Subject: [PATCH 091/757] arm64: dts: rockchip: Fix Bluetooth on the RockPro64 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The RockPro64 board has an optional BCM4345C5 Bluetooth device on UART0. This patch fixes audio stutters by setting its correct max-speed and compatible properties. Signed-off-by: Raphaël Jakse Link: https://patch.msgid.link/20251130161259.9828-1-raphael.kernel@jakse.fr Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts | 7 +++++++ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts index 304e3c51391c..883d9bcfe792 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dts @@ -28,3 +28,10 @@ }; }; }; + +&uart0 { + bluetooth { + compatible = "brcm,bcm4345c5"; + max-speed = <1500000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts index 4b42717800f7..ae3ee91dba2f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts @@ -28,3 +28,10 @@ }; }; }; + +&uart0 { + bluetooth { + compatible = "brcm,bcm4345c5"; + max-speed = <1500000>; + }; +}; From 7beae528ddadd1c3f7d5670f937d993b0f39e0ea Mon Sep 17 00:00:00 2001 From: Joseph Kogut Date: Fri, 5 Dec 2025 12:07:01 +0000 Subject: [PATCH 092/757] dt-bindings: arm: rockchip: Add Radxa CM5 IO board Add device tree binding for the Radxa CM5 IO board. This board is based on the rk3588s. Signed-off-by: Joseph Kogut Reviewed-by: Krzysztof Kozlowski Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251205120703.14721-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index d496421dbd87..79e99694577e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -907,6 +907,13 @@ properties: - const: radxa,cm3 - const: rockchip,rk3566 + - description: Radxa Compute Module 5 (CM5) + items: + - enum: + - radxa,cm5-io + - const: radxa,cm5 + - const: rockchip,rk3588s + - description: Radxa CM3 Industrial items: - enum: From 36ee19ba42dcebe6a15ec6b442a7d32eb327eee4 Mon Sep 17 00:00:00 2001 From: Joseph Kogut Date: Fri, 5 Dec 2025 12:07:02 +0000 Subject: [PATCH 093/757] arm64: dts: rockchip: Add rk3588 based Radxa CM5 Add initial support for the Radxa Compute Module 5 (CM5). The CM5 uses a proprietary connector. Specification: - Rockchip RK3588 - Up to 32 GB LPDDR4X - Up to 128 GB eMMC - 1x HDMI TX up to 8k@60 hz - 1x eDP TX up to 4k@60 hz - Gigabit Ethernet PHY Signed-off-by: Joseph Kogut Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251205120703.14721-3-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588s-radxa-cm5.dtsi | 280 ++++++++++++++++++ 1 file changed, 280 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi new file mode 100644 index 000000000000..d307e19052c6 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Joseph Kogut + */ + +/* + * CM5 data sheet + * https://dl.radxa.com/cm5/v2210/radxa_cm5_v2210_schematic.pdf + */ + +#include +#include +#include +#include + +/ { + compatible = "radxa,cm5", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + }; + + leds { + compatible = "gpio-leds"; + + led_sys: led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus + &gmac1_clkinout>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + mmc-hs200-1_8v; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vdd2_ddr_s3>; + vcc14-supply = <&vdd2_ddr_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + }; + }; +}; From 51babf83f424a695179183204226d453c8af7dc7 Mon Sep 17 00:00:00 2001 From: Joseph Kogut Date: Fri, 5 Dec 2025 12:07:03 +0000 Subject: [PATCH 094/757] arm64: dts: rockchip: Add support for CM5 IO carrier Specification: - 1x HDMI - 2x MIPI DSI - 2x MIPI CSI - 1x eDP - 1x M.2 E key - 1x USB 3.0 Host - 1x USB 3.0 OTG - 2x USB 2.0 Host - Headphone jack w/ microphone - Gigabit Ethernet w/ PoE - microSD slot - 40-pin expansion header - 12V DC Signed-off-by: Joseph Kogut Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20251205120703.14721-4-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588s-radxa-cm5-io.dts | 339 ++++++++++++++++++ 2 files changed, 340 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 3fdd1e4832e1..105dae928f97 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -210,6 +210,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts new file mode 100644 index 000000000000..f80d5a00a4bd --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Joseph Kogut + */ + +/* + * CM5 IO board data sheet + * https://dl.radxa.com/cm5/v2200/radxa_cm5_io_v2200_schematic.pdf + */ + +/dts-v1/; +#include "rk3588s.dtsi" +#include "rk3588s-radxa-cm5.dtsi" + +/ { + model = "Radxa Compute Module 5 (CM5) IO Board"; + compatible = "radxa,cm5-io", "radxa,cm5", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + vcc12v_dcin: regulator-12v0-vcc-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: regulator-3v3-vcc-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s0: pldo-reg4 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + fusb302: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <1000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orientation_switch: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + usbc0_role_switch: endpoint { + remote-endpoint = <&usb_host0_xhci_role_switch>; + }; + }; + + port@2 { + reg = <2>; + usbc0_dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + fusb302 { + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + sd-uhs-sdr104; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + usb_host0_xhci_role_switch: endpoint { + remote-endpoint = <&usbc0_role_switch>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orientation_switch>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_dp_altmode_mux>; + }; + }; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; From 1bec3bd1f839f269dfdec3c635dd2afe15e30995 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 21 Dec 2025 19:05:10 +0800 Subject: [PATCH 095/757] arm64: dts: allwinner: sun55i: Add SPI controllers The A523 family SoCs have four SPI controllers. One of them also supports DBI mode. Add device nodes for all of them. Also add pinmux nodes for spi0 on the PC pins, which is commonly used for SPI-NOR boot flash. Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20251221110513.1850535-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 42dab01e3f56..9335977751e2 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -214,6 +214,43 @@ allwinner,pinmux = <2>; }; + /omit-if-no-ref/ + spi0_pc_pins: spi0-pc-pins { + pins = "PC2", "PC4", "PC12"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + + /omit-if-no-ref/ + spi0_cs0_pc_pin: spi0-cs0-pc-pin { + pins = "PC3"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + + /omit-if-no-ref/ + spi0_cs1_pc_pin: spi0-cs1-pc-pin { + pins = "PC7"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + + /omit-if-no-ref/ + spi0_hold_pc_pin: spi0-hold-pc-pin { + /* conflicts with eMMC D7 */ + pins = "PC16"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + + /omit-if-no-ref/ + spi0_wp_pc_pin: spi0-wp-pc-pin { + /* conflicts with eMMC D2 */ + pins = "PC15"; + function = "spi0"; + allwinner,pinmux = <4>; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; allwinner,pinmux = <2>; @@ -563,6 +600,49 @@ #size-cells = <0>; }; + spi0: spi@4025000 { + compatible = "allwinner,sun55i-a523-spi"; + reg = <0x04025000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@4026000 { + compatible = "allwinner,sun55i-a523-spi-dbi", + "allwinner,sun55i-a523-spi"; + reg = <0x04026000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2: spi@4027000 { + compatible = "allwinner,sun55i-a523-spi"; + reg = <0x04027000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + usb_otg: usb@4100000 { compatible = "allwinner,sun55i-a523-musb", "allwinner,sun8i-a33-musb"; @@ -815,6 +895,20 @@ #clock-cells = <1>; }; + r_spi0: spi@7092000 { + compatible = "allwinner,sun55i-a523-spi"; + reg = <0x07092000 0x1000>; + interrupts = ; + clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>; + clock-names = "ahb", "mod"; + dmas = <&dma 53>, <&dma 53>; + dma-names = "rx", "tx"; + resets = <&r_ccu RST_BUS_R_SPI>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + mcu_ccu: clock-controller@7102000 { compatible = "allwinner,sun55i-a523-mcu-ccu"; reg = <0x7102000 0x200>; From bd14ba160bbe863e7b7bc489fd947ae1cdc03047 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sun, 21 Dec 2025 19:05:11 +0800 Subject: [PATCH 096/757] arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash The Orangepi 4A has a SPI-NOR flash connected to spi0 on the PC pins. The HOLD and WP pins are not connected, and are instead pulled up by the supply rail. Enable spi0 and add a device node for the SPI-NOR flash. Acked-by: Jernej Skrabec Link: https://patch.msgid.link/20251221110513.1850535-5-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 9e6b21cf293e..055be86e5fae 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -400,6 +400,21 @@ assigned-clock-rates = <32768>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + vcc-supply = <®_cldo1>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; From 73a6c811fa0d07078c9e1eaecea76ce26fb5f10e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:30 -0600 Subject: [PATCH 097/757] riscv: dts: spacemit: Add a PCIe regulator Define a 3.3v fixed voltage regulator to be used by PCIe on the Banana Pi BPI-F3. On this platform, this regulator is always on. Signed-off-by: Alex Elder Reviewed-by: Yixun Lan Tested-by: Yixun Lan Link: https://lore.kernel.org/r/20251218151235.454997-5-elder@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 02f218a16318..71f48454ba47 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -33,6 +33,14 @@ }; }; + pcie_vcc_3v3: pcie-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "PCIE_VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_dc_in: dc-in-12v { compatible = "regulator-fixed"; regulator-name = "dc_in_12v"; From 0be016a4b5d1b927de04e2e7a0a2bce51aacbfff Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Thu, 18 Dec 2025 09:12:31 -0600 Subject: [PATCH 098/757] riscv: dts: spacemit: PCIe and PHY-related updates Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC. Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3 board. The combo PHY is used for USB on this board, and that will be enabled when USB 3 support is accepted. The combo PHY must perform a calibration step to determine configuration values used by the PCIe-only PHYs. As a result, it must be enabled if either of the other two PHYs is enabled. Signed-off-by: Alex Elder Reviewed-by: Yixun Lan Tested-by: Yixun Lan Link: https://lore.kernel.org/r/20251218151235.454997-6-elder@riscstar.com Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 36 ++++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 176 ++++++++++++++++++ 3 files changed, 245 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 71f48454ba47..3f10efd925dc 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -61,6 +61,12 @@ }; }; +&combo_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_3_cfg>; + status = "okay"; +}; + &emmc { bus-width = <8>; mmc-hs400-1_8v; @@ -272,6 +278,36 @@ }; }; +&pcie1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_3_cfg>; + status = "okay"; +}; + +&pcie1_port { + phys = <&pcie1_phy>; +}; + +&pcie1 { + vpcie3v3-supply = <&pcie_vcc_3v3>; + status = "okay"; +}; + +&pcie2_phy { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_4_cfg>; + status = "okay"; +}; + +&pcie2_port { + phys = <&pcie2_phy>; +}; + +&pcie2 { + vpcie3v3-supply = <&pcie_vcc_3v3>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi index e922e05ff856..b13dcb10f4d6 100644 --- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi @@ -530,6 +530,39 @@ }; }; + pcie0_3_cfg: pcie0-3-cfg { + pcie0-3-pins { + pinmux = , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up = <0>; + drive-strength = <21>; + }; + }; + + pcie1_3_cfg: pcie1-3-cfg { + pcie1-3-pins { + pinmux = , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up = <0>; + drive-strength = <21>; + }; + }; + + pcie2_4_cfg: pcie2-4-cfg { + pcie2-4-pins { + pinmux = , /* PERST# */ + , /* WAKE# */ + ; /* CLKREQ# */ + + bias-pull-up = <0>; + drive-strength = <21>; + }; + }; + pwm14_1_cfg: pwm14-1-cfg { pwm14-1-pins { pinmux = ; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 7818ca4979b6..86d1db14e2ee 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -4,6 +4,7 @@ */ #include +#include /dts-v1/; / { @@ -423,6 +424,52 @@ status = "disabled"; }; + combo_phy: phy@c0b10000 { + compatible = "spacemit,k1-combo-phy"; + reg = <0x0 0xc0b10000 0x0 0x1000>; + clocks = <&vctcxo_24m>, + <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names = "refclk", + "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE0_GLOBAL>, + <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names = "phy", + "dbi", + "mstr", + "slv"; + #phy-cells = <1>; + spacemit,apmu = <&syscon_apmu>; + status = "disabled"; + }; + + pcie1_phy: phy@c0c10000 { + compatible = "spacemit,k1-pcie-phy"; + reg = <0x0 0xc0c10000 0x0 0x1000>; + clocks = <&vctcxo_24m>; + clock-names = "refclk"; + resets = <&syscon_apmu RESET_PCIE1_GLOBAL>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie2_phy: phy@c0d10000 { + compatible = "spacemit,k1-pcie-phy"; + reg = <0x0 0xc0d10000 0x0 0x1000>; + clocks = <&vctcxo_24m>; + clock-names = "refclk"; + resets = <&syscon_apmu RESET_PCIE2_GLOBAL>; + reset-names = "phy"; + #phy-cells = <0>; + status = "disabled"; + }; + syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; @@ -969,6 +1016,135 @@ #size-cells = <2>; dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>; + pcie0: pcie@ca000000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca000000 0x0 0x00001000>, + <0x0 0xca300000 0x0 0x0001ff24>, + <0x0 0x8f000000 0x0 0x00002000>, + <0x0 0xc0b20000 0x0 0x00001000>; + reg-names = "dbi", + "atu", + "config", + "link"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>, + <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>; + interrupts = <141>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE0_DBI>, + <&syscon_apmu CLK_PCIE0_MASTER>, + <&syscon_apmu CLK_PCIE0_SLAVE>; + clock-names = "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE0_DBI>, + <&syscon_apmu RESET_PCIE0_MASTER>, + <&syscon_apmu RESET_PCIE0_SLAVE>; + reset-names = "dbi", + "mstr", + "slv"; + spacemit,apmu = <&syscon_apmu 0x03cc>; + status = "disabled"; + + pcie0_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie1: pcie@ca400000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca400000 0x0 0x00001000>, + <0x0 0xca700000 0x0 0x0001ff24>, + <0x0 0x9f000000 0x0 0x00002000>, + <0x0 0xc0c20000 0x0 0x00001000>; + reg-names = "dbi", + "atu", + "config", + "link"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>, + <0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>; + interrupts = <142>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE1_DBI>, + <&syscon_apmu CLK_PCIE1_MASTER>, + <&syscon_apmu CLK_PCIE1_SLAVE>; + clock-names = "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE1_DBI>, + <&syscon_apmu RESET_PCIE1_MASTER>, + <&syscon_apmu RESET_PCIE1_SLAVE>; + reset-names = "dbi", + "mstr", + "slv"; + spacemit,apmu = <&syscon_apmu 0x3d4>; + status = "disabled"; + + pcie1_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + + pcie2: pcie@ca800000 { + device_type = "pci"; + compatible = "spacemit,k1-pcie"; + reg = <0x0 0xca800000 0x0 0x00001000>, + <0x0 0xcab00000 0x0 0x0001ff24>, + <0x0 0xb7000000 0x0 0x00002000>, + <0x0 0xc0d20000 0x0 0x00001000>; + reg-names = "dbi", + "atu", + "config", + "link"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>, + <0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>, + <0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>; + interrupts = <143>; + interrupt-names = "msi"; + clocks = <&syscon_apmu CLK_PCIE2_DBI>, + <&syscon_apmu CLK_PCIE2_MASTER>, + <&syscon_apmu CLK_PCIE2_SLAVE>; + clock-names = "dbi", + "mstr", + "slv"; + resets = <&syscon_apmu RESET_PCIE2_DBI>, + <&syscon_apmu RESET_PCIE2_MASTER>, + <&syscon_apmu RESET_PCIE2_SLAVE>; + reset-names = "dbi", + "mstr", + "slv"; + spacemit,apmu = <&syscon_apmu 0x3dc>; + status = "disabled"; + + pcie2_port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; storage-bus { From 03ea8676919af21b99bea01f18ef1a271d19f92f Mon Sep 17 00:00:00 2001 From: "Anton D. Stavinskii" Date: Wed, 26 Nov 2025 21:21:16 +0400 Subject: [PATCH 099/757] riscv: dts: sophgo: cv180x: fix USB dwc2 FIFO sizes I've tested the current dwc2 FIFO configuration and found that USB device mode breaks in ECM mode when transmitting frames larger than 128 bytes. For example, large ICMP packets or iperf3 traffic cause the USB link to hang and eventually disconnect without any messages in dmesg. After switching to more conservative FIFO sizes, ECM becomes stable and no longer drops the connection. iperf3 now shows ~130 Mbit/s RX and ~100 Mbit/s TX on SG2002 (MilkV Duo 256M). Fix the FIFO sizes accordingly. Signed-off-by: Anton D. Stavinskii Reviewed-by: Inochi Amaoto Fixes: e307248a3c2d ("riscv: dts: sophgo: Add USB support for cv18xx") Link: https://lore.kernel.org/r/20251126172115.1894190-2-stavinsky@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 1b2b1969a648..06b0ce5a2db7 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -438,8 +438,8 @@ clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>; clock-names = "otg", "utmi"; g-np-tx-fifo-size = <32>; - g-rx-fifo-size = <536>; - g-tx-fifo-size = <768 512 512 384 128 128>; + g-rx-fifo-size = <1536>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; interrupts = ; phys = <&usbphy>; phy-names = "usb2-phy"; From 21dcacabcc7ec6f75a0966738ec368563969baa4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Mon, 17 Nov 2025 18:17:52 +0100 Subject: [PATCH 100/757] dt-bindings: clock: gcc-msm8917: Add missing MDSS reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add definition for MDSS reset can be found on MSM8917 and MSM8937. Signed-off-by: Barnabás Czémán Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251117-mdss-resets-msm8917-msm8937-v2-1-a7e9bbdaac96@mainlining.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,gcc-msm8917.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h index 4e3897b3669d..4265460bfb30 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8917.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h @@ -194,6 +194,7 @@ #define GCC_QUSB2_PHY_BCR 2 #define GCC_USB_HS_BCR 3 #define GCC_USB2_HS_PHY_ONLY_BCR 4 +#define GCC_MDSS_BCR 5 /* GDSCs */ #define CPP_GDSC 0 From 4713dc185fa4cc21dcc69e7d35e347adc735126a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 14 Nov 2025 12:47:08 -0500 Subject: [PATCH 101/757] ARM: dts: lpc32xx: remove usb bus and elevate all children nodes Remove usb bus and elevate all children nodes because usb bus is not existed and only group usb devices logically. Update register address and related full node name. Fix below CHECK_DTBS warnings: arm/boot/dts/nxp/lpc/lpc3250-ea3250.dtb: usb (simple-bus): $nodename:0: 'usb' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$' from schema $id: http://devicetree.org/schemas/simple-bus.yaml# Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 79 ++++++++++++-------------- 1 file changed, 36 insertions(+), 43 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 2236901a0031..e780451fd335 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -86,51 +86,44 @@ #dma-cells = <2>; }; - usb { + /* + * Enable either ohci or usbd (gadget)! + */ + ohci: usb@31020000 { + compatible = "nxp,ohci-nxp", "usb-ohci"; + reg = <0x31020000 0x300>; + interrupt-parent = <&sic1>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_HOST>; + status = "disabled"; + }; + + usbd: usbd@31020000 { + compatible = "nxp,lpc3220-udc"; + reg = <0x31020000 0x300>; + interrupt-parent = <&sic1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_LOW>; + clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; + status = "disabled"; + }; + + i2cusb: i2c@31020300 { + compatible = "nxp,pnx-i2c"; + reg = <0x31020300 0x100>; + interrupt-parent = <&sic1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&usbclk LPC32XX_USB_CLK_I2C>; #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - ranges = <0x0 0x31020000 0x00001000>; + #size-cells = <0>; + }; - /* - * Enable either ohci or usbd (gadget)! - */ - ohci: usb@0 { - compatible = "nxp,ohci-nxp", "usb-ohci"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_HOST>; - status = "disabled"; - }; - - usbd: usbd@0 { - compatible = "nxp,lpc3220-udc"; - reg = <0x0 0x300>; - interrupt-parent = <&sic1>; - interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, - <30 IRQ_TYPE_LEVEL_HIGH>, - <28 IRQ_TYPE_LEVEL_HIGH>, - <26 IRQ_TYPE_LEVEL_LOW>; - clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; - status = "disabled"; - }; - - i2cusb: i2c@300 { - compatible = "nxp,pnx-i2c"; - reg = <0x300 0x100>; - interrupt-parent = <&sic1>; - interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usbclk LPC32XX_USB_CLK_I2C>; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbclk: clock-controller@f00 { - compatible = "nxp,lpc3220-usb-clk"; - reg = <0xf00 0x100>; - #clock-cells = <1>; - }; + usbclk: clock-controller@31020f00 { + compatible = "nxp,lpc3220-usb-clk"; + reg = <0x31020f00 0x100>; + #clock-cells = <1>; }; clcd: clcd@31040000 { From 8f1dae6cf85a823ed065255ad8960890d3d4dc3b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 14 Nov 2025 12:47:09 -0500 Subject: [PATCH 102/757] ARM: dts: lpc3250-ea3250: add key- prefix for gpio-keys Add key- prefix to fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dtb: gpio-keys (gpio-keys): 'joy0', ... do not match any of the regexes: '^(button|...)$', 'pinctrl-[0-9]+ Reviewed-by: Vladimir Zapolskiy Signed-off-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts index 63c6f17bb7c9..837a3cfa8e7c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts @@ -27,55 +27,55 @@ gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ }; - key1 { + key-1 { label = "KEY1"; linux,code = <1>; gpios = <&pca9532 0 0>; }; - key2 { + key-2 { label = "KEY2"; linux,code = <2>; gpios = <&pca9532 1 0>; }; - key3 { + key-3 { label = "KEY3"; linux,code = <3>; gpios = <&pca9532 2 0>; }; - key4 { + key-4 { label = "KEY4"; linux,code = <4>; gpios = <&pca9532 3 0>; }; - joy0 { + key-joy0 { label = "Joystick Key 0"; linux,code = <10>; gpios = <&gpio 2 0 0>; /* P2.0 */ }; - joy1 { + key-joy1 { label = "Joystick Key 1"; linux,code = <11>; gpios = <&gpio 2 1 0>; /* P2.1 */ }; - joy2 { + key-joy2 { label = "Joystick Key 2"; linux,code = <12>; gpios = <&gpio 2 2 0>; /* P2.2 */ }; - joy3 { + key-joy3 { label = "Joystick Key 3"; linux,code = <13>; gpios = <&gpio 2 3 0>; /* P2.3 */ }; - joy4 { + key-joy4 { label = "Joystick Key 4"; linux,code = <14>; gpios = <&gpio 2 4 0>; /* P2.4 */ From dd76e20b4c985a170c5b7a9ca781aa72be02e22d Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 14 Nov 2025 12:47:11 -0500 Subject: [PATCH 103/757] ARM: dts: lpc3250-phy3250: rename nodename at@0 to eeprom@0 Rename nodename at@0 to eeprom@0 to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dtb: at25@0 (atmel,at25): $nodename: 'anyOf' conditional failed, one must be fixed: 'at25@0' does not match '^eeprom@[0-9a-f]{1,2}$' 'at25@0' does not match '^fram@[0-9a-f]{1,2}$' Signed-off-by: Frank Li Reviewed-by: Vladimir Zapolskiy Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts index 21a6d0bca1e8..147ce360c4ea 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts @@ -200,7 +200,7 @@ cs-gpios = <&gpio 3 5 0>; status = "okay"; - eeprom: at25@0 { + eeprom: eeprom@0 { compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <5000000>; From 867589d82f1a0e9f534dfe7bb3bcd08a5306c22e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 14 Nov 2025 12:47:10 -0500 Subject: [PATCH 104/757] ARM: dts: lpc3250-phy3250: replace deprecated at25 properties with new ones Replace deprecated at25 properties with the required properties (size, address-width and pagesize), which duplicate the removed properties. Fix below CHECK_DTB warning: arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dtb: at25@0 (atmel,at25): 'pagesize' is a required property arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dtb: at25@0 (atmel,at25): $nodename: 'anyOf' conditional failed, one must be fixed: Signed-off-by: Frank Li [vzapolskiy: squashed two changes from the series and updated commit message] Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts index 147ce360c4ea..0f96ea0337a1 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts +++ b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts @@ -213,9 +213,9 @@ pl022,wait-state = <0>; pl022,duplex = <0>; - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; + size = <0x8000>; + address-width = <16>; + pagesize = <64>; }; }; From 9afdf3e1a59e23180540ecb1fe3287c308cc8113 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Mon, 22 Dec 2025 16:30:09 +0000 Subject: [PATCH 105/757] arm64: dts: exynos: gs101: add OTP node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the OTP controller node. Signed-off-by: Tudor Ambarus Reviewed-by: André Draszik Link: https://patch.msgid.link/20251222-gs101-chipid-v4-5-aa8e20ce7bb3@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 2e25eeb0c259..48f3819590cf 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -571,6 +571,14 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; + efuse@10000000 { + compatible = "google,gs101-otp"; + reg = <0x10000000 0xf084>; + clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>; + clock-names = "pclk"; + interrupts = ; + }; + cmu_misc: clock-controller@10010000 { compatible = "google,gs101-cmu-misc"; reg = <0x10010000 0x10000>; From 628f6ac792c9a3dace4b6f50d6445f7d5a6af4f2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 3 Nov 2025 16:48:32 -0500 Subject: [PATCH 106/757] arm64: dts: imx8qm: add ddr perf device node Add ddr perf monitor device node for i.MX8QM. Change imx8-ss-ddr.dtsi's compatible string to fsl,imx8qxp-ddr-pmu. i.MX8QM overwrite to fsl,imx8qm-ddr-pmu. All fallback to fsl,imx8-ddr-pmu. Signed-off-by: Joakim Zhang Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8-ss-ddr.dtsi | 2 +- .../boot/dts/freescale/imx8qm-ss-ddr.dtsi | 19 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 2 ++ 3 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi index 7d5183c6c5be..37e68865b026 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-ddr.dtsi @@ -11,7 +11,7 @@ ddr_subsys: bus@5c000000 { ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; ddr_pmu0: ddr-pmu@5c020000 { - compatible = "fsl,imx8-ddr-pmu"; + compatible = "fsl,imx8qxp-ddr-pmu", "fsl,imx8-ddr-pmu"; reg = <0x5c020000 0x10000>; interrupts = ; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi new file mode 100644 index 000000000000..c831567cfbc1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-ddr.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * Dong Aisheng + */ + +&ddr_pmu0 { + compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu"; + interrupts = ; +}; + +&ddr_subsys { + ddr_pmu1: ddr-pmu@5c120000 { + compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu"; + reg = <0x5c120000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index cb66853b1cd3..9e7309a0ca51 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -635,6 +635,7 @@ #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" #include "imx8-ss-conn.dtsi" + #include "imx8-ss-ddr.dtsi" #include "imx8-ss-lsio.dtsi" #include "imx8-ss-hsio.dtsi" }; @@ -647,5 +648,6 @@ #include "imx8qm-ss-lvds.dtsi" #include "imx8qm-ss-mipi.dtsi" #include "imx8qm-ss-hsio.dtsi" +#include "imx8qm-ss-ddr.dtsi" /delete-node/ &dsp; From 4688fd527c85f63890167b4705a3622488e73781 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 3 Nov 2025 16:48:33 -0500 Subject: [PATCH 107/757] arm64: dts: imx8dxl-ss-ddr: Add DB (system interconnects) pmu support for i.MX8DXL Add DB pmu related nodes. This pmu is in DB (system interconnects). Signed-off-by: Jacky Bai Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 22 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 7 ++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi index 3569abb5bb9b..adc6e394dbc5 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -7,3 +7,25 @@ compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu"; interrupts = ; }; + +&ddr_subsys { + db_pmu0: db-pmu@5ca40000 { + compatible = "fsl,imx8dxl-db-pmu"; + reg = <0x5ca40000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_4>, <&db_pmu0_lpcg IMX_LPCG_CLK_0>; + clock-names = "ipg", "cnt"; + }; + + db_pmu0_lpcg: clock-controller@5cae0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5cae0000 0x10000>; + #clock-cells = <1>; + clocks = <&db_ipg_clk>, <&db_ipg_clk>; + clock-indices = , ; + clock-output-names = "perf_lpcg_cnt_clk", + "perf_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_PERF>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 8d60827822ed..5106be2fde6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -236,6 +236,13 @@ clock-output-names = "xtal_24MHz"; }; + db_ipg_clk: clock-db-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <456000000>; + clock-output-names = "db_ipg_clk"; + }; + /* sorted in register address */ #include "imx8-ss-cm40.dtsi" #include "imx8-ss-adma.dtsi" From c3ea38980ab48c8b86d2f940cd9714b5b8c62d9b Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Sun, 16 Nov 2025 09:35:57 +0800 Subject: [PATCH 108/757] arm64: dts: imx94: add basic NETC related nodes The NETC related nodes for i.MX94, this NETC has two PCIe buses, the bus 0 has 1 ENETC instance, one PTP timer, one RCEC and a switch, currently, the switch is not added due to the DT binding and the driver is not ready at the moment. The bus 1 has three ENETC instances, 2 PTP timers, 1 RCEC and one EMDIO. Signed-off-by: Wei Fang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx94.dtsi | 138 +++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 73184f03f8a3..4fdec712307f 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -1191,6 +1191,144 @@ }; }; + netc_blk_ctrl: system-controller@4ceb0000 { + compatible = "nxp,imx94-netc-blk-ctrl"; + reg = <0x0 0x4ceb0000 0x0 0x10000>, + <0x0 0x4cec0000 0x0 0x10000>, + <0x0 0x4c810000 0x0 0x7C>; + reg-names = "ierb", "prb", "netcmix"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + clocks = <&scmi_clk IMX94_CLK_ENET>; + clock-names = "ipg"; + power-domains = <&scmi_devpd IMX94_PD_NETC>; + status = "disabled"; + + netc_bus0: pcie@4ca00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4ca00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x0 0x0>; + msi-map = <0x00 &its 0x68 0x1>, //ENETC3 PF + <0x01 &its 0x61 0x1>, //Timer0 + <0x02 &its 0x64 0x1>, //Switch + <0x40 &its 0x69 0x1>, //ENETC3 VF0 + <0x80 &its 0x6a 0x1>, //ENETC3 VF1 + <0xC0 &its 0x6b 0x1>; //ENETC3 VF2 + /* Switch BAR0 - non-prefetchable memory */ + ranges = <0x02000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0x80000 + /* ENETC 3 and Timer 0 BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4cd40000 0x0 0x4cd40000 0x0 0x60000 + /* Switch and Timer 0 BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce00000 0x0 0x4ce00000 0x0 0x20000 + /* ENETC 3 VF0-2 BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4ce50000 0x0 0x4ce50000 0x0 0x30000 + /* ENETC 3 VF0-2 BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce80000 0x0 0x4ce80000 0x0 0x30000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 + GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + enetc3: ethernet@0,0 { + compatible = "pci1131,e110"; + reg = <0x0 0 0 0 0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + netc_timer0: ptp-timer@0,1 { + compatible = "pci1131,ee02"; + reg = <0x100 0 0 0 0>; + status = "disabled"; + }; + + rcec@1,0 { + reg = <0x800 0 0 0 0>; + interrupts = <1>; + }; + }; + + netc_bus1: pcie@4cb00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4cb00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x1 0x1>; + msi-map = <0x100 &its 0x65 0x1>, //ENETC0 PF + <0x101 &its 0x62 0x1>, //Timer1 + <0x140 &its 0x66 0x1>, //ENETC1 PF + <0x180 &its 0x67 0x1>, //ENETC2 PF + <0x181 &its 0x63 0x1>, //Timer2 + <0x1C0 &its 0x60 0x1>; //EMDIO + /* ENETC 0-2 BAR0 - non-prefetchable memory */ + ranges = <0x02000000 0x0 0x4cC80000 0x0 0x4cc80000 0x0 0xc0000 + /* Timer 1-2 and EMDIO BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4cda0000 0x0 0x4cda0000 0x0 0x60000 + /* Timer 1-2 and EMDIO BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce20000 0x0 0x4ce20000 0x0 0x30000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 + GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + + enetc0: ethernet@0,0 { + compatible = "pci1131,e101"; + reg = <0x10000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer1: ptp-timer@0,1 { + compatible = "pci1131,ee02"; + reg = <0x10100 0 0 0 0>; + status = "disabled"; + }; + + rcec@1,0 { + reg = <0x10800 0 0 0 0>; + interrupts = <1>; + }; + + enetc1: ethernet@8,0 { + compatible = "pci1131,e101"; + reg = <0x14000 0 0 0 0>; + status = "disabled"; + }; + + enetc2: ethernet@10,0 { + compatible = "pci1131,e101"; + reg = <0x18000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer2: ptp-timer@10,1 { + compatible = "pci1131,ee02"; + reg = <0x18100 0 0 0 0>; + status = "disabled"; + }; + + netc_emdio: mdio@18,0 { + compatible = "pci1131,ee00"; + reg = <0x1c000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + }; + ddr-pmu@4e090dc0 { compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu"; reg = <0x0 0x4e090dc0 0x0 0x200>; From bfc1982c660161c4a768b6696dc24b9f608aeea0 Mon Sep 17 00:00:00 2001 From: Wei Fang Date: Sun, 16 Nov 2025 09:35:58 +0800 Subject: [PATCH 109/757] arm64: dts: imx943-evk: add ENETC, EMDIO and PTP Timer support Add ENETC instance 1~3, EMDIO and PTP Timer 0~1 support. The EMDIO provides MDIO bus for ENETCs to access their external PHYs. The PTP Timer provides current time with nanosecond resolution, precise periodic pulse, pulse on timeout, and time capture on external pulse support. It also provides PTP clock for ENETCs to implement time synchronization as required for IEEE 1588 and IEEE 802.1AS-2020. Signed-off-by: Wei Fang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 100 +++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index c8c3eff9df1a..8b348f2941fa 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -12,6 +12,9 @@ model = "NXP i.MX943 EVK board"; aliases { + ethernet0 = &enetc3; + ethernet1 = &enetc1; + ethernet2 = &enetc2; i2c2 = &lpi2c3; i2c3 = &lpi2c4; i2c5 = &lpi2c6; @@ -127,6 +130,30 @@ }; }; +&enetc1 { + clocks = <&scmi_clk IMX94_CLK_MAC4>; + clock-names = "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth3>; + phy-handle = <ðphy3>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc2 { + clocks = <&scmi_clk IMX94_CLK_MAC5>; + clock-names = "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth4>; + phy-handle = <ðphy4>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc3 { + status = "okay"; +}; + &lpi2c3 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c3>; @@ -396,6 +423,39 @@ status = "okay"; }; +&netc_blk_ctrl { + assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>, + <&scmi_clk IMX94_CLK_MAC5>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>; + assigned-clock-rates = <250000000>, <250000000>; + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + status = "okay"; + + ethphy3: ethernet-phy@6 { + reg = <0x6>; + realtek,clkout-disable; + }; + + ethphy4: ethernet-phy@7 { + reg = <0x7>; + realtek,clkout-disable; + }; +}; + +&netc_timer0 { + status = "okay"; +}; + +&netc_timer1 { + status = "okay"; +}; + &sai1 { assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>, <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>, @@ -431,6 +491,46 @@ }; &scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC 0x57e + IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO 0x97e + >; + }; + + pinctrl_eth3: eth3grp { + fsl,pins = < + IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3 0x50e + IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2 0x50e + IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1 0x50e + IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0 0x50e + IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL 0x51e + IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK 0x59e + IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL 0x51e + IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK 0x59e + IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0 0x51e + IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1 0x51e + IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2 0x51e + IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3 0x51e + >; + }; + + pinctrl_eth4: eth4grp { + fsl,pins = < + IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x50e + IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2 0x50e + IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1 0x50e + IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0 0x50e + IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL 0x51e + IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x59e + IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL 0x51e + IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x59e + IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0 0x51e + IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1 0x51e + IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2 0x51e + IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x51e + >; + }; pinctrl_ioexpander_int2: ioexpanderint2grp { fsl,pins = < From 3619c5b41ec57e2f6a9eefea1fdc759dbfdc1c67 Mon Sep 17 00:00:00 2001 From: Yashwanth Varakala Date: Mon, 17 Nov 2025 13:45:14 +0100 Subject: [PATCH 110/757] arm64: dts: imx8mp libra: add and update display overlays Add imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso devicetree display overlay for the i.MX8MP Libra RDK platform. The overlay enable LVDS display configuration. To keep the consistent style of panel and backlight nodes and labels. They are updated in imx8mp-libra base board devicetree and etml1010g3dra display overlay. Signed-off-by: Yashwanth Varakala Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 8 +++- ...8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso | 2 +- ...ibra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso | 44 +++++++++++++++++++ .../dts/freescale/imx8mp-libra-rdk-fpsc.dts | 4 +- 4 files changed, 53 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f30d3fd724d0..050f50890fd8 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -225,8 +225,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc.dtb -imx8mp-libra-rdk-fpsc-lvds-dtbs += imx8mp-libra-rdk-fpsc.dtb imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo -dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds.dtb +imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo +imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso index 1dcf249ca90d..02889d691c01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso @@ -34,7 +34,7 @@ status = "okay"; }; -&panel0_lvds { +&panel_lvds0 { compatible = "edt,etml1010g3dra"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso new file mode 100644 index 000000000000..418c8536e791 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtso @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include + +/dts-v1/; +/plugin/; + +&backlight_lvds0 { + brightness-levels = <0 8 16 32 64 128 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; + num-interpolated-steps = <2>; + pwms = <&pwm1 0 66667 0>; + status = "okay"; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* + * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to + * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout + * engine can reach accurate pixel clock of exactly 66.5 MHz. + */ + assigned-clock-rates = <0>, <465500000>; + status = "okay"; +}; + +&panel_lvds0 { + compatible = "powertip,ph128800t006-zhc01"; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts index 6f3a7b863dca..ec1f10022248 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts @@ -15,7 +15,7 @@ "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp"; model = "PHYTEC i.MX8MP Libra RDK FPSC"; - backlight_lvds0: backlight0 { + backlight_lvds0: backlight-lvds0 { compatible = "pwm-backlight"; pinctrl-0 = <&pinctrl_lvds0>; pinctrl-names = "default"; @@ -27,7 +27,7 @@ stdout-path = &uart4; }; - panel0_lvds: panel-lvds { + panel_lvds0: panel-lvds0 { /* compatible panel in overlay */ backlight = <&backlight_lvds0>; power-supply = <®_vdd_3v3>; From b105f62a35a9a2814675b7754a6aa8e4963f4df1 Mon Sep 17 00:00:00 2001 From: Yashwanth Varakala Date: Mon, 17 Nov 2025 13:45:15 +0100 Subject: [PATCH 111/757] arm64: dts: imx8mp libra: add peb-av-10 expansion board overlay Add an overlay of expansion board (PEB-AV-10) that supports multimedia interfaces, 3.5mm headphone jack, a USB-A port and LVDS, backlight connectors can be connected to the imx8mp libra. Audio works when no display is connected to expansion board. A separate overlay for Powertip display, based on peb-av-10.dtsi and intended for use with PEB-AV-10 expansion board, will be added later as display support is not yet available. Signed-off-by: Yashwanth Varakala Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 + .../imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi | 196 ++++++++++++++++++ .../imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso | 9 + 3 files changed, 208 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 050f50890fd8..18e6f8217ec4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -229,8 +229,11 @@ imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra-dtbs += imx8mp-libra-rdk-fpsc.dtb \ imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtbo imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01-dtbs += imx8mp-libra-rdk-fpsc.dtb \ imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtbo +imx8mp-libra-rdk-fpsc-lvds-peb-av-10-dtbs += imx8mp-libra-rdk-fpsc.dtb \ + imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-ph128800t006-zhc01.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-enc-carrier-board.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi new file mode 100644 index 000000000000..57bbbdd734e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include "imx8mp-pinfunc.h" + +&{/} { + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pinctrl-0 = <&pinctrl_lvds1>; + pinctrl-names = "default"; + power-supply = <®_vcc_12v>; + status = "disabled"; + }; + + panel_lvds1: panel-lvds1 { + backlight = <&backlight_lvds1>; + power-supply = <®_vdd_3v3>; + status = "disabled"; + + port { + panel1_in: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; + + reg_vcc_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VCC_12V"; + }; + + reg_vcc_1v8_audio: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC_1V8_Audio"; + }; + + reg_vcc_3v3_analog: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3_Analog"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,codec { + sound-dai = <&codec>; + }; + + dailink_master: simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: audio-codec@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + pinctrl-0 = <&pinctrl_tlv320>; + pinctrl-names = "default"; + #sound-dai-cells = <0>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_vcc_3v3_analog>; + DRVDD-supply = <®_vcc_3v3_analog>; + DVDD-supply = <®_vcc_1v8_audio>; + IOVDD-supply = <®_vdd_3v3>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_vdd_3v3>; + }; +}; + +&ldb_lvds_ch1 { + remote-endpoint = <&panel1_in>; +}; + +&pwm2 { + pinctrl-0 = <&pinctrl_pwm2>; + pinctrl-names = "default"; +}; + +&sai5 { + pinctrl-0 = <&pinctrl_sai5>; + pinctrl-names = "default"; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", + "pll11k"; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + fsl,sai-synchronous-rx; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1e2 + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1e2 + >; + }; + + pinctrl_lvds1: lvds1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x12 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x12 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 + >; + }; + + pinctrl_tlv320: tlv320grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso new file mode 100644 index 000000000000..803a199dffa3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtso @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; +/plugin/; + +#include "imx8mp-libra-rdk-fpsc-lvds-peb-av-10.dtsi" From 0538ca1f102d87b2e98d38c7ca28915abee44777 Mon Sep 17 00:00:00 2001 From: Gregor Herburger Date: Mon, 17 Nov 2025 14:09:13 +0100 Subject: [PATCH 112/757] arm64: dts: ls1028a: Add mbls1028a and mbls1028a-ind devicetrees Add device trees for the MBLS1028A and the MBLS1028A-IND and the SoM TQMLS1028A. Signed-off-by: Gregor Herburger Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts | 68 +++++ .../fsl-ls1028a-tqmls1028a-mbls1028a.dts | 118 +++++++ .../fsl-ls1028a-tqmls1028a-mbls1028a.dtsi | 287 ++++++++++++++++++ .../dts/freescale/fsl-ls1028a-tqmls1028a.dtsi | 124 ++++++++ 5 files changed, 599 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 18e6f8217ec4..db3d56fc7db6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -16,6 +16,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-tqmls1028a-mbls1028a.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-tqmls1028a-mbls1028a-ind.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-tqmls1043a-mbls10xxa.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts new file mode 100644 index 000000000000..571b801c4f14 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a-ind.dts @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +/dts-v1/; + +#include "fsl-ls1028a-tqmls1028a-mbls1028a.dtsi" + +/ { + model = "MBLS1028A-IND starterkit"; + compatible = "tq,ls1028a-tqmls1028a-mbls1028a-ind", "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; +}; + +&i2c5 { + gpio_exp_3v3: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + #gpio-cells = <2>; + gpio-controller; + + clk-intn-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + input; + line-name = "CLK_INT#"; + }; + + mpcie-waken-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "MPCIE_WAKE#"; + }; + + mpcie-disn-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_DIS#"; + }; + + mpcie-rstn-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_RST#"; + }; + + sata-perstn-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SATA_PERST#"; + }; + + dcdc-reset-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "DCDC_RESET"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts new file mode 100644 index 000000000000..02563f982ff8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include +#include "fsl-ls1028a-tqmls1028a-mbls1028a.dtsi" + +/ { + model = "MBLS1028A starterkit"; + compatible = "tq,ls1028a-tqmls1028a-mbls1028a", "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; + + gpio-beeper { + compatible = "gpio-beeper"; + gpios = <&gpio_exp_3v3 15 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-0 { + label = "S4"; + linux,code = ; + gpios = <&gpio_exp_3v3 11 GPIO_ACTIVE_LOW>; + }; + + button-1 { + label = "S5"; + linux,code = ; + gpios = <&gpio_exp_3v3 12 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&gpio_exp_3v3 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio_exp_3v3 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpio_exp_1v8 { + dcdc-reset-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + line-name = "DCDC_RESET"; + output-low; + }; +}; + +&i2c5 { + gpio_exp_3v3: gpio@25 { + compatible = "nxp,pca9555"; + reg = <0x25>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3p3v>; + + clk-intn-hog { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + input; + line-name = "CLK_INT#"; + }; + + mpcie-waken-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + input; + line-name = "MPCIE_WAKE#"; + }; + + mpcie-disn-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_DIS#"; + }; + + mpcie-rstn-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "MPCIE_RST#"; + }; + + sata-perstn-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SATA_PERST#"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi new file mode 100644 index 000000000000..cf338b2e8006 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a-mbls1028a.dtsi @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +#include +#include +#include "fsl-ls1028a-tqmls1028a.dtsi" + +/ { + aliases { + crypto = &crypto; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + mmc0 = &esdhc; /* SD-Card */ + mmc1 = &esdhc1; /* eMMC */ + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = &duart0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + /* 256 MiB */ + size = <0 0x10000000>; + linux,cma-default; + }; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&dspi2 { + bus-num = <2>; + status = "okay"; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&esdhc { + cd-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + no-sdio; + no-1-8-v; + bus-width = <4>; + status = "okay"; +}; + +/* When switched to baseboard-internal i2c bus, + * IIC5 has access to the following devices. + */ +&i2c4 { + /* TUSB8041 only supports 100 KHz, but it is not connected */ + clock-frequency = <400000>; + status = "okay"; + + /* SI5338 - set up in U-Boot */ + /* clockgen@70 */ +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + gpio_exp_1v8: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <30 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_1p8v>; + + ec1-intn-hog { + gpio-hog; + gpios = <0 0>; + input; + line-name = "EC1_INT#"; + }; + + sgmii-intn-hog { + gpio-hog; + gpios = <2 0>; + input; + line-name = "SGMII_INT#"; + }; + + qsgmii-intn-hog { + gpio-hog; + gpios = <4 0>; + input; + line-name = "QSGMII_INT#"; + }; + + qsgmii-rstn-hog { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "QSGMII_RESET#"; + }; + }; +}; + +&enetc_mdio_pf3 { + mdio0_rgmii_phy00: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + reset-gpios = <&gpio_exp_1v8 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <1>; + reset-deassert-us = <200>; + interrupt-parent = <&gpio_exp_1v8>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,clk-output-sel = ; + ti,fifo-depth = ; + }; + + mdio0_sgmii_phy03: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x03>; + reset-gpios = <&gpio_exp_1v8 3 GPIO_ACTIVE_LOW>; + /* + * Long reset to work around PHY incorrect strap pin sampling + * due to external capacitors for SGMII + */ + reset-assert-us = <2500>; + reset-deassert-us = <200>; + interrupt-parent = <&gpio_exp_1v8>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + ti,clk-output-sel = ; + ti,fifo-depth = ; + }; + + qsgmii_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + qsgmii_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + qsgmii_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + qsgmii_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; +}; + +&enetc_port0 { + phy-handle = <&mdio0_sgmii_phy03>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <&mdio0_rgmii_phy00>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc_port2 { + status = "okay"; +}; + +&mscc_felix { + status = "okay"; +}; + +/* l2switch ports */ +&mscc_felix_port0 { + phy-handle = <&qsgmii_phy1>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port1 { + phy-handle = <&qsgmii_phy2>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port2 { + phy-handle = <&qsgmii_phy3>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port3 { + phy-handle = <&qsgmii_phy4>; + phy-mode = "qsgmii"; + status = "okay"; +}; + +&mscc_felix_port4 { + ethernet = <&enetc_port2>; + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb0 { + /* dual role is implemented, but not a full featured OTG */ + hnp-disable; + srp-disable; + adp-disable; + dr_mode = "otg"; + status = "okay"; +}; + +&usb1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3p3v>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio_exp_3v3 1 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3p3v>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi new file mode 100644 index 000000000000..dbf24dbc043b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-tqmls1028a.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright 2019-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Michael Krummsdorf + * Author: Matthias Schiffer + * Author: Alexander Stein + */ + +#include "fsl-ls1028a.dtsi" + +/ { + compatible = "tq,ls1028a-tqmls1028a", "fsl,ls1028a"; + + reg_1p8v_som: regulator-1p8v-som { + compatible = "regulator-fixed"; + regulator-name = "1P8V_SOM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v_som: regulator-3p3v-som { + compatible = "regulator-fixed"; + regulator-name = "3P3V_SOM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + thermal-zones { + /* + * TQMLS1028A uses an external temperature sensor + * instead of TMU + */ + /delete-node/ ddr-controller; + + cluster-thermal { + thermal-sensors = <&sa56004_4c 1>; + }; + }; +}; + +&esdhc1 { + no-sdio; + no-sd; + non-removable; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-ddr-1_8v; + bus-width = <8>; + vmmc-supply = <®_3p3v_som>; + vqmmc-supply = <®_1p8v_som>; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <®_1p8v_som>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + js42_18: temperature-sensor@18 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x18>; + }; + + sa56004_4c: temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + #thermal-sensor-cells = <1>; + vcc-supply = <®_3p3v_som>; + }; + + se97_50: eeprom@50 { + compatible = "nxp,se97b", "atmel,24c02"; + read-only; + reg = <0x50>; + pagesize = <16>; + vcc-supply = <®_3p3v_som>; + }; + + rtc1: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; + + m24c256_57: eeprom@57 { + compatible = "atmel,24c256"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3p3v_som>; + }; +}; + +/* + * We use a separate sensor IC to measure core temperature. Disable the TMU + * as its driver can cause log spam outside of its measurement range (0-125C). + * + * Will have to be reevaluated if this DTS is ported to a mainline kernel, + * as both sensors of the TMU are referenced by the default LS1028A + * thermal-zones definitions there. + */ +&tmu { + status = "disabled"; +}; From 51d857a0168a0101fb691a9191feed771aa78ecd Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 17 Nov 2025 14:09:12 +0100 Subject: [PATCH 113/757] dt-bindings: arm: fsl: add TQ-Systems boards MBLS1028A and MBLS1028A-IND Add two mainboards for the TQ-Systems TQMLS1028A SoM, based on the NXP Layerscape LS1028A. Signed-off-by: Matthias Schiffer Reviewed-by: Frank Li Acked-by: Conor Dooley Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 68a2d5fecc43..dfe9fa5c4dbc 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1672,6 +1672,15 @@ properties: - const: kontron,sl28 - const: fsl,ls1028a + - description: + TQ-Systems TQMLS1028A SoM on MBLS1028A/MBLS1028A-IND board + items: + - enum: + - tq,ls1028a-tqmls1028a-mbls1028a + - tq,ls1028a-tqmls1028a-mbls1028a-ind + - const: tq,ls1028a-tqmls1028a + - const: fsl,ls1028a + - description: LS1043A based Boards items: - enum: From def8f003d4f3fa5eac34e0d1ba3ba43b681e116a Mon Sep 17 00:00:00 2001 From: Rogerio Pimentel Date: Sun, 23 Nov 2025 13:14:43 -0500 Subject: [PATCH 114/757] dt-bindings: arm: fsl: Add i.MX8MP FRDM board Add device tree compatible string for the i.MX8MP FRDM board. Acked-by: Conor Dooley Signed-off-by: Rogerio Pimentel Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index dfe9fa5c4dbc..b94ce23aa8f6 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1099,6 +1099,7 @@ properties: - emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit - fsl,imx8mp-evk # i.MX8MP EVK Board - fsl,imx8mp-evk-revb4 # i.MX8MP EVK Rev B4 Board + - fsl,imx8mp-frdm # i.MX8MP Freedom Board - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board From 92ecc94b2786c71d52e193edad9fcb15cf1d923e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 20 Nov 2025 16:43:18 -0500 Subject: [PATCH 115/757] arm64: dts: mba8xx: replace 0 with IMX_LPCG_CLK_0 for lpcg indices Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the numerical value is identical, the LPCG input is defined as IMX_LPCG_CLK_, so using the symbolic constant improves clarity and consistency with the LPCG clock naming convention. Signed-off-by: Frank Li Reviewed-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/mba8xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi index f534dab44e8e..e32519b156d9 100644 --- a/arch/arm64/boot/dts/freescale/mba8xx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8xx.dtsi @@ -232,7 +232,7 @@ tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; - clocks = <&mclkout0_lpcg 0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; clock-names = "mclk"; iov-supply = <®_1v8>; ldoin-supply = <®_3v3>; @@ -343,7 +343,7 @@ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&sai1_lpcg 0>; + <&sai1_lpcg IMX_LPCG_CLK_0>; assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; From 4ea67ed403d922e9ad6a1289967e6a0aa1b7e73f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 20 Nov 2025 16:53:50 -0500 Subject: [PATCH 116/757] arm64: dts: imx8qxp-mek: Add sensors under i2c1 bus Add sensors under i2c1 bus. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 523f48896b6b..50a97c0297c7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -485,12 +485,38 @@ #size-cells = <0>; reg = <2>; + accelerometer@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + }; + + gyroscope@21 { + compatible = "nxp,fxas21002c"; + reg = <0x21>; + }; + pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; vdd-supply = <®_3v3>; vddio-supply = <®_3v3>; }; + + /* Ref SCH-54536 */ + inertial-meter@68 { + compatible = "invensense,icm20602"; + reg = <0x68>; + }; + + inertial-meter@69 { + compatible = "invensense,iam20380"; + reg = <0x69>; + }; + + pressure-sensor@77 { + compatible = "meas,ms5611"; + reg = <0x77>; + }; }; i2c@3 { @@ -520,6 +546,12 @@ interrupt-parent = <&lsio_gpio1>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; }; + + /* Ref SCH-54536 */ + light-sensort@60 { + compatible = "vishay,vcnl4035"; + reg = <0x60>; + }; }; }; From 81c6b6ffbda1ad077896e719a23c09c8690f2a9b Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 21 Nov 2025 08:31:40 +0100 Subject: [PATCH 117/757] arm64: dts: tqma8xxs: replace 0 with IMX_LPCG_CLK_0 for lpcg indices Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the numerical value is identical, the LPCG input is defined as IMX_LPCG_CLK_, so using the symbolic constant improves clarity and consistency with the LPCG clock naming convention. Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/tqma8xxs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi index 2d0a329c2fa5..ebf20d5b5df9 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi @@ -406,7 +406,7 @@ assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&sai1_lpcg 0>; + <&sai1_lpcg IMX_LPCG_CLK_0>; assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; From 7834d199a7d7e49e4ccb6a2dd465febb683026f0 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 21 Nov 2025 08:31:41 +0100 Subject: [PATCH 118/757] arm64: dts: tqma8xxs-mb-smarc-2: replace 0 with IMX_LPCG_CLK_0 for lpcg indices Replace the 0 with IMX_LPCG_CLK_0 for LPCG clock indices. Although the numerical value is identical, the LPCG input is defined as IMX_LPCG_CLK_, so using the symbolic constant improves clarity and consistency with the LPCG clock naming convention. Signed-off-by: Alexander Stein Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi index 3d20e3bf32ce..8bfe77113d64 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi @@ -130,7 +130,7 @@ tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; - clocks = <&mclkout0_lpcg 0>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; clock-names = "mclk"; iov-supply = <®_1v8>; ldoin-supply = <®_3v3>; From bb5b318f11e6f41c8cbb51848555f58b9ef175e6 Mon Sep 17 00:00:00 2001 From: Rogerio Pimentel Date: Sun, 23 Nov 2025 13:14:44 -0500 Subject: [PATCH 119/757] arm64: dts: add support for NXP i.MX8MP FRDM board The FRDM-i.MX8MP is an NXP development platform based on the i.MX8M Plus SoC, featuring a quad Cortex-A53, Cortex-M7 co-processor, 4GB LPDDR4, 32GB eMMC, Wi-Fi 6/Bluetooth 5.4/802.15.4 tri-radio, Ethernet, HDMI/MIPI display interfaces, camera connectors, and standard expansion headers. Based on the device tree found in the NXP repository at github https://github.com/nxp-imx-support/meta-imx-frdm and on imx8mp-evk board kernel mainline device tree. This is a basic device tree supporting: - Quad Cortex-A53 - 4GB LPDDR4 DRAM - PCA9450C PMIC with regulators - Two NXP PCAL6416 GPIO expanders - RGB LEDs via GPIO expander - I2C1, I2C2, I2C3 controllers - UART2 (console) and UART3 (with RTS/CTS) - USDHC3 (8-bit eMMC) - SNVS power key (onboard power button) Co-developed-by: Xiaofeng Wei Signed-off-by: Xiaofeng Wei Signed-off-by: Rogerio Pimentel Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mp-frdm.dts | 355 ++++++++++++++++++ 2 files changed, 356 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-frdm.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index db3d56fc7db6..862788fb3ea4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -214,6 +214,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts new file mode 100644 index 000000000000..55690f5e53d7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-frdm.dts @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model = "NXP i.MX8MPlus FRDM board"; + compatible = "fsl,imx8mp-frdm", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + label = "red"; + gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + label = "green"; + gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + led-2 { + label = "blue"; + gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0xc0000000>, + <0x1 0x00000000 0 0x40000000>; + }; +}; + +&A53_0 { + cpu-supply = <®_arm>; +}; + +&A53_1 { + cpu-supply = <®_arm>; +}; + +&A53_2 { + cpu-supply = <®_arm>; +}; + +&A53_3 { + cpu-supply = <®_arm>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_arm: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6416_0: gpio@20 { + compatible = "nxp,pcal6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416_0_int>; + interrupt-parent = <&gpio3>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "CSI1_nRST", + "CSI2_nRST", + "DSI_CTP_RST", + "EXT_PWREN1", + "CAN_STBY", + "EXP_P0_5", + "EXP_P0_6", + "P0_7", + "LVDS0_BLT_EN", + "LVDS1_BLT_EN", + "LVDS0_CTP_RST", + "LVDS1_CTP_RST", + "SPK_PWREN", + "RLED_GPIO", + "GLED_GPIO", + "BLED_GPIO"; + }; + + pcal6416_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416_1_int>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "P0_0", + "P0_1", + "AUD_nINT", + "RTC_nINTA", + "USB1_SS_SEL", + "USB2_PWR_EN", + "SPI_EXP_SEL", + "P0_7", + "W2_HOST_WAKE_SD_3V3", + "W2_HOST_WAKE_BT_3V3", + "EXP_WIFI_BT_PDN_3V3", + "EXP_BT_RST_3V3", + "W2_RST_IND_3V3", + "SPI_nINT_3V3", + "KEYM_PCIE_nWAKE", + "P1_7"; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_pcal6416_0_int: pcal6416-0-int-grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x146 + >; + }; + + pinctrl_pcal6416_1_int: pcal6416-1-int-grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x146 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; +}; From fb617c00e4ed993e85cb475a863a369fb9a27fe7 Mon Sep 17 00:00:00 2001 From: Daniel Schultz Date: Mon, 24 Nov 2025 01:22:42 -0800 Subject: [PATCH 120/757] arm64: dts: imx8mm: Add label to thermal-zones Add 'thermal_zones' as a label to the thermal-zones node. Without this label, it is not possible to add additional trip points in board files. For example, to add an active trip point for controlling a fan. Signed-off-by: Daniel Schultz Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index fc3cd639310e..9f49c0b386d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -234,7 +234,7 @@ arm,no-tick-in-suspend; }; - thermal-zones { + thermal_zones: thermal-zones { cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; From a4f7357d5328cf6d005853a783229320d68d1f6a Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 26 Nov 2025 16:06:44 +0800 Subject: [PATCH 121/757] arm64: dts: imx943-evk: add flexcan support Add flexcan2 and flexcan4, and related phys support. Signed-off-by: Haibo Chen Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 44 ++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 8b348f2941fa..98938391497e 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -28,6 +28,22 @@ #sound-dai-cells = <1>; }; + flexcan2_phy: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&pcal6416_i2c6_u50 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + standby-gpios = <&pcal6416_i2c6_u50 4 GPIO_ACTIVE_LOW>; + }; + + flexcan4_phy: can-phy1 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&pcal6416_i2c3_u171 0 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + standby-gpios = <&pcal6416_i2c3_u171 1 GPIO_ACTIVE_LOW>; + }; + chosen { stdout-path = &lpuart1; }; @@ -154,6 +170,20 @@ status = "okay"; }; +&flexcan2 { + phys = <&flexcan2_phy>; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan4 { + phys = <&flexcan4_phy>; + pinctrl-0 = <&pinctrl_flexcan4>; + pinctrl-names = "default"; + status = "okay"; +}; + &lpi2c3 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c3>; @@ -532,6 +562,20 @@ >; }; + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX94_PAD_GPIO_IO34__CAN2_TX 0x39e + IMX94_PAD_GPIO_IO35__CAN2_RX 0x39e + >; + }; + + pinctrl_flexcan4: flexcan4grp { + fsl,pins = < + IMX94_PAD_GPIO_IO36__CAN4_TX 0x39e + IMX94_PAD_GPIO_IO37__CAN4_RX 0x39e + >; + }; + pinctrl_ioexpander_int2: ioexpanderint2grp { fsl,pins = < IMX94_PAD_CCM_CLKO4__GPIO4_IO3 0x31e From e00ac93be0121c866163094572d4517f2699ad3f Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 26 Nov 2025 04:42:18 -0800 Subject: [PATCH 122/757] arm64: dts: imx8ulp: add sim lpav node Add DT node for the SIM LPAV module. Reviewed-by: Daniel Baluta Reviewed-by: Frank Li Signed-off-by: Laurentiu Mihalcea Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 13b01f3aa2a4..9b5d98766512 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -776,6 +776,23 @@ "ch28", "ch29", "ch30", "ch31"; }; + sim_lpav: clock-controller@2da50000 { + compatible = "fsl,imx8ulp-sim-lpav"; + reg = <0x2da50000 0x10000>; + clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>, + <&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>; + clock-names = "bus", "core", "plat"; + #clock-cells = <1>; + #reset-cells = <1>; + + sim_lpav_mux: mux-controller { + compatible = "reg-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x8 0x00000200>; + }; + }; + cgc2: clock-controller@2da60000 { compatible = "fsl,imx8ulp-cgc2"; reg = <0x2da60000 0x10000>; From adee0d6614349ab06e4a7766139803609a891fda Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 1 Dec 2025 15:58:43 +0900 Subject: [PATCH 123/757] arm64: dts: imx93-14x14-evk: Add bt-sco sound card support Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default. Signed-off-by: Chancel Liu Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-14x14-evk.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index f9eebd27d640..e47fee24471a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -27,6 +27,11 @@ serial0 = &lpuart1; }; + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + chosen { stdout-path = &lpuart1; }; @@ -168,6 +173,25 @@ regulator-max-microvolt = <1800000>; }; + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; + usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; @@ -371,6 +395,16 @@ status = "okay"; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -568,6 +602,15 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e From 4e6c3b68c1d51a74b65de9c2dfeb9734fbb8208a Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Mon, 1 Dec 2025 15:58:44 +0900 Subject: [PATCH 124/757] arm64: dts: imx93-14x14-evk: Add audio XCVR sound card Add audio XCVR sound card, which supports SPDIF TX & RX only, eARC RX, ARC RX are not supported. Signed-off-by: Chancel Liu Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-14x14-evk.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts index e47fee24471a..61843b2c1b1b 100644 --- a/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts @@ -192,6 +192,19 @@ }; }; + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + usdhc3_pwrseq: usdhc3_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; @@ -468,6 +481,17 @@ status = "okay"; }; +&xcvr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + &iomuxc { pinctrl_flexcan1: flexcan1grp { fsl,pins = < @@ -611,6 +635,13 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX93_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e From b53eb75f26ddfffd61f4f5d5914a5d47fd1fbbf3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:24:25 +0100 Subject: [PATCH 125/757] arm64: dts: cix: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251223152424.155253-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index 64b76905cbff..fb8c826bbc97 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -523,7 +523,7 @@ reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, - <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; + <0x43000000 0x0c 0x00000000 0x0c 0x00000000 0x04 0x00000000>; #address-cells = <3>; #size-cells = <2>; bus-range = <0x30 0x5f>; From b49f2dece02501c0684de70b7e00d1f7742aac88 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 1 Dec 2025 08:03:33 +0100 Subject: [PATCH 126/757] arm64: dts: tqmls1046a: Move BMAN/QMAN buffers to DRAM1 area DRAM1 is only 2GiB in size (0x00_8000_0000 - 0x01_0000_0000) which is already used by Linux kernel, etc. Move the allocation area of BMAN and QMAN to DRAM1 region. This frees the complete DRAM2 area for e.g. CMA. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi index fa543db99def..7059ab8bc9d4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi @@ -10,6 +10,18 @@ #include "fsl-ls1046a.dtsi" #include "tqmls10xxa.dtsi" +&bman_fbpr { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + +&qman_fqd { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + +&qman_pfdr { + alloc-ranges = <0 0x88000000 1 0x00000000>; +}; + &qspi { num-cs = <2>; status = "okay"; From 21335bc94ac3a5ac1d5b4ef36a232256a3da2dbd Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 2 Dec 2025 14:04:33 +0800 Subject: [PATCH 127/757] arm64: dts: imx93-9x9-qsb: add CAN support overlay file CAN1 and Micfil share pins on imx93-9x9-qsb board, use TMUX1574RSVR to control the connection: put sel to high, select CAN1, put sel to low, select Micfil. In default, sel keep low. To support CAN1, need to put the sel to high. Besides, CAN1 use phy TJA1057GT/3. Signed-off-by: Haibo Chen Reviewed-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/imx93-9x9-qsb-can1.dtso | 63 +++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 862788fb3ea4..f25bebabf558 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -382,7 +382,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb +imx93-9x9-qsb-can1-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-can1.dtbo imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso new file mode 100644 index 000000000000..0bf1e9d4bad2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-can1.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include +#include "imx93-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&flexcan1 { + phys = <&flexcan_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + >; + }; +}; + +/* micfi1 use the A port, conflict with can1 */ +&micfil { + status = "disabled"; +}; + +&pcal6524 { + /* + * mic-can-sel-hog have property 'output-low', dt overlay don't + * support /delete-property/. Both 'output-low' and 'output-high' + * will be exist under hog nodes if overlay file set 'output-high'. + * Workaround is disable this hog and create new hog with + * 'output-high'. + */ + mic-can-sel-hog { + status = "disabled"; + }; + + /* + * Config the MIC/CAN_SEL to high, chose B + * port, connect to CAN. + */ + mic-can-high-sel-hog { + gpio-hog; + gpios = <0x11 0x00>; + output-high; + }; +}; From c3085bef552f9cbf68b6b944bcad332c217fdf16 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:01 +0900 Subject: [PATCH 128/757] arm64: dts: imx91-11x11-evk: Refine label and node name of WM8962 Refine label with "wm8962" and node name with "codec" to follow devicetree specification. Signed-off-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index aca78768dbd4..90a4d1061d4a 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -132,7 +132,7 @@ pinctrl-names = "default"; status = "okay"; - audio_codec: wm8962@1a { + wm8962: audio-codec@1a { compatible = "wlf,wm8962"; reg = <0x1a>; clocks = <&clk IMX93_CLK_SAI3_GATE>; From 08a4d6fb6488136a96b390534f4f6d6e939a4622 Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:02 +0900 Subject: [PATCH 129/757] arm64: dts: imx91-11x11-evk: Add bt-sco sound card support Add bt-sco sound card, which is used by BT HFP case. It supports wb profile as default. Signed-off-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91-11x11-evk.dts | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 90a4d1061d4a..c9cb122094e7 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -31,6 +31,11 @@ serial4 = &lpuart5; }; + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + chosen { stdout-path = &lpuart1; }; @@ -77,6 +82,25 @@ linux,cma-default; }; }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + }; }; &adc1 { @@ -372,6 +396,17 @@ }; }; +&sai1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-1 = <&pinctrl_sai1_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { adp-disable; disable-over-current; @@ -528,6 +563,24 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e + MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1sleepgrp { + fsl,pins = < + MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e + MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e + MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e + MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e + >; + }; + pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e From 3529bf1c7d9e483967151ddb14c76a38c255a54e Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:03 +0900 Subject: [PATCH 130/757] arm64: dts: imx91-11x11-evk: Add WM8962 sound card support Add WM8962 sound card support which connects to SAI3. Signed-off-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91-11x11-evk.dts | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index c9cb122094e7..6b26ecfd06c9 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -83,6 +83,22 @@ }; }; + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + audio-cpu = <&sai3>; + audio-codec = <&wm8962>; + hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC", + "IN1R", "AMIC"; + }; + sound-bt-sco { compatible = "simple-audio-card"; simple-audio-card,name = "bt-sco-audio"; @@ -407,6 +423,17 @@ status = "okay"; }; +&sai3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-1 = <&pinctrl_sai3_sleep>; + assigned-clocks = <&clk IMX93_CLK_SAI3>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { adp-disable; disable-over-current; @@ -581,6 +608,26 @@ >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e + MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e + MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e + MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + >; + }; + + pinctrl_sai3_sleep: sai3sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e + MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e + MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e + MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e + MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e + >; + }; + pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e From c85b67e2ab5f8f8a03d96cf8e082647066e312de Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:04 +0900 Subject: [PATCH 131/757] arm64: dts: imx91-11x11-evk: Add PDM microphone sound card support Add PDM micphone sound card support. This sound card supports recording sound from PDM microphone and convert the PDM format data to PCM data. Signed-off-by: Chancel Liu Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91-11x11-evk.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index 6b26ecfd06c9..b0a295993dba 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -117,6 +117,20 @@ dai-tdm-slot-width = <16>; }; }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; }; &adc1 { @@ -412,6 +426,16 @@ }; }; +&micfil { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-1 = <&pinctrl_pdm_sleep>; + assigned-clocks = <&clk IMX93_CLK_PDM>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + &sai1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_sai1>; @@ -590,6 +614,22 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__PDM_CLK 0x31e + MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e + MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e + >; + }; + + pinctrl_pdm_sleep: pdmsleepgrp { + fsl,pins = < + MX91_PAD_PDM_CLK__GPIO1_IO8 0x51e + MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x51e + MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x51e + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e From 7b43479e4e1467ea3750d4cc5b12385ceec0364b Mon Sep 17 00:00:00 2001 From: Chancel Liu Date: Wed, 3 Dec 2025 16:06:05 +0900 Subject: [PATCH 132/757] arm64: dts: imx91-11x11-evk: Add audio XCVR sound card support Add audio XCVR sound card, which supports SPDIF TX & RX only, eARC RX, ARC RX are not supported. Signed-off-by: Chancel Liu Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx91-11x11-evk.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts index b0a295993dba..03f460d62f7a 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts @@ -131,6 +131,19 @@ }; }; }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; }; &adc1 { @@ -523,6 +536,18 @@ status = "okay"; }; +&xcvr { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-1 = <&pinctrl_spdif_sleep>; + assigned-clocks = <&clk IMX93_CLK_SPDIF>, + <&clk IMX93_CLK_AUDIO_XCVR>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; + assigned-clock-rates = <12288000>, <200000000>; + status = "okay"; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -668,6 +693,20 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e + MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e + >; + }; + + pinctrl_spdif_sleep: spdifsleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO22__GPIO2_IO22 0x51e + MX91_PAD_GPIO_IO23__GPIO2_IO23 0x51e + >; + }; + pinctrl_lpi2c3: lpi2c3grp { fsl,pins = < MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e From 749fdd12321d3fa0fb6118d315a8ec9b126f583f Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Fri, 5 Dec 2025 10:33:25 +0100 Subject: [PATCH 133/757] arm64: dts: imx8mp-phyboard-pollux: add fan-supply Add 5v regulator to gpio fan node. Reviewed-by: Frank Li Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 9687b4ded8f4..6203e39bc01b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -31,6 +31,7 @@ compatible = "gpio-fan"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fan>; + fan-supply = <®_vcc_5v_sw>; gpio-fan,speed-map = <0 0 13000 1>; gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; From 26927206df533ef58c0123857fc4d17101e65b0a Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Fri, 5 Dec 2025 10:33:26 +0100 Subject: [PATCH 134/757] arm64: dts: imx8mp-phycore-som: add spi-nor supply vcc The spi flash on the SoM is missing its vcc supply definition. Add missing regulator which supplies the flash with 1.8V. Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index 88831c0fbb7b..63adb1c4b3eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -28,6 +28,13 @@ regulator-min-microvolt = <3300000>; regulator-name = "VDD_IO"; }; + + reg_vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8"; + }; }; &A53_0 { @@ -83,6 +90,7 @@ spi-max-frequency = <80000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; + vcc-supply = <®_vdd_1v8>; }; }; From 18c783cf09aadf0eab9d6a75806f7aebe559080e Mon Sep 17 00:00:00 2001 From: Stefan Riedmueller Date: Fri, 5 Dec 2025 10:33:27 +0100 Subject: [PATCH 135/757] arm64: dts: imx8mp-phyboard-pollux: Enable i2c3 The i2c3 of the phyBOARD-Pollux is used on the CSI1 interface to connect to imaging sensors. Thus define it so it can be easily enabled if required. Signed-off-by: Stefan Riedmueller Signed-off-by: Teresa Remmet Reviewed-by: Frank Li Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- .../freescale/imx8mp-phyboard-pollux-rdk.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 6203e39bc01b..7d34b820e321 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -228,6 +228,15 @@ }; }; +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + &ldb_lvds_ch1 { remote-endpoint = <&panel1_in>; }; @@ -442,6 +451,20 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1e2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1e2 + >; + }; + pinctrl_lvds1: lvds1grp { fsl,pins = < MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 From e4d60417f6f654bc5d3e0b074f48983861007d47 Mon Sep 17 00:00:00 2001 From: Yannic Moog Date: Fri, 5 Dec 2025 10:33:28 +0100 Subject: [PATCH 136/757] arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-05 expansion board PEB-WLBT-05 is an expansion board that provides WIFI and Bluetooth functionality. It features the Ezurio Sterling LWB module [1]. Add missing regulator to baseboard dts. [1] https://www.ezurio.com/wireless-modules/wifi-modules-bluetooth/sterling-lwb-24-ghz-wifi-4-bt-51-module Signed-off-by: Yannic Moog Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 3 + .../imx8mp-phyboard-pollux-peb-wlbt-05.dtso | 108 ++++++++++++++++++ .../freescale/imx8mp-phyboard-pollux-rdk.dts | 7 ++ 3 files changed, 118 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index f25bebabf558..e3027dc9e6c0 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -253,12 +253,15 @@ imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ imx8mp-phyboard-pollux-ph128800t006.dtbo imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo +imx8mp-phyboard-pollux-wlbt-dtbs += imx8mp-phyboard-pollux-rdk.dtb \ + imx8mp-phyboard-pollux-peb-wlbt-05.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-wlbt.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-prt8ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso new file mode 100644 index 000000000000..0e98f4d94271 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-wlbt-05.dtso @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include "imx8mp-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + wlbt_clock: clock-32768 { + compatible = "fixed-clock"; + clock-accuracy = <20000>; + clock-frequency = <32768>; + clock-output-names = "WIFIBT_SLOW_CLK"; + #clock-cells = <0>; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <250>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140 /* RTS */ + MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 /* CTS */ + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 /* RX */ + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 /* TX */ + >; + }; + + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x106 /* BT_DEV_WAKE_EXP */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x106 /* BT_REG_ON_EXP */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x106 /* BT_HOST_WAKE_EXP */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 /* SDIO_CLK */ + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 /* SDIO_CMD */ + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 /* SDIO_D0 */ + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 /* SDIO_D1 */ + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 /* SDIO_D2 */ + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 /* SDIO_D3 */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x106 /* WL_REG_ON_EXP */ + >; + }; +}; + +&uart3 { + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-0 = <&pinctrl_uart3>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-0 = <&pinctrl_bluetooth>; + pinctrl-names = "default"; + clock-names = "lpo"; + clocks = <&wlbt_clock>; + device-wakeup-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + shutdown-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_vcc_3v3_sw>; + vddio-supply = <®_vcc_1v8_exp_con>; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; + bus-width = <4>; + max-frequency = <50000000>; + mmc-pwrseq = <&usdhc1_pwrseq>; + non-removable; + vmmc-supply = <®_vcc_3v3_sw>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + pinctrl-0 = <&pinctrl_wifi>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 7d34b820e321..90ec73068a6d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -119,6 +119,13 @@ regulator-max-microvolt = <3300000>; }; + reg_vcc_1v8_exp_con: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VCC_1V8_EXP_CON"; + }; + thermal-zones { soc-thermal { trips { From 8071668e66e523f36ea57b22f00a73ae63afc5f7 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 5 Dec 2025 19:22:54 +0100 Subject: [PATCH 137/757] arm64: dts: imx93-var-som-symphony: Update gpio aliases This patch introduces 2 simple aliases: Add a gpio3->gpio4 alias to allow flexible access to these GPIOs Add a gpio4 alias for the PCA9534 GPIO expander. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index c789c1f24bdc..00bdd3b91fdc 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -20,6 +20,8 @@ gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &pca9534; i2c0 = &lpi2c1; i2c1 = &lpi2c2; i2c2 = &lpi2c3; From 3860538ff7ee027f152d83084a036a84e2cb220b Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 5 Dec 2025 19:22:55 +0100 Subject: [PATCH 138/757] arm64: dts: imx93-var-som-symphony: Add support for ft5x06 touch controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Symphony carrier board exposes a capacitive touch interface through an FFC/FPC connector. This interface is wired to an FT5x06 touch controller on the I2C bus when using Variscite’s 7-inch capacitive touch display. This patch adds the FT5x06 device node to describe the actual hardware connection and enables touch functionality on the Symphony board Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-var-som-symphony.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 00bdd3b91fdc..39bfbd0428a9 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -208,6 +208,21 @@ sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; status = "okay"; + /* Capacitive touch controller */ + ft5x06_ts: touchscreen@38 { + compatible = "edt,edt-ft5206"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_captouch>; + interrupt-parent = <&gpio2>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + wakeup-source; + }; + /* DS1337 RTC module */ rtc@68 { compatible = "dallas,ds1337"; @@ -272,6 +287,12 @@ }; &iomuxc { + pinctrl_captouch: captouchgrp { + fsl,pins = < + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e From e35fffafd8a4e960296b017a461081bd6bff7cda Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 5 Dec 2025 19:22:56 +0100 Subject: [PATCH 139/757] arm64: dts: imx93-var-som-symphony: Add USB support The Symphony carrier board includes a USB Type-C connector on the USB1 port through an NXP PTN5150 Type-C controller connected on the I2C bus. The PTN5150 provides cable orientation detection and role switching information to the USB controller. This patch adds the PTN5150 node, its interrupt line, the required pin muxing, and wires the controller to the USB1 OTG dual-role device using the USB role-switch framework. This patch adds also USB2 support, that remains in host-only mode, matching the hardware capabilities of the Symphony board. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-var-som-symphony.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index 39bfbd0428a9..ee69d6b268a4 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -251,6 +251,22 @@ #gpio-cells = <2>; wakeup-source; }; + + /* USB Type-C Controller */ + ptn5150: typec@3d { + compatible = "nxp,ptn5150"; + reg = <0x3d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5150>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_NONE>; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; }; /* Console */ @@ -267,6 +283,29 @@ status = "okay"; }; +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + /* SD */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -351,6 +390,12 @@ >; }; + pinctrl_ptn5150: ptn5150grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX93_PAD_UART1_RXD__LPUART1_RX 0x31e From 4139384b586b916c8826483331f0054a65767f97 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Fri, 5 Dec 2025 19:22:57 +0100 Subject: [PATCH 140/757] arm64: dts: imx93-var-som-symphony: Enable LPSPI6 controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the LPSPI6 controller so it can be used by user applications through the board’s expansion connector. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx93-var-som-symphony.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index ee69d6b268a4..c0842fb3cfa3 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -276,6 +276,13 @@ status = "okay"; }; +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + /* J18.7, J18.9 */ &lpuart6 { pinctrl-names = "default"; @@ -384,6 +391,15 @@ >; }; + pinctrl_lpspi6: lpspi6grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__GPIO2_IO00 0x31e + MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x31e + MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x31e + MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x31e + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e From 99bd26b4e5dc12854404bce585b33a9c28c30d3d Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 09:57:46 +0100 Subject: [PATCH 141/757] arm64: dts: freescale: imx8-apalis: Add ethernet alias Add alias for the apalis first ethernet interface, this ensures consistent interface naming (e.g. `end0`) and this is used by the firmware to correctly set the MAC address. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 9153dddfd3b8..6fc82b5eb58c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -6,6 +6,10 @@ #include / { + aliases { + ethernet0 = &fec1; + }; + chosen { stdout-path = &lpuart1; }; From 98b8de62e846617cdb75c0f480d35cb37d3bc447 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 11:17:49 +0100 Subject: [PATCH 142/757] arm64: dts: freescale: imx8mp-verdin: Remove obsolete TODO comments Remove obsolete TODO comments, I2S interface is supported since Linux v6.6. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index d43ba0087126..d31f8082394f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -832,10 +832,6 @@ #pwm-cells = <3>; }; -/* TODO: Verdin I2S_1 */ - -/* TODO: Verdin I2S_2 */ - &snvs_pwrkey { status = "okay"; }; From 9cd778b49692bcdff5d709bd78190aa61a70193c Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 11:17:50 +0100 Subject: [PATCH 143/757] arm64: dts: freescale: imx8mp-verdin: enable hdmi_pai device Enable the hdmi_pai device on the various iMX8M Plus Verdin boards that feature the related HDMI interface. The hdmi_pai device, together with aud2htx module, hdmi_pai and hdmi controller compose the HDMI audio pipeline. See commit b21f87b8322f ("arm64: dts: imx8mp-evk: enable hdmi_pai device") for the equivalent change on the NXP i.MX8MP EVK board. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 1493319aa748..0e218e6b8e29 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -112,6 +112,10 @@ }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index a38e7c947a42..72a4f846d694 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -121,6 +121,10 @@ }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi index 11cf3bdc95c4..846b36706821 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi @@ -109,6 +109,10 @@ }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi index cc389cda2af2..f3d28e23ba6c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -123,6 +123,10 @@ }; /* Verdin HDMI_1 */ +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; From 53fb7a3aa55e7ce3968fa74982847872b08a6830 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 9 Dec 2025 11:17:51 +0100 Subject: [PATCH 144/757] arm64: dts: freescale: imx8mp-toradex-smarc: enable hdmi_pai device Enable the hdmi_pai device on the Toradex SMARC iMX8M Plus Development boards. The hdmi_pai device, together with aud2htx module, hdmi_pai and hdmi controller compose the HDMI audio pipeline. See commit b21f87b8322f ("arm64: dts: imx8mp-evk: enable hdmi_pai device") for the equivalent change on the NXP i.MX8MP EVK board. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts index 6f9dcd3a75c8..b31de307093c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc-dev.dts @@ -107,6 +107,10 @@ pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; From 2b1f623fc83dcbd8820fed3cec73c9138e27a246 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:07 +0100 Subject: [PATCH 145/757] arm64: dts: tqma8mpql-mba8mpxl: Adjust copyright text format Replace personal mail address by mailing list. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 59642a8a2c44..0605cf2faf83 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright 2021-2022 TQ-Systems GmbH - * Author: Alexander Stein + * Copyright 2021-2025 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein */ /dts-v1/; From 3494d778e8d1eff06f0636531379b2ae40e5a2e1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:08 +0100 Subject: [PATCH 146/757] arm64: dts: tqma8mpql-mba8mpxl: Fix Ethernet PHY IRQ support Ethernet PHY interrupt mode is level triggered. Adjust the mode accordingly. Reviewed-by: Andrew Lunn Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 0605cf2faf83..ff2bacf24bfd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -345,7 +345,7 @@ reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; }; }; }; @@ -375,7 +375,7 @@ reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; }; }; }; From 8401527abb5e3a00c867b6597b8e1b29c80c9824 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:09 +0100 Subject: [PATCH 147/757] arm64: dts: tqma8mpql-mba8mpxl: Fix HDMI CEC pad control settings As per datasheet of the HDMI protection IC the CEC_IC pin has been configured as open-drain. Fixes: 418d1d840e42 ("arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP") Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ff2bacf24bfd..03b75d4cf699 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -868,7 +868,7 @@ fsl,pins = , , , - ; + ; }; pinctrl_hoggpio2: hoggpio2grp { From 251f9c7ce592e3556a50a7547928262cbfd6d50e Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:10 +0100 Subject: [PATCH 148/757] arm64: dts: tqma8mpql-mba8mpxl: Add HDMI audio output support Add the HDMI audio soundcard and enable necessary nodes. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 03b75d4cf699..ac889a69da69 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -248,6 +248,13 @@ "Line Out Jack", "LOR"; }; + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; + thermal-zones { soc-thermal { trips { @@ -290,6 +297,10 @@ }; }; +&aud2htx { + status = "okay"; +}; + &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -486,6 +497,10 @@ "", "", "", ""; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; From 5c50503db36df8ed6d1e54f45ee6ea1bdbb5ca7d Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:11 +0100 Subject: [PATCH 149/757] arm64: dts: tqma8mpql-mba8mpxl: Configure IEEE 1588 event out signal The event out signal on channel 2 is available on pad SAI2_RXD0 which is connected to X63 pin 13. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ac889a69da69..fdfe246c5640 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -807,7 +807,8 @@ , , , - ; + , + ; }; pinctrl_eqos_event: eqosevtgrp { From 38bbf7903e8016587f62b614dffc757ff33889a1 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:12 +0100 Subject: [PATCH 150/757] arm64: dts: tqma8mpql-mba8mp-ras314: Fix Ethernet PHY IRQ support Ethernet PHY interrupt mode is level triggered. Adjust the mode accordingly. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index f7346b3d35fe..67fe1f63fd93 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -190,7 +190,7 @@ reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; @@ -222,7 +222,7 @@ reset-deassert-us = <50000>; enet-phy-lane-no-swap; interrupt-parent = <&gpio4>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; ti,rx-internal-delay = ; ti,tx-internal-delay = ; ti,fifo-depth = ; From 53a5c1d98d1155ece4c9446c0fea55e17d08774a Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:13 +0100 Subject: [PATCH 151/757] arm64: dts: tqma8mpql-mba8mp-ras314: Fix HDMI CEC pad control settings As per datasheet of the HDMI protection IC the CEC_IC pin has been configured as open-drain. Fixes: ddabb3ce3f90 ("arm64: dts: freescale: add TQMa8MPQL on MBa8MP-RAS314") Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index 67fe1f63fd93..30f0e81c4be0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -704,7 +704,7 @@ fsl,pins = , , , - ; + ; }; pinctrl_gpt1: gpt1grp { From ad7b5ed46c6815f2b9930d1a10b0cfa78695b495 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 9 Dec 2025 11:53:14 +0100 Subject: [PATCH 152/757] arm64: dts: tqma8mpql-mba8mp-ras314: Add HDMI audio output support Add the HDMI audio soundcard and enable necessary nodes. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index 30f0e81c4be0..6e927ff1e967 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -159,6 +159,17 @@ "Headphone Jack", "HPL", "Headphone Jack", "HPR"; }; + + sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + }; +}; + +&aud2htx { + status = "okay"; }; &ecspi3 { @@ -335,6 +346,10 @@ status = "disabled"; }; +&hdmi_pai { + status = "okay"; +}; + &hdmi_pvi { status = "okay"; }; From 4f0cee99186c452c7f51f41f6e8f63bf2f990428 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 9 Dec 2025 12:58:28 -0800 Subject: [PATCH 153/757] arm64: dts: imx8m{m,p}-venice-gw71xx: Add Magetometer Add support for the optional LIS2MDL magnetometer on GW71xx baseboards. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 15 +++++++++++++++ .../boot/dts/freescale/imx8mp-venice-gw71xx.dtsi | 15 +++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 429be2bab8a2..320806d3d073 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -92,6 +92,15 @@ interrupt-parent = <&gpio4>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>; }; + + magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; }; /* off-board header */ @@ -174,6 +183,12 @@ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x159 + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi index 4bf818873fe3..9317e62304e3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi @@ -101,6 +101,15 @@ interrupt-parent = <&gpio4>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; }; + + magnetometer@1e { + compatible = "st,lis2mdl"; + reg = <0x1e>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mag>; + interrupt-parent = <&gpio4>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + }; }; &pcie_phy { @@ -198,6 +207,12 @@ >; }; + pinctrl_mag: maggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x150 /* IRQ */ + >; + }; + pinctrl_gpio_leds: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ From 5d96e8677f75d7811aa1a697978961d320161af6 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 12 Dec 2025 09:58:59 +0100 Subject: [PATCH 154/757] dt-bindings: power: fsl,imx-gpc: Document address-cells The GPC power controller is an interrupt controllers and can be referenced in interrupt-map properties, e.g. PCIe controller, thus the node should have address-cells property. Signed-off-by: Alexander Stein Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml index 9de3fe73c1eb..d49a5130b87c 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml @@ -38,6 +38,9 @@ properties: reg: maxItems: 1 + "#address-cells": + const: 0 + interrupts: maxItems: 1 From 3c1df79fe708e6e5c321d540fb214ce630a54d85 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 12 Dec 2025 09:59:00 +0100 Subject: [PATCH 155/757] ARM: dts: imx6qdl: Add default GIC address cells Add missing address-cells 0 to GPC interrupt node to silence W=1 warning: imx6qdl.dtsi:281.4-284.29: Warning (interrupt_map): /soc/pcie@1ffc000:interrupt-map: Missing property '#address-cells' in node /soc/bus@2000000/gpc@20dc000, using 0 as fallback Value '0' is correct because: 1. GPC interrupt controller children are only power domains, 2. interrupt-map property (in PCI node) consists of five components and the fourth component "parent unit address", which size is defined by '#address-cells' of the node pointed to by the interrupt-parent component, is not used (=0) Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index 45bcfd7faf9d..9793feee6394 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -875,6 +875,7 @@ gpc: gpc@20dc000 { compatible = "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; + #address-cells = <0>; interrupt-controller; #interrupt-cells = <3>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; From 51eea410b977a071ee99593427e08b421d250188 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Dec 2025 17:57:19 +0800 Subject: [PATCH 156/757] arm64: dts: imx95-15x15-evk: Use phys to replace xceiver-supply The TJA1051T/3 used on i.MX95-15x15-EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li Acked-by: Marc Kleine-Budde Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index c1e245ecea9c..b934295bac15 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -107,12 +107,11 @@ gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>; }; - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "can2-stby"; - gpio = <&pcal6524 14 GPIO_ACTIVE_LOW>; + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 14 GPIO_ACTIVE_HIGH>; }; reg_m2_pwr: regulator-m2-pwr { @@ -318,7 +317,7 @@ &flexcan2 { pinctrl-0 = <&pinctrl_flexcan2>; pinctrl-names = "default"; - xceiver-supply = <®_can2_stby>; + phys = <&flexcan2_phy>; status = "okay"; }; From 3563aaa006af39f4072e114c883f2363cd26b51f Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Dec 2025 17:57:20 +0800 Subject: [PATCH 157/757] arm64: dts: imx8mp-evk: Use phys to replace xceiver-supply The TJA1048 used on i.MX8MP-EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li Acked-by: Marc Kleine-Budde Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 43 ++++++-------------- 1 file changed, 13 insertions(+), 30 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index c6facb2ad9aa..7ededc1a0617 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -56,6 +56,16 @@ <0x1 0x00000000 0 0xc0000000>; }; + flexcan_phy: can-phy { + compatible = "nxp,tja1048"; + #phy-cells = <1>; + max-bitrate = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_phy>; + standby-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>, + <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + native-hdmi-connector { compatible = "hdmi-connector"; label = "HDMI OUT"; @@ -103,28 +113,6 @@ enable-active-high; }; - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - regulator-name = "can1-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_can2_stby: regulator-can2-stby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_pcie0: regulator-pcie { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -431,14 +419,14 @@ &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_can1_stby>; + phys = <&flexcan_phy 0>; status = "okay"; }; &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_stby>; + phys = <&flexcan_phy 1>; status = "disabled";/* can2 pin conflict with pdm */ }; @@ -909,14 +897,9 @@ >; }; - pinctrl_flexcan1_reg: flexcan1reggrp { + pinctrl_flexcan_phy: flexcanphygrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */ - >; - }; - - pinctrl_flexcan2_reg: flexcan2reggrp { - fsl,pins = < MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */ >; }; From 753f9460a645296f656bf7fd4a85f55c411561fb Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 12 Dec 2025 17:57:21 +0800 Subject: [PATCH 158/757] arm64: dts: imx93-11x11-evk: Use phys to replace xceiver-supply The TJA1057 used on i.MX93 EVK is actually high-speed CAN transceiver, not a regulator supply. So use phys to reflect the truth. Reviewed-by: Frank Li Acked-by: Marc Kleine-Budde Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-evk.dts | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index b94a24193e19..8dd5340e8141 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -81,6 +81,13 @@ }; + flexcan_phy: can-phy { + compatible = "nxp,tja1057"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&adp5585 6 GPIO_ACTIVE_HIGH>; + }; + reg_vdd_12v: regulator-vdd-12v { compatible = "regulator-fixed"; regulator-name = "VDD_12V"; @@ -106,14 +113,6 @@ enable-active-high; }; - reg_can2_standby: regulator-can2-standby { - compatible = "regulator-fixed"; - regulator-name = "can2-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&adp5585 6 GPIO_ACTIVE_LOW>; - }; - reg_m2_pwr: regulator-m2-pwr { compatible = "regulator-fixed"; regulator-name = "M.2-power"; @@ -302,7 +301,7 @@ &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_can2_standby>; + phys = <&flexcan_phy>; status = "okay"; }; From 057ffbb1cfffbbf56eee68b5ebdcfdfa89adad40 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:48 +0100 Subject: [PATCH 159/757] arm64: dts: imx8mp-var-som: Move USDHC2 support to Symphony carrier The VAR-SOM-MX8MP module does not include a microSD slot connected to USDHC2. The USDHC2 interface is routed only on the Symphony carrier board, and it may optionally be used or omitted depending on the customer's carrier design. Move the USDHC2 node, its regulators, pinctrl groups and related GPIOs from the SOM device tree to the Symphony carrier DTS, keeping the SOM description limited to hardware populated on the module. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-var-som-symphony.dts | 77 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-var-som.dtsi | 75 ------------------ 2 files changed, 77 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 36d3eb865202..ea3c193bb684 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -8,4 +8,81 @@ / { model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp"; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + regulator-name = "VSD_VSEL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0 1800000 0x1>; + vin-supply = <&ldo5>; + }; +}; + +/* SD-card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 29f080904482..949d9878f395 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -35,27 +35,6 @@ <0x1 0x00000000 0 0xc0000000>; }; - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; - - reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { - compatible = "regulator-gpio"; - regulator-name = "VSD_VSEL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - states = <3300000 0x0 1800000 0x1>; - vin-supply = <&ldo5>; - }; - reg_phy_supply: regulator-phy-supply { compatible = "regulator-fixed"; regulator-name = "phy-supply"; @@ -271,19 +250,6 @@ status = "okay"; }; -/* SD-card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - bus-width = <4>; - status = "okay"; -}; - /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -358,47 +324,6 @@ >; }; - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 From 5ea98ce8b11969bae1441b5648b73242a9b99386 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:49 +0100 Subject: [PATCH 160/757] arm64: dts: imx8mp-var-som: Move PCA9534 GPIO expander to Symphony carrier The VAR-SOM-MX8MP module does not include the PCA9534 GPIO expander nor the LED connected to it. These components are present only on the Symphony carrier board and may vary across custom carrier designs. Move the PCA9534 GPIO expander node and the associated LED definition from the SOM device tree to the Symphony carrier DTS, ensuring the SOM dtsi describes only hardware present on the module. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-var-som-symphony.dts | 50 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-var-som.dtsi | 50 ------------------- 2 files changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index ea3c193bb684..361e6122bdc3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -9,6 +9,16 @@ model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp"; + gpio-leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -31,6 +41,33 @@ }; }; +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible = "nxp,pca9534"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9534>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + + usb3-sata-sel-hog { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "usb3_sata_sel"; + }; + }; +}; + /* SD-card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -45,6 +82,19 @@ }; &iomuxc { + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pca9534: pca9534grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 + >; + }; + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 949d9878f395..158a78ec9656 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -19,16 +19,6 @@ stdout-path = &uart2; }; - gpio-leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, @@ -216,33 +206,6 @@ }; }; -&i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - /* GPIO expander */ - pca9534: gpio@20 { - compatible = "nxp,pca9534"; - reg = <0x20>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9534>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - - usb3-sata-sel-hog { - gpio-hog; - gpios = <4 0>; - output-low; - line-name = "usb3_sata_sel"; - }; - }; -}; - /* Console */ &uart2 { pinctrl-names = "default"; @@ -298,19 +261,6 @@ >; }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 - >; - }; - - pinctrl_pca9534: pca9534grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0xc0 - >; - }; - pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1c0 From e5b8c6103a41ada6c40ff052c572cc811b45b32c Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:50 +0100 Subject: [PATCH 161/757] arm64: dts: imx8mp-var-som: Move UART2 description to Symphony carrier The VAR-SOM-MX8MP module does not provide an onboard debug console. UART2 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART. Move the UART2 node from the SOM device tree to the imx8mp-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mp-var-som-symphony.dts | 18 ++++++++++++++++++ .../boot/dts/freescale/imx8mp-var-som.dtsi | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 361e6122bdc3..291f65e36865 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -9,6 +9,10 @@ model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp"; + chosen { + stdout-path = &uart2; + }; + gpio-leds { compatible = "gpio-leds"; @@ -68,6 +72,13 @@ }; }; +/* Console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + /* SD-card */ &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -95,6 +106,13 @@ >; }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 + >; + }; + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 158a78ec9656..5bba91dcef17 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -15,10 +15,6 @@ / { model = "Variscite VAR-SOM-MX8M Plus module"; - chosen { - stdout-path = &uart2; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0xc0000000>, @@ -206,13 +202,6 @@ }; }; -/* Console */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -267,13 +256,6 @@ >; }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40 - MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 From 84095b3bd0cc836a112c8a1774edc7ea6fa43f69 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:51 +0100 Subject: [PATCH 162/757] arm64: dts: imx8mp-var-som: Add WiFi and Bluetooth support Add device tree nodes for the WiFi and Bluetooth module mounted on the VAR-SOM-MX8MP. The module can be based on either the NXP IW612 or IW611 chipset, depending on the configuration chosen by the customer. Regardless of the chipset used, WiFi communicates over SDIO and Bluetooth over UART. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-var-som.dtsi | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 5bba91dcef17..2c49d53e30c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -21,6 +21,14 @@ <0x1 0x00000000 0 0xc0000000>; }; + iw61x_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <10000>; + reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio2 19 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; + reg_phy_supply: regulator-phy-supply { compatible = "regulator-fixed"; regulator-name = "phy-supply"; @@ -202,6 +210,33 @@ }; }; +/* BT */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bluetooth>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + mmc-pwrseq = <&iw61x_pwrseq>; + status = "okay"; +}; + /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -222,6 +257,14 @@ &iomuxc { + pinctrl_bluetooth: bluetoothgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0xc0 + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0xc0 + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0xc0 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -256,6 +299,48 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 @@ -309,4 +394,11 @@ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 >; }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0xc0 + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0xc0 + >; + }; }; From cb452cc24ade40ebf3f0c592e1bad17c1b3cd693 Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:52 +0100 Subject: [PATCH 163/757] arm64: dts: imx8mp-var-som: Add support for WM8904 audio codec The VAR-SOM-MX8MP can integrate the WM8904, a high-performance ultra-low-power stereo codec optimized for portable audio applications. This patch adds the WM8904 device to the appropriate I2C bus, enables the SAI peripheral, and introduces the sound node to expose the sound card to the system. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-var-som.dtsi | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 2c49d53e30c3..6da5df11c44a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -29,6 +29,14 @@ <&gpio2 19 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ }; + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_phy_supply: regulator-phy-supply { compatible = "regulator-fixed"; regulator-name = "phy-supply"; @@ -46,6 +54,34 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + }; }; &A53_0 { @@ -208,6 +244,52 @@ }; }; }; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <®_audio_supply>; + CPVDD-supply = <®_audio_supply>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <®_audio_supply>; + MICVDD-supply = <®_audio_supply>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <11536000>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, + <&clk IMX8MP_CLK_DUMMY>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, + <&clk IMX8MP_CLK_DUMMY>, + <&clk IMX8MP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + fsl,sai-mclk-direction-output; + status = "okay"; }; /* BT */ @@ -299,6 +381,18 @@ >; }; + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0xd6 + >; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140 From e583afbe3568c654a221793019e77738ffd2946f Mon Sep 17 00:00:00 2001 From: Stefano Radaelli Date: Sun, 14 Dec 2025 22:52:53 +0100 Subject: [PATCH 164/757] arm64: dts: imx8mp-var-som: Add support for TSC2046 touchscreen The VAR-SOM-MX8MP integrates a TSC2046 resistive touchscreen controller. The controller is physically located on the SOM, and its signals are routed to the SOM pins, allowing carrier boards to make use of it. This patch adds the TSC2046 node and the appropriate SPI controller. Signed-off-by: Stefano Radaelli Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-var-som.dtsi | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 6da5df11c44a..49467b48d0b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -100,6 +100,37 @@ cpu-supply = <&buck2>; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* Resistive touch controller */ + tsc2046: touchscreen@0 { + compatible = "ti,tsc2046"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_restouch>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <1500000>; + pendown-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; + ti,x-min = /bits/ 16 <125>; + ti,x-max = /bits/ 16 <4008>; + ti,y-min = /bits/ 16 <282>; + ti,y-max = /bits/ 16 <3864>; + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + ti,debounce-max = /bits/ 16 <10>; + ti,debounce-tol = /bits/ 16 <3>; + ti,debounce-rep = /bits/ 16 <1>; + ti,settle-delay-usec = /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -347,6 +378,15 @@ >; }; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x12 + MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x12 + MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x12 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x12 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 @@ -381,6 +421,12 @@ >; }; + pinctrl_restouch: restouchgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0xc0 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 From fcef3fa00fcecc88b45526f83ea4df73d0e7dc77 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:31:04 +0100 Subject: [PATCH 165/757] arm64: dts: imx8mm-tqma8mqml: remove virtual 3.3V regulator BUCK4 rail supplies the 3.3V rail. Use the actual regulator instead of a virtual fixed regulator. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index b82e9790ea20..16ed8ce5b5c4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -24,14 +24,6 @@ regulator-max-microvolt = <1800000>; }; - /* identical to buck4_reg, but should never change */ - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -223,14 +215,14 @@ read-only; reg = <0x53>; pagesize = <16>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; }; @@ -253,7 +245,7 @@ non-removable; no-sd; no-sdio; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <&buck4_reg>; vqmmc-supply = <®_vcc1v8>; status = "okay"; }; From c5d2ecfe495e102fc6c29b3c76dba6b88153d1e0 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:31:05 +0100 Subject: [PATCH 166/757] arm64: dts: imx8mm-tqma8mqml: remove virtual 1.8V regulator BUCK5 regulator supplies the 1.8V rail. Use the actual regulator instead of a virtual fixed regulator. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 16ed8ce5b5c4..6e63cf8beadc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -16,14 +16,6 @@ reg = <0x00000000 0x40000000 0 0x40000000>; }; - /* e-MMC IO, needed for HS modes */ - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXML_VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -246,7 +238,7 @@ no-sd; no-sdio; vmmc-supply = <&buck4_reg>; - vqmmc-supply = <®_vcc1v8>; + vqmmc-supply = <&buck5_reg>; status = "okay"; }; From 7c9910ffdadb42428c96fa73715f292a445b3a37 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:31:06 +0100 Subject: [PATCH 167/757] arm64: dts: imx8mm-tqma8mqml: remove superfluous line Remove one empty line that is not needed. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 6e63cf8beadc..2e3860a5f4fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -195,7 +195,6 @@ }; }; - pcf85063: rtc@51 { compatible = "nxp,pcf85063a"; reg = <0x51>; From f7a65b08bcf5edb95697cf7a10435a1d051c9268 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:31:07 +0100 Subject: [PATCH 168/757] arm64: dts: imx8mm-tqma8mqml: fix LDO5 power off Fix SD card removal caused by automatic LDO5 power off after boot. To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled regulator that is supplied by LDO5. Since this is implemented on SoM but used on baseboards with SD-card interface, implement the functionality on SoM part and optionally enable it on baseboards if needed. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mm-tqma8mqml-mba8mx.dts | 13 ++++++----- .../boot/dts/freescale/imx8mm-tqma8mqml.dtsi | 22 +++++++++++++++++++ 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index b941c8c4f7bb..8dcc5cbcb8f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -101,6 +101,10 @@ status = "okay"; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MM_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; @@ -276,8 +280,7 @@ , , , - , - ; + ; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -286,8 +289,7 @@ , , , - , - ; + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -296,7 +298,6 @@ , , , - , - ; + ; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 2e3860a5f4fd..29b298af0d73 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -16,6 +16,20 @@ reg = <0x00000000 0x40000000 0 0x40000000>; }; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5_reg>; + status = "disabled"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -227,6 +241,10 @@ fsl,clkreq-unsupported; }; +&usdhc2 { + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -281,6 +299,10 @@ fsl,pins = ; }; + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = ; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = , , From cd09cbebfc8a4c76d74c2e7e1818a4c8cf3ca033 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:39:23 +0100 Subject: [PATCH 169/757] arm64: dts: imx8mn-tqma8mqnl: remove virtual 3.3V regulator BUCK4 rail supplies the 3.3V rail. Use the actual regulator instead of a virtual fixed regulator. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 1d23814e11cd..34d6415348f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -23,13 +23,6 @@ regulator-max-microvolt = <1800000>; }; - reg_vcc3v3: regulator-vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXNL_VCC3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -217,14 +210,14 @@ read-only; reg = <0x53>; pagesize = <16>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - vcc-supply = <®_vcc3v3>; + vcc-supply = <&buck4_reg>; }; }; @@ -242,7 +235,7 @@ non-removable; no-sd; no-sdio; - vmmc-supply = <®_vcc3v3>; + vmmc-supply = <&buck4_reg>; vqmmc-supply = <®_vcc1v8>; status = "okay"; }; From 8b6ffe54fde2375efdc034e253e71e8988da3c54 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:39:24 +0100 Subject: [PATCH 170/757] arm64: dts: imx8mn-tqma8mqnl: remove virtual 1.8V regulator BUCK5 regulator supplies the 1.8V rail. Use the actual regulator instead of a virtual fixed regulator. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 34d6415348f8..ac6ce5d814c5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -15,14 +15,6 @@ reg = <0x00000000 0x40000000 0 0x40000000>; }; - /* e-MMC IO, needed for HS modes */ - reg_vcc1v8: regulator-vcc1v8 { - compatible = "regulator-fixed"; - regulator-name = "TQMA8MXNL_VCC1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -236,7 +228,7 @@ no-sd; no-sdio; vmmc-supply = <&buck4_reg>; - vqmmc-supply = <®_vcc1v8>; + vqmmc-supply = <&buck5_reg>; status = "okay"; }; From 8adc841d43ebceabec996c9dcff6e82d3e585268 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Tue, 16 Dec 2025 14:39:25 +0100 Subject: [PATCH 171/757] arm64: dts: imx8mn-tqma8mqnl: fix LDO5 power off Fix SD card removal caused by automatic LDO5 power off after boot To prevent this, add vqmmc regulator for USDHC, using a GPIO-controlled regulator that is supplied by LDO5. Since this is implemented on SoM but used on baseboards with SD-card interface, implement the functionality on SoM part and optionally enable it on baseboards if needed. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts | 13 ++++++----- .../boot/dts/freescale/imx8mn-tqma8mqnl.dtsi | 22 +++++++++++++++++++ 2 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index d7f7f9aafb7d..0d009f4be804 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -69,6 +69,10 @@ samsung,esc-clock-frequency = <20000000>; }; +®_usdhc2_vqmmc { + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MN_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; @@ -216,8 +220,7 @@ , , , - , - ; + ; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { @@ -226,8 +229,7 @@ , , , - , - ; + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { @@ -236,8 +238,7 @@ , , , - , - ; + ; }; pinctrl_usdhc2_gpio: usdhc2-gpiogrp { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index ac6ce5d814c5..31a3ca137e63 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -15,6 +15,20 @@ reg = <0x00000000 0x40000000 0 0x40000000>; }; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>; + regulator-name = "V_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&ldo5_reg>; + status = "disabled"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -218,6 +232,10 @@ vddio-supply = <&ldo3_reg>; }; +&usdhc2 { + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -272,6 +290,10 @@ fsl,pins = ; }; + pinctrl_reg_usdhc2_vqmmc: regusdhc2vqmmcgrp { + fsl,pins = ; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = , , From 30e6d444b8dc5ae1f5dee1f3cda3a49864cd10fb Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 17 Dec 2025 09:48:04 +0100 Subject: [PATCH 172/757] arm64: dts: mb-smarc-2: Add PCIe support TQMa8XxS on MB-SMARC-2 supports mPCIe on X44. Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- .../boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi | 10 ++++++++++ arch/arm64/boot/dts/freescale/tqma8xxs.dtsi | 14 +++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi index 8bfe77113d64..050ae23c4dc1 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs-mb-smarc-2.dtsi @@ -126,6 +126,12 @@ status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &i2c0 { tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; @@ -156,6 +162,10 @@ status = "okay"; }; +&pcieb { + status = "okay"; +}; + ®_sdvmmc { off-on-delay-us = <200000>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi index ebf20d5b5df9..bfc918f18d01 100644 --- a/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi +++ b/arch/arm64/boot/dts/freescale/tqma8xxs.dtsi @@ -402,6 +402,14 @@ status = "okay"; }; +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &sai1 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, @@ -646,9 +654,9 @@ }; pinctrl_pcieb: pcieagrp { - fsl,pins = , - , - ; + fsl,pins = , + , + ; }; pinctrl_pwm_mipi_lvds0: mipi-lvds0-pwmgrp { From a95260063fb3e01878a28ed23f10241b9e138ae9 Mon Sep 17 00:00:00 2001 From: Fabian Pflug Date: Thu, 18 Dec 2025 12:39:21 +0100 Subject: [PATCH 173/757] dt-bindings: arm: fsl: add i.MX93 11x11 FRDM board Add DT compatible string for NXP i.MX93 11x11 FRDM board. Acked-by: Krzysztof Kozlowski Reviewed-by: Daniel Baluta Signed-off-by: Fabian Pflug Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b94ce23aa8f6..20b3a5d6aec2 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1420,6 +1420,7 @@ properties: - enum: - fsl,imx93-9x9-qsb # i.MX93 9x9 QSB Board - fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board + - fsl,imx93-11x11-frdm # i.MX93 11x11 FRDM Board - fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board - const: fsl,imx93 From eb2f28413e23c219188d3e1a2ce8bca9894f9832 Mon Sep 17 00:00:00 2001 From: Fabian Pflug Date: Thu, 18 Dec 2025 12:39:22 +0100 Subject: [PATCH 174/757] arm64: dts: freescale: add support for NXP i.MX93 FRDM The FRDM i.MX 93 development board is a low-cost and compact development board featuring the i.MX93 applications processor. It features: - Dual Cortex-A55 - 2 GB LPDDR4X / LPDDR4 - 32 GB eMMC5.1 - MicroSD slot - GbE RJ45 x 2 - USB2.0 1x Type C, 1x Type A This file is based upon the one provided by nxp in their own kernel and yocto meta layer for the device, but adapted for mainline. Signed-off-by: Haidong Zheng Signed-off-by: Danwei Luo Signed-off-by: Lei Xu Signed-off-by: Fabian Pflug Reviewed-by: Francesco Valla Tested-by: Francesco Valla Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx93-11x11-frdm.dts | 620 ++++++++++++++++++ 2 files changed, 621 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index e3027dc9e6c0..edb8332ed7e0 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -391,6 +391,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-can1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-nash.dtb diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts new file mode 100644 index 000000000000..066c5139842b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts @@ -0,0 +1,620 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/dts-v1/; + +#include +#include "imx93.dtsi" + +/ { + compatible = "fsl,imx93-11x11-frdm", "fsl,imx93"; + model = "NXP i.MX93 11X11 FRDM board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; /* EMMC */ + mmc1 = &usdhc2; /* uSD */ + rtc0 = &pcf2131; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + vin-supply = <&buck4>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + + rsc_table: rsc-table@2021e000 { + reg = <0 0x2021e000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4010000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + }; +}; + +&adc1 { + vref-supply = <&buck5>; + status = "okay"; +}; + +&mu1 { + status = "okay"; +}; + +&cm33 { + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; +}; + +&fec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy2>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + /* does not boot with supplier set, because it is the bucks interrupt parent */ + /* vcc-supply = <&buck4>; */ + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + regulators { + + buck1: BUCK1 { + regulator-name = "VDD_SOC_0V8"; + regulator-min-microvolt = <610000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "LPD4_x_VDDQ_0V6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <670000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6: BUCK6 { + regulator-name = "LPD4_x_VDD2_1V1"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1140000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1: LDO1 { + regulator-name = "NVCC_BBSM_1V8"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_ANA_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <840000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + pagesize = <64>; + vcc-supply = <&buck4>; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupt-parent = <&pcal6524>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&lpuart1 { /* console */ + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <&buck4>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = < + MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e + MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e + MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e + MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e + MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e + MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e + MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; From be1e3ea0cf76f2fa613220253a630308d19ae5d0 Mon Sep 17 00:00:00 2001 From: Teresa Remmet Date: Thu, 18 Dec 2025 13:00:06 +0100 Subject: [PATCH 175/757] arm64: dts: imx8mm-phycore-som: Update eth phy impedance Update the DP83867 ethernet phy impedance settings to to optimize signal quality and reduce potential signal integrity issues. Signed-off-by: Teresa Remmet Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 3d66c6701342..b764f7734868 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -83,6 +83,7 @@ enet-phy-lane-no-swap; ti,clk-output-sel = ; ti,fifo-depth = ; + ti,min-output-impedance; ti,rx-internal-delay = ; ti,tx-internal-delay = ; reg = <0>; From 6b4bcef0549e35b777896e5da0ec8af00fa942c1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Dec 2025 09:42:14 +0800 Subject: [PATCH 176/757] dt-bindings: arm: fsl: add i.MX952 EVK board Add DT compatible string for NXP i.MX952 EVK board. Acked-by: Krzysztof Kozlowski Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 20b3a5d6aec2..971846c60490 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1438,6 +1438,12 @@ properties: - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 + - description: i.MX952 based Boards + items: + - enum: + - fsl,imx952-evk # i.MX952 EVK Board + - const: fsl,imx952 + - description: PHYTEC i.MX 95 FPSC based Boards items: - enum: From b516a4dd6a1ff7ddbaf3ab30ddec88088a6ec9e6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Dec 2025 09:42:15 +0800 Subject: [PATCH 177/757] arm64: dts: freescale: Add initial device tree for i.MX952 i.MX952 is designed for AI-powered sensor fusion and vision sensing applications, it features 4 Corte-A55, 1 Cortex-M33, 1 Cortex-M7 and NXP eIQ NPU and advanced graphics, video and advanced security with edgelock. Product info could be found at: https://www.nxp.com/products/i.MX-952 The basic device tree includes: - clock, pin, power header files - device nodes: CPU[0-3], SCMI firmware, Interrupt Controller, Sys counter, eDMA, MU, SPI, UART, I2C, USB and etc Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-clock.h | 215 +++ .../arm64/boot/dts/freescale/imx952-pinfunc.h | 867 ++++++++++++ arch/arm64/boot/dts/freescale/imx952-power.h | 44 + arch/arm64/boot/dts/freescale/imx952.dtsi | 1248 +++++++++++++++++ 4 files changed, 2374 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx952-clock.h create mode 100644 arch/arm64/boot/dts/freescale/imx952-pinfunc.h create mode 100644 arch/arm64/boot/dts/freescale/imx952-power.h create mode 100644 arch/arm64/boot/dts/freescale/imx952.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx952-clock.h b/arch/arm64/boot/dts/freescale/imx952-clock.h new file mode 100644 index 000000000000..7d6f6635dc07 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-clock.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2025 NXP + */ + +#ifndef __CLOCK_IMX952_H__ +#define __CLOCK_IMX952_H__ + +/* Clock Source */ +#define IMX952_CLK_EXT 0 +#define IMX952_CLK_OSC32K 1 +#define IMX952_CLK_OSC24M 2 +#define IMX952_CLK_FRO 3 +#define IMX952_CLK_SYSPLL1_VCO 4 +#define IMX952_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX952_CLK_SYSPLL1_PFD0 6 +#define IMX952_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX952_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX952_CLK_SYSPLL1_PFD1 9 +#define IMX952_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX952_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX952_CLK_SYSPLL1_PFD2 12 +#define IMX952_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX952_CLK_AUDIOPLL1_VCO 14 +#define IMX952_CLK_AUDIOPLL1 15 +#define IMX952_CLK_AUDIOPLL2_VCO 16 +#define IMX952_CLK_AUDIOPLL2 17 +#define IMX952_CLK_VIDEOPLL1_VCO 18 +#define IMX952_CLK_VIDEOPLL1 19 +#define IMX952_CLK_SRC_RESERVED20 20 +#define IMX952_CLK_SYSPLL1_PFD3_UNGATED 21 +#define IMX952_CLK_SYSPLL1_PFD3 22 +#define IMX952_CLK_SYSPLL1_PFD3_DIV2 23 +#define IMX952_CLK_ARMPLL_VCO 24 +#define IMX952_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX952_CLK_ARMPLL_PFD0 26 +#define IMX952_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX952_CLK_ARMPLL_PFD1 28 +#define IMX952_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX952_CLK_ARMPLL_PFD2 30 +#define IMX952_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX952_CLK_ARMPLL_PFD3 32 +#define IMX952_CLK_DRAMPLL_VCO 33 +#define IMX952_CLK_DRAMPLL 34 +#define IMX952_CLK_HSIOPLL_VCO 35 +#define IMX952_CLK_HSIOPLL 36 +#define IMX952_CLK_LDBPLL_VCO 37 +#define IMX952_CLK_LDBPLL 38 +#define IMX952_CLK_EXT1 39 +#define IMX952_CLK_EXT2 40 + +/* Clock ROOT */ +#define IMX952_CLK_ADC 41 +#define IMX952_CLK_RESERVED1 42 +#define IMX952_CLK_BUSAON 43 +#define IMX952_CLK_CAN1 44 +#define IMX952_CLK_RESERVED4 45 +#define IMX952_CLK_I3C1SLOW 46 +#define IMX952_CLK_LPI2C1 47 +#define IMX952_CLK_LPI2C2 48 +#define IMX952_CLK_LPSPI1 49 +#define IMX952_CLK_LPSPI2 50 +#define IMX952_CLK_LPTMR1 51 +#define IMX952_CLK_LPUART1 52 +#define IMX952_CLK_LPUART2 53 +#define IMX952_CLK_M33 54 +#define IMX952_CLK_M33SYSTICK 55 +#define IMX952_CLK_RESERVED15 56 +#define IMX952_CLK_PDM 57 +#define IMX952_CLK_SAI1 58 +#define IMX952_CLK_RESERVED18 59 +#define IMX952_CLK_TPM2 60 +#define IMX952_CLK_RESERVED20 61 +#define IMX952_CLK_CAMAPB 62 +#define IMX952_CLK_CAMAXI 63 +#define IMX952_CLK_CAMCM0 64 +#define IMX952_CLK_CAMISI 65 +#define IMX952_CLK_CAMPHYCFG 66 +#define IMX952_CLK_MIPIPHYPLLBYPASS 67 +#define IMX952_CLK_RESERVED27 68 +#define IMX952_CLK_MIPITESTBYTE 69 +#define IMX952_CLK_A55 70 +#define IMX952_CLK_A55MTRBUS 71 +#define IMX952_CLK_A55PERIPH 72 +#define IMX952_CLK_DRAMALT 73 +#define IMX952_CLK_DRAMAPB 74 +#define IMX952_CLK_DISPAPB 75 +#define IMX952_CLK_DISPAXI 76 +#define IMX952_CLK_DISPLPSPI 77 +#define IMX952_CLK_DISPOCRAM 78 +#define IMX952_CLK_DISPPHYCFG 79 +#define IMX952_CLK_DISP1PIX 80 +#define IMX952_CLK_DISPCDPHYAPB 81 +#define IMX952_CLK_RESERVED41 82 +#define IMX952_CLK_GPUAPB 83 +#define IMX952_CLK_GPU 84 +#define IMX952_CLK_HSIOACSCAN480M 85 +#define IMX952_CLK_HSIOACSCAN80M 86 +#define IMX952_CLK_HSIO 87 +#define IMX952_CLK_HSIOPCIEAUX 88 +#define IMX952_CLK_HSIOPCIETEST160M 89 +#define IMX952_CLK_HSIOPCIETEST400M 90 +#define IMX952_CLK_HSIOPCIETEST500M 91 +#define IMX952_CLK_HSIOUSBTEST50M 92 +#define IMX952_CLK_HSIOUSBTEST60M 93 +#define IMX952_CLK_BUSM7 94 +#define IMX952_CLK_M7 95 +#define IMX952_CLK_M7SYSTICK 96 +#define IMX952_CLK_BUSNETCMIX 97 +#define IMX952_CLK_ENET 98 +#define IMX952_CLK_ENETPHYTEST200M 99 +#define IMX952_CLK_ENETPHYTEST500M 100 +#define IMX952_CLK_ENETPHYTEST667M 101 +#define IMX952_CLK_ENETREF 102 +#define IMX952_CLK_ENETTIMER1 103 +#define IMX952_CLK_RESERVED63 104 +#define IMX952_CLK_SAI2 105 +#define IMX952_CLK_NOCAPB 106 +#define IMX952_CLK_NOC 107 +#define IMX952_CLK_NPUAPB 108 +#define IMX952_CLK_NPU 109 +#define IMX952_CLK_CCMCKO1 110 +#define IMX952_CLK_CCMCKO2 111 +#define IMX952_CLK_CCMCKO3 112 +#define IMX952_CLK_CCMCKO4 113 +#define IMX952_CLK_VPUAPB 114 +#define IMX952_CLK_VPU 115 +#define IMX952_CLK_RESERVED75 116 +#define IMX952_CLK_RESERVED76 117 +#define IMX952_CLK_AUDIOXCVR 118 +#define IMX952_CLK_BUSWAKEUP 119 +#define IMX952_CLK_CAN2 120 +#define IMX952_CLK_CAN3 121 +#define IMX952_CLK_CAN4 122 +#define IMX952_CLK_CAN5 123 +#define IMX952_CLK_FLEXIO1 124 +#define IMX952_CLK_FLEXIO2 125 +#define IMX952_CLK_XSPI1 126 +#define IMX952_CLK_RESERVED86 127 +#define IMX952_CLK_I3C2SLOW 128 +#define IMX952_CLK_LPI2C3 129 +#define IMX952_CLK_LPI2C4 130 +#define IMX952_CLK_LPI2C5 131 +#define IMX952_CLK_LPI2C6 132 +#define IMX952_CLK_LPI2C7 133 +#define IMX952_CLK_LPI2C8 134 +#define IMX952_CLK_LPSPI3 135 +#define IMX952_CLK_LPSPI4 136 +#define IMX952_CLK_LPSPI5 137 +#define IMX952_CLK_LPSPI6 138 +#define IMX952_CLK_LPSPI7 139 +#define IMX952_CLK_LPSPI8 140 +#define IMX952_CLK_LPTMR2 141 +#define IMX952_CLK_LPUART3 142 +#define IMX952_CLK_LPUART4 143 +#define IMX952_CLK_LPUART5 144 +#define IMX952_CLK_LPUART6 145 +#define IMX952_CLK_LPUART7 146 +#define IMX952_CLK_LPUART8 147 +#define IMX952_CLK_SAI3 148 +#define IMX952_CLK_SAI4 149 +#define IMX952_CLK_SAI5 150 +#define IMX952_CLK_SPDIF 151 +#define IMX952_CLK_SWOTRACE 152 +#define IMX952_CLK_TPM4 153 +#define IMX952_CLK_TPM5 154 +#define IMX952_CLK_TPM6 155 +#define IMX952_CLK_MIPIPHYDFT400 156 +#define IMX952_CLK_MIPIPHYDFT540 157 +#define IMX952_CLK_USDHC1 158 +#define IMX952_CLK_USDHC2 159 +#define IMX952_CLK_USDHC3 160 +#define IMX952_CLK_V2XPK 161 +#define IMX952_CLK_WAKEUPAXI 162 +#define IMX952_CLK_XSPISLVROOT 163 +#define IMX952_CLK_AUDMIX1 164 +#define IMX952_CLK_ASRC1 165 +#define IMX952_CLK_ASRC2 166 +#define IMX952_CLK_GPT1 167 +#define IMX952_CLK_GPT2 168 +#define IMX952_CLK_GPT3 169 +#define IMX952_CLK_GPT4 170 + +/* Clock GPR SEL */ +#define IMX952_CLK_GPR_SEL_EXT 171 +#define IMX952_CLK_GPR_SEL_A55C0 172 +#define IMX952_CLK_GPR_SEL_A55C1 173 +#define IMX952_CLK_GPR_SEL_A55C2 174 +#define IMX952_CLK_GPR_SEL_A55C3 175 +#define IMX952_CLK_GPR_SEL_A55P 176 +#define IMX952_CLK_GPR_SEL_DRAM 177 +#define IMX952_CLK_GPR_SEL_TEMPSENSE 178 + +/* Clock CGC */ +#define IMX952_CLK_CGC_NPU 179 +#define IMX952_CLK_CGC_GPU 180 +#define IMX952_CLK_CGC_CAMISI 181 +#define IMX952_CLK_CGC_CAMISP 182 +#define IMX952_CLK_CGC_CAMCSI0 183 +#define IMX952_CLK_CGC_CAMCSI1 184 +#define IMX952_CLK_CGC_CAMOCRAM 185 +#define IMX952_CLK_CGC_HSIOUSB 186 +#define IMX952_CLK_CGC_HSIOPCIE 187 +#define IMX952_CLK_CGC_DISPOCRAM 188 +#define IMX952_CLK_CGC_DISPSEERIS 189 +#define IMX952_CLK_CGC_DISPDSI 190 +#define IMX952_CLK_CGC_NOCGIC 191 +#define IMX952_CLK_CGC_NOCOCRAM 192 +#define IMX952_CLK_CGC_NETC 193 +#define IMX952_CLK_CGC_VPUENC 194 +#define IMX952_CLK_CGC_VPUJPEGENC 195 +#define IMX952_CLK_CGC_VPUJPEGDEC 196 +#define IMX952_CLK_CGC_VPUDEC 197 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx952-pinfunc.h b/arch/arm64/boot/dts/freescale/imx952-pinfunc.h new file mode 100644 index 000000000000..debe6ede2d70 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-pinfunc.h @@ -0,0 +1,867 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __DTS_IMX952_PINFUNC_H__ +#define __DTS_IMX952_PINFUNC_H__ + +/* + * The pin function ID is a tuple of + * + */ +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_TDI 0x0000 0x0230 0x05FC 0x00 0x00 +#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0230 0x0000 0x01 0x00 +#define IMX952_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0230 0x0000 0x02 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_CAN2_TX 0x0000 0x0230 0x0000 0x03 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_30 0x0000 0x0230 0x0000 0x04 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_GPIO3_IO_28 0x0000 0x0230 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x0000 0x0230 0x059C 0x06 0x00 + +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_TMS 0x0004 0x0234 0x0600 0x00 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_31 0x0004 0x0234 0x0000 0x04 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_GPIO3_IO_29 0x0004 0x0234 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x0004 0x0234 0x0000 0x06 0x00 + +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_TCK 0x0008 0x0238 0x05F8 0x00 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0008 0x0238 0x04B4 0x04 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_GPIO3_IO_30 0x0008 0x0238 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0008 0x0238 0x0598 0x06 0x00 + +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_TDO 0x000C 0x023C 0x0000 0x00 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x023C 0x0000 0x01 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM2 0x000C 0x023C 0x0000 0x02 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_CAN2_RX 0x000C 0x023C 0x04A4 0x03 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x000C 0x023C 0x04B8 0x04 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_GPIO3_IO_31 0x000C 0x023C 0x0000 0x05 0x00 +#define IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x000C 0x023C 0x05A0 0x06 0x00 + +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPIO2_IO_0 0x0010 0x0240 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x0010 0x0240 0x0530 0x01 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_GPTMUX_INOUT0 0x0010 0x0240 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPSPI6_PCS0 0x0010 0x0240 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPUART5_TX 0x0010 0x0240 0x05A0 0x05 0x01 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C5_SDA 0x0010 0x0240 0x0540 0x06 0x00 +#define IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x0010 0x0240 0x04BC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPIO2_IO_1 0x0014 0x0244 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x0014 0x0244 0x052C 0x01 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_GPTMUX_INOUT1 0x0014 0x0244 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPSPI6_SIN 0x0014 0x0244 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPUART5_RX 0x0014 0x0244 0x059C 0x05 0x01 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C5_SCL 0x0014 0x0244 0x053C 0x06 0x00 +#define IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x0014 0x0244 0x04C0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPIO2_IO_2 0x0018 0x0248 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C4_SDA 0x0018 0x0248 0x0538 0x01 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_GPTMUX_INOUT2 0x0018 0x0248 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPSPI6_SOUT 0x0018 0x0248 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPUART5_CTS_B 0x0018 0x0248 0x0598 0x05 0x01 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x0018 0x0248 0x0548 0x06 0x00 +#define IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x0018 0x0248 0x04C4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPIO2_IO_3 0x001C 0x024C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C4_SCL 0x001C 0x024C 0x0534 0x01 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_GPTMUX_INOUT3 0x001C 0x024C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPSPI6_SCK 0x001C 0x024C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPUART5_RTS_B 0x001C 0x024C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x001C 0x024C 0x0544 0x06 0x00 +#define IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x001C 0x024C 0x04C8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x0020 0x0250 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_TPM3_CH0 0x0020 0x0250 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0250 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPTMUX_INOUT4 0x0020 0x0250 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPSPI7_PCS0 0x0020 0x0250 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPUART6_TX 0x0020 0x0250 0x05AC 0x05 0x00 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_LPI2C6_SDA 0x0020 0x0250 0x0548 0x06 0x01 +#define IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x0020 0x0250 0x04CC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPIO2_IO_5 0x0024 0x0254 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_TPM4_CH0 0x0024 0x0254 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_0 0x0024 0x0254 0x0464 0x02 0x01 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_GPTMUX_INOUT5 0x0024 0x0254 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x0024 0x0254 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPUART6_RX 0x0024 0x0254 0x05A8 0x05 0x00 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPI2C6_SCL 0x0024 0x0254 0x0544 0x06 0x01 +#define IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x0024 0x0254 0x04D0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPIO2_IO_6 0x0028 0x0258 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_TPM5_CH0 0x0028 0x0258 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_1 0x0028 0x0258 0x0468 0x02 0x01 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_GPTMUX_INOUT6 0x0028 0x0258 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x0028 0x0258 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0028 0x0258 0x05A4 0x05 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPI2C7_SDA 0x0028 0x0258 0x0550 0x06 0x00 +#define IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x0028 0x0258 0x04D4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPIO2_IO_7 0x002C 0x025C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI3_PCS1 0x002C 0x025C 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_GPTMUX_INOUT7 0x002C 0x025C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x002C 0x025C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPUART6_RTS_B 0x002C 0x025C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPI2C7_SCL 0x002C 0x025C 0x054C 0x06 0x00 +#define IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x002C 0x025C 0x04D8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPIO2_IO_8 0x0030 0x0260 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPSPI3_PCS0 0x0030 0x0260 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_GPTMUX_INOUT8 0x0030 0x0260 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_TPM6_CH0 0x0030 0x0260 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPUART7_TX 0x0030 0x0260 0x05B4 0x05 0x00 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x0030 0x0260 0x0550 0x06 0x01 +#define IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0030 0x0260 0x04DC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPIO2_IO_9 0x0034 0x0264 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPSPI3_SIN 0x0034 0x0264 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_GPTMUX_INOUT9 0x0034 0x0264 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_TPM3_EXTCLK 0x0034 0x0264 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPUART7_RX 0x0034 0x0264 0x05B0 0x05 0x00 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x0034 0x0264 0x054C 0x06 0x01 +#define IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0034 0x0264 0x04E0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x0038 0x0268 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPSPI3_SOUT 0x0038 0x0268 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPTMUX_INOUT10 0x0038 0x0268 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_TPM4_EXTCLK 0x0038 0x0268 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPUART7_CTS_B 0x0038 0x0268 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_LPI2C8_SDA 0x0038 0x0268 0x0558 0x06 0x00 +#define IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x0038 0x0268 0x04E4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x003C 0x026C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPSPI3_SCK 0x003C 0x026C 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPTMUX_INOUT11 0x003C 0x026C 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_TPM5_EXTCLK 0x003C 0x026C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPUART7_RTS_B 0x003C 0x026C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_LPI2C8_SCL 0x003C 0x026C 0x0554 0x06 0x00 +#define IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x003C 0x026C 0x04E8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_GPIO2_IO_12 0x0040 0x0270 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x0040 0x0270 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_2 0x0040 0x0270 0x046C 0x02 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0040 0x0270 0x04EC 0x03 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPSPI8_PCS0 0x0040 0x0270 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPUART8_TX 0x0040 0x0270 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_LPI2C8_SDA 0x0040 0x0270 0x0558 0x06 0x01 +#define IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x0040 0x0270 0x05BC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_GPIO2_IO_13 0x0044 0x0274 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_TPM4_CH2 0x0044 0x0274 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_3 0x0044 0x0274 0x0470 0x02 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPSPI8_SIN 0x0044 0x0274 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPUART8_RX 0x0044 0x0274 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_LPI2C8_SCL 0x0044 0x0274 0x0554 0x06 0x01 +#define IMX952_PAD_GPIO_IO13__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0044 0x0274 0x04F0 0x07 0x00 + +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_GPIO2_IO_14 0x0048 0x0278 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART3_TX 0x0048 0x0278 0x0588 0x01 0x01 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPSPI8_SOUT 0x0048 0x0278 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART8_CTS_B 0x0048 0x0278 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_LPUART4_TX 0x0048 0x0278 0x0594 0x06 0x01 +#define IMX952_PAD_GPIO_IO14__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x0048 0x0278 0x04F4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_GPIO2_IO_15 0x004C 0x027C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART3_RX 0x004C 0x027C 0x0584 0x01 0x01 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x004C 0x027C 0x0624 0x03 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPSPI8_SCK 0x004C 0x027C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART8_RTS_B 0x004C 0x027C 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_LPUART4_RX 0x004C 0x027C 0x0590 0x06 0x01 +#define IMX952_PAD_GPIO_IO15__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x004C 0x027C 0x04F8 0x07 0x00 + +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x0050 0x0280 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x0050 0x0280 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_2 0x0050 0x0280 0x046C 0x02 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0050 0x0280 0x0580 0x04 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0050 0x0280 0x0564 0x05 0x00 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_LPUART4_CTS_B 0x0050 0x0280 0x058C 0x06 0x01 +#define IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0050 0x0280 0x04FC 0x07 0x00 + +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x0054 0x0284 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x0054 0x0284 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART3_RTS_B 0x0054 0x0284 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0054 0x0284 0x0560 0x05 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_LPUART4_RTS_B 0x0054 0x0284 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0054 0x0284 0x0500 0x07 0x00 + +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x0058 0x0288 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0058 0x0288 0x05B8 0x01 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI5_PCS0 0x0058 0x0288 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0058 0x0288 0x055C 0x05 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_TPM5_CH2 0x0058 0x0288 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x0058 0x0288 0x0504 0x07 0x00 + +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_GPIO2_IO_19 0x005C 0x028C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_SAI3_RX_SYNC 0x005C 0x028C 0x05BC 0x01 0x01 +#define IMX952_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_3 0x005C 0x028C 0x0470 0x02 0x01 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x005C 0x028C 0x0508 0x03 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI5_SIN 0x005C 0x028C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_LPSPI4_SIN 0x005C 0x028C 0x056C 0x05 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x005C 0x028C 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x005C 0x028C 0x05F4 0x07 0x00 + +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x0060 0x0290 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x0060 0x0290 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_0 0x0060 0x0290 0x0464 0x02 0x02 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI5_SOUT 0x0060 0x0290 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_LPSPI4_SOUT 0x0060 0x0290 0x0570 0x05 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_TPM3_CH1 0x0060 0x0290 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0060 0x0290 0x050C 0x07 0x00 + +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x0064 0x0294 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x0064 0x0294 0x05F4 0x01 0x01 +#define IMX952_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0294 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0064 0x0294 0x0510 0x03 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI5_SCK 0x0064 0x0294 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_LPSPI4_SCK 0x0064 0x0294 0x0568 0x05 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_TPM4_CH1 0x0064 0x0294 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_SAI3_RX_BCLK 0x0064 0x0294 0x05B8 0x07 0x01 + +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_GPIO2_IO_22 0x0068 0x0298 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_USDHC3_CLK 0x0068 0x0298 0x0604 0x01 0x00 +#define IMX952_PAD_GPIO_IO22__HSIOMIX_TOP_USB1_OTG_OC 0x0068 0x0298 0x047C 0x03 0x01 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM5_CH1 0x0068 0x0298 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_TPM6_EXTCLK 0x0068 0x0298 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_LPI2C5_SDA 0x0068 0x0298 0x0540 0x06 0x01 +#define IMX952_PAD_GPIO_IO22__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x0068 0x0298 0x0514 0x07 0x00 + +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_GPIO2_IO_23 0x006C 0x029C 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_USDHC3_CMD 0x006C 0x029C 0x0608 0x01 0x00 +#define IMX952_PAD_GPIO_IO23__HSIOMIX_TOP_USB2_OTG_OC 0x006C 0x029C 0x0480 0x03 0x01 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_TPM6_CH1 0x006C 0x029C 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_LPI2C5_SCL 0x006C 0x029C 0x053C 0x06 0x01 +#define IMX952_PAD_GPIO_IO23__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x006C 0x029C 0x0518 0x07 0x00 + +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_GPIO2_IO_24 0x0070 0x02A0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_USDHC3_DATA0 0x0070 0x02A0 0x060C 0x01 0x00 +#define IMX952_PAD_GPIO_IO24__HSIOMIX_TOP_USB1_OTG_PWR 0x0070 0x02A0 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TPM3_CH3 0x0070 0x02A0 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_TDO 0x0070 0x02A0 0x0000 0x05 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_LPSPI6_PCS1 0x0070 0x02A0 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO24__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0070 0x02A0 0x051C 0x07 0x00 + +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_GPIO2_IO_25 0x0074 0x02A4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_USDHC3_DATA1 0x0074 0x02A4 0x0610 0x01 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x0074 0x02A4 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO25__HSIOMIX_TOP_USB2_OTG_PWR 0x0074 0x02A4 0x0000 0x03 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TPM4_CH3 0x0074 0x02A4 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_TCK 0x0074 0x02A4 0x05F8 0x05 0x01 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_LPSPI7_PCS1 0x0074 0x02A4 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0074 0x02A4 0x0520 0x07 0x00 + +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x0078 0x02A8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_USDHC3_DATA2 0x0078 0x02A8 0x0614 0x01 0x00 +#define IMX952_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_1 0x0078 0x02A8 0x0468 0x02 0x02 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x0078 0x02A8 0x04AC 0x03 0x01 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TPM5_CH3 0x0078 0x02A8 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_TDI 0x0078 0x02A8 0x05FC 0x05 0x01 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_LPSPI8_PCS1 0x0078 0x02A8 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x0078 0x02A8 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_GPIO2_IO_27 0x007C 0x02AC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_USDHC3_DATA3 0x007C 0x02AC 0x0618 0x01 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x007C 0x02AC 0x04A4 0x02 0x02 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TPM6_CH3 0x007C 0x02AC 0x0000 0x04 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_TMS 0x007C 0x02AC 0x0600 0x05 0x01 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_LPSPI5_PCS1 0x007C 0x02AC 0x0000 0x06 0x00 +#define IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x007C 0x02AC 0x04B0 0x07 0x01 + +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_GPIO2_IO_28 0x0080 0x02B0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_LPI2C3_SDA 0x0080 0x02B0 0x0530 0x01 0x01 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_CAN3_TX 0x0080 0x02B0 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO28__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_28 0x0080 0x02B0 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_GPIO2_IO_29 0x0084 0x02B4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_LPI2C3_SCL 0x0084 0x02B4 0x052C 0x01 0x01 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_CAN3_RX 0x0084 0x02B4 0x04A8 0x02 0x01 +#define IMX952_PAD_GPIO_IO29__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_29 0x0084 0x02B4 0x0000 0x07 0x00 + +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_GPIO2_IO_30 0x0088 0x02B8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x0088 0x02B8 0x0538 0x01 0x01 +#define IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_30 0x0088 0x02B8 0x04B4 0x07 0x01 + +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_GPIO2_IO_31 0x008C 0x02BC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x008C 0x02BC 0x0534 0x01 0x01 +#define IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_31 0x008C 0x02BC 0x04B8 0x07 0x01 + +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_GPIO5_IO_12 0x0090 0x02C0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x02C0 0x0000 0x01 0x00 +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPUART6_TX 0x0090 0x02C0 0x05AC 0x02 0x01 +#define IMX952_PAD_GPIO_IO32__WAKEUPMIX_TOP_LPSPI4_PCS2 0x0090 0x02C0 0x0564 0x04 0x01 + +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_GPIO5_IO_13 0x0094 0x02C4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPUART6_RX 0x0094 0x02C4 0x05A8 0x02 0x01 +#define IMX952_PAD_GPIO_IO33__WAKEUPMIX_TOP_LPSPI4_PCS1 0x0094 0x02C4 0x0560 0x04 0x01 + +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x0098 0x02C8 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPUART6_CTS_B 0x0098 0x02C8 0x05A4 0x02 0x01 +#define IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_LPSPI4_PCS0 0x0098 0x02C8 0x055C 0x04 0x01 + +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_GPIO5_IO_15 0x009C 0x02CC 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPUART6_RTS_B 0x009C 0x02CC 0x0000 0x02 0x00 +#define IMX952_PAD_GPIO_IO35__WAKEUPMIX_TOP_LPSPI4_SIN 0x009C 0x02CC 0x056C 0x04 0x01 + +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPSPI4_SOUT 0x00A0 0x02D0 0x0570 0x04 0x01 +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x00A0 0x02D0 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_LPUART7_TX 0x00A0 0x02D0 0x05B4 0x02 0x01 + +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_GPIO5_IO_17 0x00A4 0x02D4 0x0000 0x00 0x00 +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPUART7_RX 0x00A4 0x02D4 0x05B0 0x02 0x01 +#define IMX952_PAD_GPIO_IO37__WAKEUPMIX_TOP_LPSPI4_SCK 0x00A4 0x02D4 0x0568 0x04 0x01 + +#define IMX952_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00D4 0x0304 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00D4 0x0304 0x0494 0x01 0x00 +#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_26 0x00D4 0x0304 0x04AC 0x04 0x00 +#define IMX952_PAD_CCM_CLKO1__WAKEUPMIX_TOP_GPIO3_IO_26 0x00D4 0x0304 0x0000 0x05 0x00 + +#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_GPIO3_IO_27 0x00D8 0x0308 0x0000 0x05 0x00 +#define IMX952_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00D8 0x0308 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00D8 0x0308 0x0000 0x01 0x00 +#define IMX952_PAD_CCM_CLKO2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_27 0x00D8 0x0308 0x04B0 0x04 0x00 + +#define IMX952_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00DC 0x030C 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00DC 0x030C 0x0498 0x01 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_CAN3_TX 0x00DC 0x030C 0x0000 0x02 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_28 0x00DC 0x030C 0x0000 0x04 0x00 +#define IMX952_PAD_CCM_CLKO3__WAKEUPMIX_TOP_GPIO4_IO_28 0x00DC 0x030C 0x0000 0x05 0x00 + +#define IMX952_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00E0 0x0310 0x0000 0x00 0x00 +#define IMX952_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00E0 0x0310 0x0000 0x01 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_CAN3_RX 0x00E0 0x0310 0x04A8 0x02 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_29 0x00E0 0x0310 0x0000 0x04 0x00 +#define IMX952_PAD_CCM_CLKO4__WAKEUPMIX_TOP_GPIO4_IO_29 0x00E0 0x0310 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00E4 0x0314 0x0484 0x00 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_LPUART3_DCD_B 0x00E4 0x0314 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_I3C2_SCL 0x00E4 0x0314 0x0524 0x02 0x00 +#define IMX952_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00E4 0x0314 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_0 0x00E4 0x0314 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_MDC__WAKEUPMIX_TOP_GPIO4_IO_0 0x00E4 0x0314 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00E8 0x0318 0x0488 0x00 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_LPUART3_RIN_B 0x00E8 0x0318 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_I3C2_SDA 0x00E8 0x0318 0x0528 0x02 0x00 +#define IMX952_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00E8 0x0318 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_1 0x00E8 0x0318 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_MDIO__WAKEUPMIX_TOP_GPIO4_IO_1 0x00E8 0x0318 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00EC 0x031C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_CAN2_TX 0x00EC 0x031C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00EC 0x031C 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_2 0x00EC 0x031C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD3__WAKEUPMIX_TOP_GPIO4_IO_2 0x00EC 0x031C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00F0 0x0320 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00F0 0x0320 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_CAN2_RX 0x00F0 0x0320 0x04A4 0x02 0x01 +#define IMX952_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00F0 0x0320 0x0480 0x03 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_3 0x00F0 0x0320 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD2__WAKEUPMIX_TOP_GPIO4_IO_3 0x00F0 0x0320 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00F4 0x0324 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_LPUART3_RTS_B 0x00F4 0x0324 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR 0x00F4 0x0324 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00F4 0x0324 0x047C 0x03 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_4 0x00F4 0x0324 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_GPIO4_IO_4 0x00F4 0x0324 0x0000 0x05 0x00 +#define IMX952_PAD_ENET1_TD1__WAKEUPMIX_TOP_I3C2_PUR_B 0x00F4 0x0324 0x0000 0x06 0x00 +#define IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00F4 0x0324 0x0000 0x07 0x00 + +#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00F8 0x0328 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_LPUART3_TX 0x00F8 0x0328 0x0588 0x01 0x00 +#define IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00F8 0x0328 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_5 0x00F8 0x0328 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TD0__WAKEUPMIX_TOP_GPIO4_IO_5 0x00F8 0x0328 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00FC 0x032C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_LPUART3_DTR_B 0x00FC 0x032C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00FC 0x032C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_6 0x00FC 0x032C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_6 0x00FC 0x032C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x0100 0x0330 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RMII_REF50_CLK_OUT 0x0100 0x0330 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_7 0x0100 0x0330 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_TXC__WAKEUPMIX_TOP_GPIO4_IO_7 0x0100 0x0330 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x0104 0x0334 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_LPUART3_DSR_B 0x0104 0x0334 0x0000 0x01 0x00 +#define IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x0104 0x0334 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x0104 0x0334 0x0000 0x03 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_8 0x0104 0x0334 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_8 0x0104 0x0334 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x0108 0x0338 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0108 0x0338 0x048C 0x01 0x00 +#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_9 0x0108 0x0338 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RXC__WAKEUPMIX_TOP_GPIO4_IO_9 0x0108 0x0338 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x010C 0x033C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_LPUART3_RX 0x010C 0x033C 0x0584 0x01 0x00 +#define IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x010C 0x033C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_10 0x010C 0x033C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD0__WAKEUPMIX_TOP_GPIO4_IO_10 0x010C 0x033C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x0110 0x0340 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPUART3_CTS_B 0x0110 0x0340 0x0580 0x01 0x00 +#define IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x0110 0x0340 0x0000 0x02 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_LPTMR2_ALT0 0x0110 0x0340 0x0574 0x03 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_11 0x0110 0x0340 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD1__WAKEUPMIX_TOP_GPIO4_IO_11 0x0110 0x0340 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x0114 0x0344 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x0114 0x0344 0x048C 0x02 0x01 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_LPTMR2_ALT1 0x0114 0x0344 0x0578 0x03 0x00 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_12 0x0114 0x0344 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD2__WAKEUPMIX_TOP_GPIO4_IO_12 0x0114 0x0344 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x0118 0x0348 0x0000 0x00 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0118 0x0348 0x057C 0x03 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_13 0x0118 0x0348 0x0000 0x04 0x00 +#define IMX952_PAD_ENET1_RD3__WAKEUPMIX_TOP_GPIO4_IO_13 0x0118 0x0348 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x011C 0x034C 0x0484 0x00 0x01 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_LPUART4_DCD_B 0x011C 0x034C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x011C 0x034C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_14 0x011C 0x034C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_MDC__WAKEUPMIX_TOP_GPIO4_IO_14 0x011C 0x034C 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x0120 0x0350 0x0488 0x00 0x01 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_LPUART4_RIN_B 0x0120 0x0350 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x0120 0x0350 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_15 0x0120 0x0350 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_MDIO__WAKEUPMIX_TOP_GPIO4_IO_15 0x0120 0x0350 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_0 0x0124 0x0354 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_16 0x0124 0x0354 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD3__WAKEUPMIX_TOP_GPIO4_IO_16 0x0124 0x0354 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x0124 0x0354 0x0000 0x00 0x00 + +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x0128 0x0358 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x0128 0x0358 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_1 0x0128 0x0358 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x0128 0x0358 0x05D0 0x03 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_17 0x0128 0x0358 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD2__WAKEUPMIX_TOP_GPIO4_IO_17 0x0128 0x0358 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x012C 0x035C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_LPUART4_RTS_B 0x012C 0x035C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_2 0x012C 0x035C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x012C 0x035C 0x05CC 0x03 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_18 0x012C 0x035C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD1__WAKEUPMIX_TOP_GPIO4_IO_18 0x012C 0x035C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x012C 0x035C 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0130 0x0360 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_LPUART4_TX 0x0130 0x0360 0x0594 0x01 0x00 +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_3 0x0130 0x0360 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x0130 0x0360 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_19 0x0130 0x0360 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TD0__WAKEUPMIX_TOP_GPIO4_IO_19 0x0130 0x0360 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0130 0x0360 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0134 0x0364 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_LPUART4_DTR_B 0x0134 0x0364 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0134 0x0364 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0134 0x0364 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_20 0x0134 0x0364 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TX_CTL__WAKEUPMIX_TOP_GPIO4_IO_20 0x0134 0x0364 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x0138 0x0368 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RMII_REF50_CLK_OUT 0x0138 0x0368 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x0138 0x0368 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_21 0x0138 0x0368 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_TXC__WAKEUPMIX_TOP_GPIO4_IO_21 0x0138 0x0368 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x013C 0x036C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_LPUART4_DSR_B 0x013C 0x036C 0x0000 0x01 0x00 +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_0 0x013C 0x036C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_22 0x013C 0x036C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RX_CTL__WAKEUPMIX_TOP_GPIO4_IO_22 0x013C 0x036C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x013C 0x036C 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0140 0x0370 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0140 0x0370 0x0490 0x01 0x00 +#define IMX952_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_1 0x0140 0x0370 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x0140 0x0370 0x05C8 0x03 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_23 0x0140 0x0370 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RXC__WAKEUPMIX_TOP_GPIO4_IO_23 0x0140 0x0370 0x0000 0x05 0x00 + +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0144 0x0374 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_LPUART4_RX 0x0144 0x0374 0x0590 0x01 0x00 +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_2 0x0144 0x0374 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x0144 0x0374 0x05C0 0x03 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_24 0x0144 0x0374 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD0__WAKEUPMIX_TOP_GPIO4_IO_24 0x0144 0x0374 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0144 0x0374 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x0148 0x0378 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_3 0x0148 0x0378 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x0148 0x0378 0x05C4 0x03 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_25 0x0148 0x0378 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD1__WAKEUPMIX_TOP_GPIO4_IO_25 0x0148 0x0378 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x0148 0x0378 0x0000 0x06 0x00 + +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x014C 0x037C 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_LPUART4_CTS_B 0x014C 0x037C 0x058C 0x01 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x014C 0x037C 0x0000 0x02 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x014C 0x037C 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_26 0x014C 0x037C 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD2__WAKEUPMIX_TOP_GPIO4_IO_26 0x014C 0x037C 0x0000 0x05 0x00 +#define IMX952_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x014C 0x037C 0x0490 0x06 0x01 + +#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0150 0x0380 0x0000 0x00 0x00 +#define IMX952_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0150 0x0380 0x0000 0x03 0x00 +#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_FLEXIO2_FLEXIO_27 0x0150 0x0380 0x0000 0x04 0x00 +#define IMX952_PAD_ENET2_RD3__WAKEUPMIX_TOP_GPIO4_IO_27 0x0150 0x0380 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_8 0x0154 0x0384 0x04DC 0x04 0x01 +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_GPIO3_IO_8 0x0154 0x0384 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x0154 0x0384 0x0000 0x00 0x00 + +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x0158 0x0388 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_9 0x0158 0x0388 0x04E0 0x04 0x01 +#define IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_GPIO3_IO_9 0x0158 0x0388 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x015C 0x038C 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_10 0x015C 0x038C 0x04E4 0x04 0x01 +#define IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_GPIO3_IO_10 0x015C 0x038C 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x0160 0x0390 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_11 0x0160 0x0390 0x04E8 0x04 0x01 +#define IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_GPIO3_IO_11 0x0160 0x0390 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x0164 0x0394 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_XSPI1_INTFA_B 0x0164 0x0394 0x0624 0x01 0x01 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_12 0x0164 0x0394 0x04EC 0x04 0x01 +#define IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_GPIO3_IO_12 0x0164 0x0394 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0164 0x0394 0x0000 0x06 0x00 + +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x0168 0x0398 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x0168 0x0398 0x064C 0x01 0x00 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_13 0x0168 0x0398 0x04F0 0x04 0x01 +#define IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_GPIO3_IO_13 0x0168 0x0398 0x0000 0x05 0x00 + +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x016C 0x039C 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x016C 0x039C 0x0638 0x01 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_14 0x016C 0x039C 0x04F4 0x04 0x01 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_GPIO3_IO_14 0x016C 0x039C 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x016C 0x039C 0x066C 0x06 0x00 + +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x0170 0x03A0 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x0170 0x03A0 0x063C 0x01 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_RESET_B 0x0170 0x03A0 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_15 0x0170 0x03A0 0x04F8 0x04 0x01 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_GPIO3_IO_15 0x0170 0x03A0 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x0170 0x03A0 0x0670 0x06 0x00 + +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x0174 0x03A4 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x0174 0x03A4 0x0640 0x01 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_CD_B 0x0174 0x03A4 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_16 0x0174 0x03A4 0x04FC 0x04 0x01 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_GPIO3_IO_16 0x0174 0x03A4 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x0174 0x03A4 0x0674 0x06 0x00 + +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x0178 0x03A8 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x0178 0x03A8 0x0644 0x01 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_WP 0x0178 0x03A8 0x0000 0x02 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_17 0x0178 0x03A8 0x0500 0x04 0x01 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_GPIO3_IO_17 0x0178 0x03A8 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x0178 0x03A8 0x0678 0x06 0x00 + +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x017C 0x03AC 0x0000 0x00 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI1_A_DQS 0x017C 0x03AC 0x0620 0x01 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_18 0x017C 0x03AC 0x0504 0x04 0x01 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_GPIO3_IO_18 0x017C 0x03AC 0x0000 0x05 0x00 +#define IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x017C 0x03AC 0x0654 0x06 0x00 + +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x0180 0x03B0 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_WP 0x0180 0x03B0 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_LPTMR2_ALT2 0x0180 0x03B0 0x057C 0x02 0x01 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_19 0x0180 0x03B0 0x0508 0x04 0x01 +#define IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_GPIO3_IO_19 0x0180 0x03B0 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0180 0x03B0 0x0478 0x06 0x01 + +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_USDHC3_CLK 0x0184 0x03B4 0x0604 0x00 0x01 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x0184 0x03B4 0x061C 0x01 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x0184 0x03B4 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x0184 0x03B4 0x05D8 0x03 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_20 0x0184 0x03B4 0x050C 0x04 0x01 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_GPIO3_IO_20 0x0184 0x03B4 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_CLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x0184 0x03B4 0x0658 0x06 0x00 + +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_USDHC3_CMD 0x0188 0x03B8 0x0608 0x00 0x01 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x0188 0x03B8 0x0648 0x01 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x0188 0x03B8 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x0188 0x03B8 0x05E8 0x03 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_21 0x0188 0x03B8 0x0510 0x04 0x01 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_GPIO3_IO_21 0x0188 0x03B8 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_CMD__WAKEUPMIX_TOP_XSPI_SLV_CS 0x0188 0x03B8 0x0650 0x06 0x00 + +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_USDHC3_DATA0 0x018C 0x03BC 0x060C 0x00 0x01 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x018C 0x03BC 0x0628 0x01 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x018C 0x03BC 0x0000 0x02 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x018C 0x03BC 0x05D4 0x03 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_22 0x018C 0x03BC 0x0514 0x04 0x01 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_GPIO3_IO_22 0x018C 0x03BC 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x018C 0x03BC 0x065C 0x06 0x00 + +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_USDHC3_DATA1 0x0190 0x03C0 0x0610 0x00 0x01 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x0190 0x03C0 0x062C 0x01 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x0190 0x03C0 0x05DC 0x02 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x0190 0x03C0 0x0000 0x03 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_23 0x0190 0x03C0 0x0518 0x04 0x01 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_GPIO3_IO_23 0x0190 0x03C0 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x0190 0x03C0 0x0660 0x06 0x00 + +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_USDHC3_DATA2 0x0194 0x03C4 0x0614 0x00 0x01 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x0194 0x03C4 0x0630 0x01 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x0194 0x03C4 0x05E0 0x02 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x0194 0x03C4 0x05F0 0x03 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_24 0x0194 0x03C4 0x051C 0x04 0x01 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_GPIO3_IO_24 0x0194 0x03C4 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x0194 0x03C4 0x0664 0x06 0x00 + +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_USDHC3_DATA3 0x0198 0x03C8 0x0618 0x00 0x01 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x0198 0x03C8 0x0634 0x01 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x0198 0x03C8 0x05E4 0x02 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x0198 0x03C8 0x05EC 0x03 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_25 0x0198 0x03C8 0x0520 0x04 0x01 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_GPIO3_IO_25 0x0198 0x03C8 0x0000 0x05 0x00 +#define IMX952_PAD_SD3_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x0198 0x03C8 0x0668 0x06 0x00 + +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x019C 0x03CC 0x0628 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_4 0x019C 0x03CC 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_TX_BCLK 0x019C 0x03CC 0x05CC 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_SAI4_RX_DATA_1 0x019C 0x03CC 0x0000 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI_SLV_DATA_0 0x019C 0x03CC 0x065C 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_GPIO5_IO_0 0x019C 0x03CC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x01A0 0x03D0 0x062C 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_5 0x01A0 0x03D0 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_SYNC 0x01A0 0x03D0 0x05D0 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_SAI4_TX_DATA_1 0x01A0 0x03D0 0x0000 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI_SLV_DATA_1 0x01A0 0x03D0 0x0660 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_GPIO5_IO_1 0x01A0 0x03D0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x01A4 0x03D4 0x0630 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_6 0x01A4 0x03D4 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_SAI4_TX_DATA_0 0x01A4 0x03D4 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI_SLV_DATA_2 0x01A4 0x03D4 0x0664 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_GPIO5_IO_2 0x01A4 0x03D4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x01A8 0x03D8 0x0634 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_7 0x01A8 0x03D8 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_SAI4_RX_DATA_0 0x01A8 0x03D8 0x05C4 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI_SLV_DATA_3 0x01A8 0x03D8 0x0668 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_GPIO5_IO_3 0x01A8 0x03D8 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x01AC 0x03DC 0x0638 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_TX_DATA_0 0x01AC 0x03DC 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_SAI5_RX_DATA_1 0x01AC 0x03DC 0x05DC 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI_SLV_DATA_4 0x01AC 0x03DC 0x066C 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_GPIO5_IO_4 0x01AC 0x03DC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x01B0 0x03E0 0x063C 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_TX_SYNC 0x01B0 0x03E0 0x05F0 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_SAI5_RX_DATA_2 0x01B0 0x03E0 0x05E0 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_6 0x01B0 0x03E0 0x049C 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI_SLV_DATA_5 0x01B0 0x03E0 0x0670 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_GPIO5_IO_5 0x01B0 0x03E0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x01B4 0x03E4 0x0640 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_TX_BCLK 0x01B4 0x03E4 0x05EC 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_SAI5_RX_DATA_3 0x01B4 0x03E4 0x05E4 0x02 0x01 +#define IMX952_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_7 0x01B4 0x03E4 0x04A0 0x03 0x00 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI_SLV_DATA_6 0x01B4 0x03E4 0x0674 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_GPIO5_IO_6 0x01B4 0x03E4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x01B8 0x03E8 0x0644 0x00 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_RX_DATA_0 0x01B8 0x03E8 0x05D8 0x01 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_SAI5_TX_DATA_1 0x01B8 0x03E8 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI_SLV_DATA_7 0x01B8 0x03E8 0x0678 0x04 0x01 +#define IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_GPIO5_IO_7 0x01B8 0x03E8 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x01BC 0x03EC 0x0620 0x00 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_RX_SYNC 0x01BC 0x03EC 0x05E8 0x01 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_SAI5_TX_DATA_2 0x01BC 0x03EC 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_6 0x01BC 0x03EC 0x049C 0x03 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI_SLV_DQS 0x01BC 0x03EC 0x0654 0x04 0x01 +#define IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_GPIO5_IO_8 0x01BC 0x03EC 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x01C0 0x03F0 0x061C 0x00 0x01 +#define IMX952_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_4 0x01C0 0x03F0 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_SAI4_RX_SYNC 0x01C0 0x03F0 0x05C8 0x02 0x01 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI_SLV_CLK 0x01C0 0x03F0 0x0658 0x04 0x01 +#define IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_GPIO5_IO_9 0x01C0 0x03F0 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x01C4 0x03F4 0x0648 0x00 0x01 +#define IMX952_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_5 0x01C4 0x03F4 0x0000 0x01 0x00 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_SAI4_RX_BCLK 0x01C4 0x03F4 0x05C0 0x02 0x01 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI_SLV_CS 0x01C4 0x03F4 0x0650 0x04 0x01 +#define IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_GPIO5_IO_10 0x01C4 0x03F4 0x0000 0x05 0x00 + +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_XSPI1_A_SS1_B 0x01C8 0x03F8 0x064C 0x00 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_RX_BCLK 0x01C8 0x03F8 0x05D4 0x01 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_SAI5_TX_DATA_3 0x01C8 0x03F8 0x0000 0x02 0x00 +#define IMX952_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_7 0x01C8 0x03F8 0x04A0 0x03 0x01 +#define IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x01C8 0x03F8 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_USDHC2_CD_B 0x01CC 0x03FC 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01CC 0x03FC 0x0494 0x01 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_I3C2_SCL 0x01CC 0x03FC 0x0524 0x02 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_0 0x01CC 0x03FC 0x04BC 0x04 0x01 +#define IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x01CC 0x03FC 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x01D0 0x0400 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01D0 0x0400 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_I3C2_SDA 0x01D0 0x0400 0x0528 0x02 0x01 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_1 0x01D0 0x0400 0x04C0 0x04 0x01 +#define IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_GPIO3_IO_1 0x01D0 0x0400 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01D0 0x0400 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x01D4 0x0404 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01D4 0x0404 0x0498 0x01 0x01 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR 0x01D4 0x0404 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_I3C2_PUR_B 0x01D4 0x0404 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_2 0x01D4 0x0404 0x04C4 0x04 0x01 +#define IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_GPIO3_IO_2 0x01D4 0x0404 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01D4 0x0404 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x01D8 0x0408 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01D8 0x0408 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_CAN2_TX 0x01D8 0x0408 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_3 0x01D8 0x0408 0x04C8 0x04 0x01 +#define IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_GPIO3_IO_3 0x01D8 0x0408 0x0000 0x05 0x00 +#define IMX952_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01D8 0x0408 0x0000 0x06 0x00 + +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x01DC 0x040C 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01DC 0x040C 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_CAN2_RX 0x01DC 0x040C 0x04A4 0x02 0x03 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_4 0x01DC 0x040C 0x04CC 0x04 0x01 +#define IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_GPIO3_IO_4 0x01DC 0x040C 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x01E0 0x0410 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01E0 0x0410 0x0000 0x01 0x00 +#define IMX952_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01E0 0x0410 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_5 0x01E0 0x0410 0x04D0 0x04 0x01 +#define IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_GPIO3_IO_5 0x01E0 0x0410 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x01E4 0x0414 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_LPTMR2_ALT0 0x01E4 0x0414 0x0574 0x01 0x01 +#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01E4 0x0414 0x0000 0x02 0x00 +#define IMX952_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01E4 0x0414 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_6 0x01E4 0x0414 0x04D4 0x04 0x01 +#define IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_GPIO3_IO_6 0x01E4 0x0414 0x0000 0x05 0x00 + +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_USDHC2_RESET_B 0x01E8 0x0418 0x0000 0x00 0x00 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_LPTMR2_ALT1 0x01E8 0x0418 0x0578 0x01 0x01 +#define IMX952_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01E8 0x0418 0x0000 0x03 0x00 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_FLEXIO1_FLEXIO_7 0x01E8 0x0418 0x04D8 0x04 0x01 +#define IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x01E8 0x0418 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01EC 0x041C 0x0000 0x00 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01EC 0x041C 0x0000 0x01 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01EC 0x041C 0x0000 0x02 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01EC 0x041C 0x0000 0x03 0x00 +#define IMX952_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01EC 0x041C 0x0000 0x04 0x00 +#define IMX952_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_0 0x01EC 0x041C 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01F0 0x0420 0x0000 0x00 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01F0 0x0420 0x0000 0x01 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01F0 0x0420 0x0000 0x02 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01F0 0x0420 0x0000 0x03 0x00 +#define IMX952_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01F0 0x0420 0x0000 0x04 0x00 +#define IMX952_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_1 0x01F0 0x0420 0x0000 0x05 0x00 + +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01F4 0x0424 0x0000 0x00 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01F4 0x0424 0x0000 0x01 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01F4 0x0424 0x0000 0x02 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01F4 0x0424 0x0000 0x03 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01F4 0x0424 0x0000 0x04 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_2 0x01F4 0x0424 0x0000 0x05 0x00 +#define IMX952_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01F4 0x0424 0x0000 0x06 0x00 + +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01F8 0x0428 0x0000 0x00 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01F8 0x0428 0x0000 0x02 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01F8 0x0428 0x0000 0x03 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01F8 0x0428 0x0000 0x04 0x00 +#define IMX952_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_3 0x01F8 0x0428 0x0000 0x05 0x00 + +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01FC 0x042C 0x0000 0x00 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_UART_CSSI_RX 0x01FC 0x042C 0x0000 0x01 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01FC 0x042C 0x0000 0x02 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01FC 0x042C 0x0000 0x03 0x00 +#define IMX952_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_4 0x01FC 0x042C 0x0000 0x05 0x00 + +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x0200 0x0430 0x0000 0x00 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_UART_CSSI_TX 0x0200 0x0430 0x0000 0x01 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x0200 0x0430 0x0000 0x02 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x0200 0x0430 0x0000 0x03 0x00 +#define IMX952_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_5 0x0200 0x0430 0x0000 0x05 0x00 + +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x0204 0x0434 0x0000 0x00 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x0204 0x0434 0x0000 0x01 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x0204 0x0434 0x0000 0x02 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x0204 0x0434 0x0000 0x03 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x0204 0x0434 0x0474 0x04 0x00 +#define IMX952_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_6 0x0204 0x0434 0x0000 0x05 0x00 + +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x0208 0x0438 0x0000 0x00 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x0208 0x0438 0x0000 0x01 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x0208 0x0438 0x0000 0x02 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x0208 0x0438 0x0000 0x03 0x00 +#define IMX952_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_7 0x0208 0x0438 0x0000 0x05 0x00 + +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x020C 0x043C 0x0000 0x00 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x020C 0x043C 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT0 0x020C 0x043C 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x020C 0x043C 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x020C 0x043C 0x0000 0x06 0x00 + +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x0210 0x0440 0x0464 0x00 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x0210 0x0440 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x0210 0x0440 0x0000 0x02 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x0210 0x0440 0x0000 0x03 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT1 0x0210 0x0440 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x0210 0x0440 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x0210 0x0440 0x0460 0x06 0x00 + +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_1 0x0214 0x0444 0x0468 0x00 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_NMI 0x0214 0x0444 0x0000 0x01 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x0214 0x0444 0x0000 0x02 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x0214 0x0444 0x0000 0x03 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT2 0x0214 0x0444 0x0000 0x04 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_10 0x0214 0x0444 0x0000 0x05 0x00 +#define IMX952_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0214 0x0444 0x0478 0x06 0x00 + +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x0218 0x0448 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_1 0x0218 0x0448 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x0218 0x0448 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x0218 0x0448 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x0218 0x0448 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x0218 0x0448 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x021C 0x044C 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x021C 0x044C 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x021C 0x044C 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x021C 0x044C 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x021C 0x044C 0x0460 0x04 0x01 +#define IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x021C 0x044C 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x0220 0x0450 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x0220 0x0450 0x0000 0x01 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x0220 0x0450 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x0220 0x0450 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x0220 0x0450 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x0220 0x0450 0x0000 0x05 0x00 + +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x0224 0x0454 0x0000 0x00 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x0224 0x0454 0x0474 0x01 0x01 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x0224 0x0454 0x0000 0x02 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x0224 0x0454 0x0000 0x03 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x0224 0x0454 0x0000 0x04 0x00 +#define IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x0224 0x0454 0x0000 0x05 0x00 + +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x0228 0x0458 0x0000 0x00 0x00 +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x0228 0x0458 0x0000 0x01 0x00 +#define IMX952_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_15 0x0228 0x0458 0x0000 0x05 0x00 +#endif /* __DTS_IMX952_PINFUNC_H__ */ diff --git a/arch/arm64/boot/dts/freescale/imx952-power.h b/arch/arm64/boot/dts/freescale/imx952-power.h new file mode 100644 index 000000000000..1d0fb8c93e24 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-power.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright 2025 NXP + */ + +#ifndef __IMX952_POWER_H__ +#define __IMX952_POWER_H__ + +#define IMX952_PD_ANA 0 +#define IMX952_PD_AON 1 +#define IMX952_PD_BBSM 2 +#define IMX952_PD_CAMERA 3 +#define IMX952_PD_CCMSRCGPC 4 +#define IMX952_PD_A55C0 5 +#define IMX952_PD_A55C1 6 +#define IMX952_PD_A55C2 7 +#define IMX952_PD_A55C3 8 +#define IMX952_PD_A55P 9 +#define IMX952_PD_DDR 10 +#define IMX952_PD_DISPLAY 11 +#define IMX952_PD_GPU 12 +#define IMX952_PD_HSIO_TOP 13 +#define IMX952_PD_HSIO_WAON 14 +#define IMX952_PD_M7 15 +#define IMX952_PD_NETC 16 +#define IMX952_PD_NOC 17 +#define IMX952_PD_NPU 18 +#define IMX952_PD_VPU 19 +#define IMX952_PD_WAKEUP 20 + +#define IMX952_PERF_M33 0 +#define IMX952_PERF_WAKEUP 1 +#define IMX952_PERF_M7 2 +#define IMX952_PERF_DRAM 3 +#define IMX952_PERF_HSIO 4 +#define IMX952_PERF_NPU 5 +#define IMX952_PERF_NOC 6 +#define IMX952_PERF_A55 7 +#define IMX952_PERF_GPU 8 +#define IMX952_PERF_VPU 9 +#define IMX952_PERF_CAM 10 +#define IMX952_PERF_DISP 11 + +#endif diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi new file mode 100644 index 000000000000..33bde271d394 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -0,0 +1,1248 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +/* + * Copyright 2025 NXP + */ + +#include +#include +#include + +#include "imx952-clock.h" +#include "imx952-pinfunc.h" +#include "imx952-power.h" + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clk_ext1: clock-ext1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133000000>; + clock-output-names = "clk_ext1"; + }; + + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "dummy"; + }; + + clk_ldb_pll_pixel: clock-ldb-pll-div7 { + compatible = "fixed-factor-clock"; + clocks = <&scmi_clk IMX952_CLK_LDBPLL>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + clock-output-names = "ldb_pll_div7"; + }; + + clk_osc_24m: clock-osc-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc_24m"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A55_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + }; + + A55_1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + A55_2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + A55_3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + #cooling-cells = <2>; + power-domains = <&scmi_perf IMX952_PERF_A55>; + power-domain-names = "perf"; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <65536>; + cache-line-size = <64>; + cache-sets = <256>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <3>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&A55_0>; + }; + + core1 { + cpu = <&A55_1>; + }; + + core2 { + cpu = <&A55_2>; + }; + + core3 { + cpu = <&A55_3>; + }; + }; + }; + }; + + firmware { + scmi { + compatible = "arm,scmi"; + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; + shmem = <&scmi_buf0>, <&scmi_buf1>; + #address-cells = <1>; + #size-cells = <0>; + arm,max-rx-timeout-ms = <5000>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_sys_power: protocol@12 { + reg = <0x12>; + }; + + scmi_perf: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensor: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + + scmi_iomuxc: protocol@19 { + reg = <0x19>; + }; + + scmi_lmm: protocol@80 { + reg = <0x80>; + }; + + scmi_bbm: protocol@81 { + reg = <0x81>; + }; + + scmi_cpu: protocol@82 { + reg = <0x82>; + }; + + scmi_misc: protocol@84 { + reg = <0x84>; + }; + }; + }; + + gic: interrupt-controller@48000000 { + compatible = "arm,gic-v3"; + reg = <0 0x48000000 0 0x10000>, + <0 0x48060000 0 0xc0000>; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + dma-noncoherent; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its: msi-controller@48040000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x48040000 0 0x20000>; + msi-controller; + #msi-cells = <1>; + dma-noncoherent; + }; + }; + + pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,no-tick-in-suspend; + interrupt-parent = <&gic>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk_dummy>; + clock-names = "main_clk"; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + clocks = <&clk_dummy>; + clock-names = "main_clk"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>, + <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>; + + aips2: bus@42000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x42000000 0x0 0x800000>; + ranges = <0x42000000 0x0 0x42000000 0x8000000>, + <0x28000000 0x0 0x28000000 0x10000000>; + #address-cells = <1>; + #size-cells = <1>; + + mu7: mailbox@42050000 { + compatible = "fsl,imx95-mu"; + reg = <0x42050000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + + wdog3: watchdog@420b0000 { + compatible = "fsl,imx93-wdt"; + reg = <0x420b0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + timeout-sec = <40>; + status = "disabled"; + }; + + tpm3: pwm@42100000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42100000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm4: pwm@42110000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42110000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM4>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm5: pwm@42120000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42120000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM5>; + #pwm-cells = <3>; + status = "disabled"; + }; + + tpm6: pwm@42130000 { + compatible = "fsl,imx7ulp-pwm"; + reg = <0x42130000 0x1000>; + clocks = <&scmi_clk IMX952_CLK_TPM6>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i3c2: i3c@42140000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42140000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_I3C2SLOW>, + <&clk_dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c3: i2c@42150000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42150000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C3>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c4: i2c@42160000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42160000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C4>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi3: spi@42170000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42170000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI3>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi4: spi@42180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42180000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI4>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart3: serial@42190000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x42190000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART3>; + clock-names = "ipg"; + dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart4: serial@421a0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421a0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART4>; + clock-names = "ipg"; + dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart5: serial@421b0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421b0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART5>; + clock-names = "ipg"; + dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart6: serial@421c0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x421c0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART6>; + clock-names = "ipg"; + dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan2: can@421d0000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x421d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_CAN2>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + flexcan3: can@42220000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x42220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_CAN3>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + lpuart7: serial@422b0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x422b0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART7>; + clock-names = "ipg"; + dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart8: serial@422c0000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x422c0000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART8>; + clock-names = "ipg"; + dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpi2c5: i2c@422d0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C5>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c6: i2c@422e0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422e0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C6>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c7: i2c@422f0000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x422f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C7>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c8: i2c@42300000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x42300000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C8>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi5: spi@42310000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42310000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI5>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi6: spi@42320000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42320000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI6>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi7: spi@42330000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42330000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI7>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi8: spi@42340000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x42340000 0x10000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_LPSPI8>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "per", "ipg"; + dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + mu8: mailbox@42350000 { + compatible = "fsl,imx95-mu"; + reg = <0x42350000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + aips3: bus@42800000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0 0x42800000 0 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x42800000 0x0 0x42800000 0x800000>; + + edma2: dma-controller@42800000 { + compatible = "fsl,imx95-edma5"; + reg = <0x42800000 0x210000>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <64>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; //error irq + }; + + usdhc1: mmc@42c20000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c20000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: mmc@42c30000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c30000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@42c40000 { + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; + reg = <0x42c40000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_WAKEUPAXI>, + <&scmi_clk IMX952_CLK_USDHC3>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-start-tap = <1>; + fsl,tuning-step = <2>; + status = "disabled"; + }; + }; + + gpio2: gpio@43810000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43810000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 4 32>; + ngpios = <32>; + }; + + gpio3: gpio@43820000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43820000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>, + <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>; + ngpios = <32>; + }; + + gpio4: gpio@43840000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43840000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>; + ngpios = <30>; + }; + + gpio5: gpio@43850000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x43850000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, + <&scmi_clk IMX952_CLK_BUSWAKEUP>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>; + ngpios = <18>; + }; + + aips1: bus@44000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x0 0x44000000 0x0 0x800000>; + ranges = <0x44000000 0x0 0x44000000 0x800000>; + #address-cells = <1>; + #size-cells = <1>; + + edma1: dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x210000>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "dma"; + #dma-cells = <3>; + dma-channels = <32>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; //error irq + }; + + mu1: mailbox@44220000 { + compatible = "fsl,imx95-mu"; + reg = <0x44220000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + system_counter: timer@44290000 { + compatible = "nxp,imx95-sysctr-timer"; + reg = <0x44290000 0x30000>; + interrupts = ; + clocks = <&clk_osc_24m>; + clock-names = "per"; + nxp,no-divider; + }; + + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_I3C1SLOW>, + <&clk_dummy>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + + lpi2c1: i2c@44340000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44340000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C1>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpi2c2: i2c@44350000 { + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x44350000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPI2C2>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi1: spi@44360000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44360000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI1>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpspi2: spi@44370000 { + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; + reg = <0x44370000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPSPI2>, + <&scmi_clk IMX952_CLK_BUSAON>; + clock-names = "per", "ipg"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + lpuart1: serial@44380000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44380000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART1>; + clock-names = "ipg"; + dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + lpuart2: serial@44390000 { + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", + "fsl,imx7ulp-lpuart"; + reg = <0x44390000 0x1000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_LPUART2>; + clock-names = "ipg"; + dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + flexcan1: can@443a0000 { + compatible = "fsl,imx95-flexcan"; + reg = <0x443a0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>, + <&scmi_clk IMX952_CLK_CAN1>; + clock-names = "ipg", "per"; + assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>; + assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <40000000>; + fsl,clk-source = /bits/ 8 <0>; + status = "disabled"; + }; + + adc1: adc@44530000 { + compatible = "nxp,imx93-adc"; + reg = <0x44530000 0x10000>; + interrupts = , + , + ; + clocks = <&scmi_clk IMX952_CLK_ADC>; + clock-names = "ipg"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + mu2: mailbox@445b0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445b0000 0x1000>; + ranges; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + #mbox-cells = <2>; + + sram0: sram@445b1000 { + compatible = "mmio-sram"; + reg = <0x445b1000 0x400>; + ranges = <0x0 0x445b1000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_buf0: scmi-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + scmi_buf1: scmi-sram-section@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + + }; + + mu3: mailbox@445d0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445d0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu4: mailbox@445f0000 { + compatible = "fsl,imx95-mu"; + reg = <0x445f0000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu5: mailbox@44610000 { + compatible = "fsl,imx95-mu"; + reg = <0x44610000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu6: mailbox@44630000 { + compatible = "fsl,imx95-mu"; + reg = <0x44630000 0x10000>; + interrupts = ; + clocks = <&scmi_clk IMX952_CLK_BUSAON>; + #mbox-cells = <2>; + status = "disabled"; + }; + }; + + v2x_mu0: mailbox@47300000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47300000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu2: mailbox@47320000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47320000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu3: mailbox@47330000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47330000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu4: mailbox@47340000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47340000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + v2x_mu: mailbox@47350000 { + compatible = "fsl,imx95-mu-v2x"; + reg = <0x0 0x47350000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + /* GPIO1 is under exclusive control of System Manager */ + gpio1: gpio@47400000 { + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; + reg = <0x0 0x47400000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk IMX952_CLK_M33>, + <&scmi_clk IMX952_CLK_M33>; + clock-names = "gpio", "port"; + gpio-ranges = <&scmi_iomuxc 0 123 16>; + ngpios = <16>; + status = "disabled"; + }; + + elemu0: mailbox@47520000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47520000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu1: mailbox@47530000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47530000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu2: mailbox@47540000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47540000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu3: mailbox@47550000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47550000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + elemu4: mailbox@47560000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47560000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + elemu5: mailbox@47570000 { + compatible = "fsl,imx95-mu-ele"; + reg = <0x0 0x47570000 0x0 0x10000>; + interrupts = ; + #mbox-cells = <2>; + status = "disabled"; + }; + + usb1: usb@4c100000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c100000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, + <&scmi_clk IMX952_CLK_OSC32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; + phys = <&usbphynop1>; + fsl,usbmisc = <&usbmisc1 0>; + status = "disabled"; + }; + + usbmisc1: usbmisc@4c100200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x0 0x4c100200 0x0 0x200>, + <0x0 0x4c010010 0x0 0x4>; + }; + + usb2: usb@4c200000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c200000 0x0 0x200>; + interrupts = , + ; + clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, + <&scmi_clk IMX952_CLK_OSC32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; + phys = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@4c200200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + #index-cells = <1>; + reg = <0x0 0x4c200200 0x0 0x200>, + <0x0 0x4c010014 0x0 0x4>; + }; + }; +}; From a5aa8551d0046ec701e8962f83361165ccf640a4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 22 Dec 2025 09:42:16 +0800 Subject: [PATCH 178/757] arm64: dts: freescale: Add i.MX952 EVK basic device tree Add i.MX952 EVK basic device tree, with UART1, SDHC[1,2] supported. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + arch/arm64/boot/dts/freescale/imx952-evk.dts | 217 +++++++++++++++++++ 2 files changed, 219 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx952-evk.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index edb8332ed7e0..633f7c0e33af 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -430,6 +430,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-verdin-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx952-evk.dtb + imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo imx8mm-kontron-bl-lte-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts new file mode 100644 index 000000000000..2c753fcbae3c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include "imx952.dtsi" + +/ { + model = "NXP i.MX952 EVK board"; + compatible = "fsl,imx952-evk", "fsl,imx952"; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &lpuart1; + }; + + chosen { + stdout-path = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + size = <0 0x3c000000>; + linux,cma-default; + reusable; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-name = "vref_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VDD_SD2_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <12000>; + }; +}; + +&lpuart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x15fe + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x13fe + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x13fe + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x13fe + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x13fe + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x13fe + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x13fe + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x13fe + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x13fe + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x13fe + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e + IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e + IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e + IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e + IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e + IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e + IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e + >; + }; +}; From c8614121539494c6dad84df074aa5d89e2d845f7 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 23 Dec 2025 17:05:56 +0800 Subject: [PATCH 179/757] arm64: dts: imx94: add xspi device node imx94 has two xspi, add these device nodes. Signed-off-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx94.dtsi | 34 +++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi index 4fdec712307f..d2f31c8caf6e 100644 --- a/arch/arm64/boot/dts/freescale/imx94.dtsi +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi @@ -629,7 +629,7 @@ compatible = "fsl,aips-bus", "simple-bus"; reg = <0 0x42800000 0 0x800000>; ranges = <0x42800000 0x0 0x42800000 0x800000>, - <0x28000000 0x0 0x28000000 0x1000000>; + <0x24000000 0x0 0x24000000 0xc000000>; #address-cells = <1>; #size-cells = <1>; @@ -785,6 +785,38 @@ #mbox-cells = <2>; status = "disabled"; }; + + xspi1: spi@42b90000 { + compatible = "nxp,imx94-xspi"; + reg = <0x42b90000 0x50000>, <0x28000000 0x08000000>; + reg-names = "base", "mmap"; + interrupts = , // EENV0 + , // EENV1 + , // EENV2 + , // EENV3 + ; // EENV4 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_XSPI1>; + clock-names = "per"; + status = "disabled"; + }; + + xspi2: spi@42be0000 { + compatible = "nxp,imx94-xspi"; + reg = <0x42be0000 0x50000>, <0x24000000 0x04000000>; + reg-names = "base", "mmap"; + interrupts = , // EENV0 + , // EENV1 + , // EENV2 + , // EENV3 + ; // EENV4 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&scmi_clk IMX94_CLK_XSPI2>; + clock-names = "per"; + status = "disabled"; + }; }; gpio2: gpio@43810000 { From 5a0ee673a793c977e94c30ff8b5ac81d8e6a3c0f Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 23 Dec 2025 17:05:57 +0800 Subject: [PATCH 180/757] arm64: dts: imx94: add mt35xu512aba spi nor support Add mt35xu512aba spi nor support on imx943-evk board. This nor chip support OCT DTR mode. For the reset pin, since the nor chip side need 1.8v IO voltage for reset pin, but the IO expander side use 3.3v IO voltage, so to make circuit safe, need to config the pad as OPEN DRAIN. Signed-off-by: Haibo Chen Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx943-evk.dts | 34 ++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts index 98938391497e..31fa9675cee1 100644 --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts @@ -738,6 +738,22 @@ IMX94_PAD_SD2_RESET_B__GPIO4_IO27 0x31e >; }; + + pinctrl_xspi1: xspi1grp { + fsl,pins = < + IMX94_PAD_XSPI1_SCLK__XSPI1_A_SCLK 0x3fe + IMX94_PAD_XSPI1_SS0_B__XSPI1_A_SS0_B 0x3fe + IMX94_PAD_XSPI1_DATA0__XSPI1_A_DATA0 0x3fe + IMX94_PAD_XSPI1_DATA1__XSPI1_A_DATA1 0x3fe + IMX94_PAD_XSPI1_DATA2__XSPI1_A_DATA2 0x3fe + IMX94_PAD_XSPI1_DATA3__XSPI1_A_DATA3 0x3fe + IMX94_PAD_XSPI1_DATA4__XSPI1_A_DATA4 0x3fe + IMX94_PAD_XSPI1_DATA5__XSPI1_A_DATA5 0x3fe + IMX94_PAD_XSPI1_DATA6__XSPI1_A_DATA6 0x3fe + IMX94_PAD_XSPI1_DATA7__XSPI1_A_DATA7 0x3fe + IMX94_PAD_XSPI1_DQS__XSPI1_A_DQS 0x3fe + >; + }; }; &usdhc1 { @@ -769,3 +785,21 @@ fsl,ext-reset-output; status = "okay"; }; + +&xspi1 { + pinctrl-0 = <&pinctrl_xspi1>; + pinctrl-1 = <&pinctrl_xspi1>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mt35xu512aba: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + reset-gpios = <&pcal6416_i2c6_u50 15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + spi-max-frequency = <200000000>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + }; +}; From 5ceddf531b7f5ec4e505f329a9ccc7ef18f7de4e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:25 +0100 Subject: [PATCH 181/757] arm64: dts: freescale: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso | 2 +- arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 2 +- arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ef80bf6a604f..b07022e3b6d5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -278,7 +278,7 @@ clock-names = "sfp"; }; - sec_mon: sec_mon@1e90000 { + sec_mon: sec-mon@1e90000 { compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon"; reg = <0x0 0x1e90000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 22173d69713d..6fefe837f434 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -851,7 +851,7 @@ status = "disabled"; }; - pcie_ep1: pcie_ep@3400000 { + pcie_ep1: pcie-ep@3400000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03400000 0x0 0x00100000>, <0x40 0x00000000 0x8 0x00000000>; @@ -890,7 +890,7 @@ status = "disabled"; }; - pcie_ep2: pcie_ep@3500000 { + pcie_ep2: pcie-ep@3500000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03500000 0x0 0x00100000>, <0x48 0x00000000 0x8 0x00000000>; @@ -929,7 +929,7 @@ status = "disabled"; }; - pcie_ep3: pcie_ep@3600000 { + pcie_ep3: pcie-ep@3600000 { compatible = "fsl,ls1046a-pcie-ep"; reg = <0x00 0x03600000 0x0 0x00100000>, <0x50 0x00000000 0x8 0x00000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso index 43d5905f3d72..414f44b85564 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-rpmsg.dtso @@ -33,7 +33,7 @@ no-map; }; - rsc_table: rsc_table@b80ff000 { + rsc_table: rsc-table@b80ff000 { reg = <0 0xb80ff000 0 0x1000>; no-map; }; diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index b934295bac15..3081513cfc04 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -215,7 +215,7 @@ no-map; }; - vpu_boot: vpu_boot@a0000000 { + vpu_boot: vpu-boot@a0000000 { reg = <0 0xa0000000 0 0x100000>; no-map; }; diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi index 43418844701b..456129f4a682 100644 --- a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi @@ -40,7 +40,7 @@ linux,cma-default; }; - vpu_boot: vpu_boot@a0000000 { + vpu_boot: vpu-boot@a0000000 { reg = <0 0xa0000000 0 0x100000>; no-map; }; From 7dce6d3909cb95108d92fc95dedf18d488e9ccae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:26 +0100 Subject: [PATCH 182/757] arm64: dts: freescale: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' and before '{' characters. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts | 2 +- .../dts/freescale/imx8mp-hummingboard-pulse-common.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 6 +++--- arch/arm64/boot/dts/freescale/imx93-var-som.dtsi | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts index 138f21e257aa..242fa930bd2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts @@ -117,7 +117,7 @@ }; &easrc { - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi index 825ad6a2ba14..fa7cb9759d01 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi @@ -141,7 +141,7 @@ }; &i2c3 { - carrier_eeprom: eeprom@57{ + carrier_eeprom: eeprom@57 { compatible = "st,24c02", "atmel,24c02"; reg = <0x57>; pagesize = <16>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi index 4e6629f940bf..3cdb0bc0ab72 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi @@ -198,7 +198,7 @@ nxp,dvs-standby-voltage = <850000>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -206,7 +206,7 @@ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -264,7 +264,7 @@ }; }; - som_eeprom: eeprom@50{ + som_eeprom: eeprom@50 { compatible = "st,24c01", "atmel,24c01"; reg = <0x50>; pagesize = <16>; diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi index 2dc8b18ae91e..24063bf8183d 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi @@ -131,7 +131,7 @@ regulator-ramp-delay = <3125>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -139,7 +139,7 @@ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; From 202266aee7d54e90a861fcc364993100414b8148 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:27 +0100 Subject: [PATCH 183/757] arm64: dts: freescale: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- .../boot/dts/freescale/fsl-ls1088a-ten64.dts | 4 +-- .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 32 +++++++++---------- .../dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts | 16 +++++----- .../dts/freescale/imx8mp-libra-rdk-fpsc.dts | 2 +- .../freescale/imx8mp-phyboard-pollux-rdk.dts | 2 +- .../dts/freescale/imx8mp-toradex-smarc.dtsi | 6 ++-- .../imx8mp-tqma8mpql-mba8mp-ras314.dts | 2 +- .../freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 2 +- .../dts/freescale/imx8mq-librem5-devkit.dts | 2 +- .../boot/dts/freescale/imx8mq-librem5.dtsi | 6 ++-- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 12 +++---- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 4 +-- arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 6 ++-- .../boot/dts/freescale/imx8x-colibri.dtsi | 2 +- .../boot/dts/freescale/imx95-15x15-evk.dts | 2 +- .../dts/freescale/imx95-toradex-smarc.dtsi | 2 +- arch/arm64/boot/dts/freescale/s32g3.dtsi | 4 +-- .../boot/dts/freescale/s32gxxxa-evb.dtsi | 20 ++++++------ .../boot/dts/freescale/s32gxxxa-rdb.dtsi | 20 ++++++------ 21 files changed, 75 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts index 71765ec91745..f51508952d51 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts @@ -392,13 +392,13 @@ /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */ partition@2800000 { label = "ubia"; - reg = <0x2800000 0x6C00000>; + reg = <0x2800000 0x6c00000>; }; /* ubib (second OpenWrt) */ partition@9400000 { label = "ubib"; - reg = <0x9400000 0x6C00000>; + reg = <0x9400000 0x6c00000>; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index b2f6cd237be0..99016768b73f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -684,7 +684,7 @@ compatible = "arm,mmu-500"; reg = <0 0x5000000 0 0x800000>; #iommu-cells = <1>; - stream-match-mask = <0x7C00>; + stream-match-mask = <0x7c00>; dma-coherent; #global-interrupts = <12>; // global secure fault diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 9421fdd7e30e..6073e426774a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -881,7 +881,7 @@ reg = <0 0x5000000 0 0x800000>; #global-interrupts = <12>; #iommu-cells = <1>; - stream-match-mask = <0x7C00>; + stream-match-mask = <0x7c00>; dma-coherent; interrupts = , /* global secure fault */ , /* combined secure interrupt */ diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index d899c0355e51..853b01452813 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -35,7 +35,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; @@ -52,7 +52,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster0_l2>; @@ -69,7 +69,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; @@ -86,7 +86,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster1_l2>; @@ -103,7 +103,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; @@ -120,7 +120,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster2_l2>; @@ -137,7 +137,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; @@ -154,7 +154,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster3_l2>; @@ -171,7 +171,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; @@ -188,7 +188,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster4_l2>; @@ -205,7 +205,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; @@ -222,7 +222,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster5_l2>; @@ -239,7 +239,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; @@ -256,7 +256,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster6_l2>; @@ -273,7 +273,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; @@ -290,7 +290,7 @@ d-cache-size = <0x8000>; d-cache-line-size = <64>; d-cache-sets = <128>; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <192>; next-level-cache = <&cluster7_l2>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index 0d009f4be804..664f4a6950a8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -147,23 +147,23 @@ }; pinctrl_i2c2: i2c2grp { - fsl,pins = , - ; + fsl,pins = , + ; }; pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = , - ; + fsl,pins = , + ; }; pinctrl_i2c3: i2c3grp { - fsl,pins = , - ; + fsl,pins = , + ; }; pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = , - ; + fsl,pins = , + ; }; pinctrl_pwm3: pwm3grp { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts index ec1f10022248..86b8c5af4153 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts @@ -226,7 +226,7 @@ }; pinctrl_rtc: rtcgrp { fsl,pins = < - MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1C0 + MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 90ec73068a6d..0fe52c73fc8f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -501,7 +501,7 @@ pinctrl_rtc: rtcgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0 + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi index bebe19eb360f..0348da385f23 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi @@ -1044,7 +1044,7 @@ }; pinctrl_mcu_int: mcuintgrp { - fsl,pins = ; /* MCU_INT# */ + fsl,pins = ; /* MCU_INT# */ }; /* SMARC LCD1_BKLT_PWM */ @@ -1096,12 +1096,12 @@ /* SMARC SLEEP# */ pinctrl_sleep: sleepgrp { - fsl,pins = ; /* SMARC S149 - SLEEP# */ + fsl,pins = ; /* SMARC S149 - SLEEP# */ }; /* SMARC SMB_ALERT# */ pinctrl_smb_alert: smbalertgrp { - fsl,pins = ; /* SMARC P1 - SMB_ALERT# */ + fsl,pins = ; /* SMARC P1 - SMB_ALERT# */ }; /* TPM_CS# */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts index 6e927ff1e967..b7f69c92b774 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts @@ -134,7 +134,7 @@ compatible = "shared-dma-pool"; reusable; size = <0 0x38000000>; - alloc-ranges = <0 0x40000000 0 0xB0000000>; + alloc-ranges = <0 0x40000000 0 0xb0000000>; linux,cma-default; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index fdfe246c5640..ad49bf85a04d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -228,7 +228,7 @@ compatible = "shared-dma-pool"; reusable; size = <0 0x38000000>; - alloc-ranges = <0 0x40000000 0 0xB0000000>; + alloc-ranges = <0 0x40000000 0 0xb0000000>; linux,cma-default; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index d9f203c79519..aadaeef928bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -633,7 +633,7 @@ pinctrl_hpdet: hpdetgrp { fsl,pins = < - MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */ + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xc0 /* HP_DET */ >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 9e0e2d7271ef..2975e9451661 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -536,9 +536,9 @@ pinctrl_keys: keysgrp { fsl,pins = < /* VOL- */ - MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0 + MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01c0 /* VOL+ */ - MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0 + MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01c0 >; }; @@ -620,7 +620,7 @@ pinctrl_tcpc: tcpcgrp { fsl,pins = < /* TCPC_INT */ - MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0 + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01c0 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 779d9f78fb81..7d4574c6de1d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -1214,17 +1214,17 @@ pinctrl_mipi_csi0: mipi-csi0grp { fsl,pins = < - IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 - IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 - IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xc0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xc0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041 >; }; pinctrl_mipi_csi1: mipi-csi1grp { fsl,pins = < - IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 - IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 - IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xc0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xc0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xc0000041 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 9e7309a0ca51..f7e28f22343a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -137,7 +137,7 @@ reg = <0x0 0x100>; clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; @@ -241,7 +241,7 @@ gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ - <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x51b00000 0 0xc0000>, /* GICR */ <0x0 0x52000000 0 0x2000>, /* GICC */ <0x0 0x52010000 0 0x1000>, /* GICH */ <0x0 0x52020000 0 0x20000>; /* GICV */ diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 50a97c0297c7..40a0bc9f4e84 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -1062,9 +1062,9 @@ pinctrl_mipi_csi0: mipi-csi0grp { fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 - IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 - IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xc0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xc0000041 + IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 8e9e841cc828..014808774b0e 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -623,7 +623,7 @@ }; pinctrl_csi_mclk: csimclkgrp { - fsl,pins = ; /* SODIMM 75 / X3-12 */ + fsl,pins = ; /* SODIMM 75 / X3-12 */ }; pinctrl_ext_io0: extio0grp { diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts index 3081513cfc04..d4184fb8b28c 100644 --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts @@ -178,7 +178,7 @@ linux_cma: linux,cma { compatible = "shared-dma-pool"; - alloc-ranges = <0 0x80000000 0 0x7F000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; reusable; size = <0 0x3c000000>; linux,cma-default; diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi index afbdadcb3686..a0752f21edf9 100644 --- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi @@ -153,7 +153,7 @@ compatible = "shared-dma-pool"; reusable; size = <0 0x3c000000>; - alloc-ranges = <0 0x80000000 0 0x7F000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; linux,cma-default; }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index eff7673e7f34..e314f3c7d61d 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -641,9 +641,9 @@ status = "disabled"; }; - swt7: watchdog@4020C000 { + swt7: watchdog@4020c000 { compatible = "nxp,s32g3-swt", "nxp,s32g2-swt"; - reg = <0x4020C000 0x1000>; + reg = <0x4020c000 0x1000>; clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>; clock-names = "counter", "module", "register"; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi index f1969cdcef19..803ff4531077 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi @@ -197,16 +197,16 @@ }; dspi1-grp3 { - pinmux = <0x5F0>; + pinmux = <0x5f0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi1-grp4 { - pinmux = <0x3D92>, - <0x3DA2>, - <0x3DB2>; + pinmux = <0x3d92>, + <0x3da2>, + <0x3db2>; }; }; @@ -219,26 +219,26 @@ }; dspi5-grp1 { - pinmux = <0xA0>; + pinmux = <0xa0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi5-grp2 { - pinmux = <0x3ED2>, - <0x3EE2>, - <0x3EF2>; + pinmux = <0x3ed2>, + <0x3ee2>, + <0x3ef2>; }; dspi5-grp3 { - pinmux = <0xB3>; + pinmux = <0xb3>; output-enable; slew-rate = <150>; }; dspi5-grp4 { - pinmux = <0xC3>; + pinmux = <0xc3>; output-enable; input-enable; slew-rate = <150>; diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi index 3bc3335c9248..979868f6d2c5 100644 --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi @@ -151,16 +151,16 @@ }; dspi1-grp3 { - pinmux = <0x5F0>; + pinmux = <0x5f0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi1-grp4 { - pinmux = <0x3D92>, - <0x3DA2>, - <0x3DB2>; + pinmux = <0x3d92>, + <0x3da2>, + <0x3db2>; }; }; @@ -173,26 +173,26 @@ }; dspi5-grp1 { - pinmux = <0xA0>; + pinmux = <0xa0>; input-enable; slew-rate = <150>; bias-pull-up; }; dspi5-grp2 { - pinmux = <0x3ED2>, - <0x3EE2>, - <0x3EF2>; + pinmux = <0x3ed2>, + <0x3ee2>, + <0x3ef2>; }; dspi5-grp3 { - pinmux = <0xB3>; + pinmux = <0xb3>; output-enable; slew-rate = <150>; }; dspi5-grp4 { - pinmux = <0xC3>; + pinmux = <0xc3>; output-enable; input-enable; slew-rate = <150>; From eb2615ad4643c9e3fc6a3c9082084cec744402b9 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 23 Dec 2025 17:28:28 +0100 Subject: [PATCH 184/757] arm64: dts: imx8qm: Add CPU cluster labels Add labels to the cpu cluster nodes to prepare for the addition of the i.MX8QP SoC in which these nodes would need to be adjusted from another DT file. Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index f7e28f22343a..ae7de9f99055 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -38,7 +38,7 @@ #size-cells = <0>; cpu-map { - cluster0 { + cluster0: cluster0 { core0 { cpu = <&A53_0>; }; @@ -53,7 +53,7 @@ }; }; - cluster1 { + cluster1: cluster1 { core0 { cpu = <&A72_0>; }; From 3669332babd0038b714abd3e360be130fd401022 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 23 Dec 2025 17:28:29 +0100 Subject: [PATCH 185/757] arm64: dts: freescale: Add NXP i.MX8QP SoC dtsi Add support for NXP i.MX8QP SoC, this is pin to pin compatible variant of the i.MX8QM, with a slower GPU and one Cortex A72 core instead of two. Link: https://www.nxp.com/products/i.MX8 Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8qp.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qp.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qp.dtsi b/arch/arm64/boot/dts/freescale/imx8qp.dtsi new file mode 100644 index 000000000000..26af9c5a51c5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) + +#include "imx8qm.dtsi" + +/delete-node/ &A72_1; + +&cluster1 { + /delete-node/ core1; +}; + +&gpu_3d0 { + assigned-clock-rates = <625000000>, <625000000>; +}; + +&thermal_zones { + cpu1-thermal { + cooling-maps { + map0 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; From db97615aea6602ce0f81f320eced9574f808b091 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 23 Dec 2025 17:28:30 +0100 Subject: [PATCH 186/757] arm64: dts: freescale: Add Apalis iMX8QP Add support for the Apalis iMX8QP SoM mated with Apalis Ixora and Apalis Evaluation board. Apalis iMX8QP is a variant of the Apalis iMX8QM, using an NXP i.MX8QP SoC instead of the i.MX8QM. The two SoCs are pin to pin compatible, with the i.MX8QP being a lower end variant, with a slower GPU and one Cortex A72 core instead of two. The two Apalis SoMs variants share the same schematics and PCB, and the iMX8QP variant exists only on revision V1.1 of board. Link: https://www.nxp.com/products/i.MX8 Link: https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 Signed-off-by: Francesco Dolcini Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 5 ++++ .../imx8qp-apalis-v1.1-eval-v1.2.dts | 26 +++++++++++++++++++ .../dts/freescale/imx8qp-apalis-v1.1-eval.dts | 16 ++++++++++++ .../imx8qp-apalis-v1.1-ixora-v1.1.dts | 16 ++++++++++++ .../imx8qp-apalis-v1.1-ixora-v1.2.dts | 16 ++++++++++++ .../dts/freescale/imx8qp-apalis-v1.1.dtsi | 16 ++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 633f7c0e33af..c770b1212a34 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -363,6 +363,11 @@ dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-csi1.dtb imx8qm-mek-ov5640-dual-dtbs := imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo imx8qm-mek-ov5640-csi1.dtbo dtb-${CONFIG_ARCH_MXC} += imx8qm-mek-ov5640-dual.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-eval.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-eval-v1.2.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-ixora-v1.1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qp-apalis-v1.1-ixora-v1.2.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts new file mode 100644 index 000000000000..b5318de67cb0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-v1.1-eval-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /delete-property/ no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /delete-property/ no-1-8-v; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts new file mode 100644 index 000000000000..d558cff2582f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8-v1.1-eval", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts new file mode 100644 index 000000000000..a73a6324f552 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.1.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.1 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.1", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts new file mode 100644 index 000000000000..71568d7ec8e5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.2 Carrier Board"; + compatible = "toradex,apalis-imx8-v1.1-ixora-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi new file mode 100644 index 000000000000..1e5311512344 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx8qp.dtsi" +#include "imx8-apalis-v1.1.dtsi" + +&cooling_maps_map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; From 6b9d8ef2908727dd80eacb307d6a409963e4dfe5 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 23 Dec 2025 17:28:27 +0100 Subject: [PATCH 187/757] dt-bindings: arm: fsl: Add Apalis iMX8QP Add binding documentation for the Apalis iMX8QP SoM mated with Apalis Ixora and Apalis Evaluation board. Apalis iMX8QP is a variant of the Apalis iMX8QM, using an NXP i.MX8QP SoC instead of the i.MX8QM. The two SoCs are pin to pin compatible, with the i.MX8QP being a lower end variant, with a slower GPU and one Cortex A72 core instead of two. The two Apalis SoMs variants share the same schematics and PCB, and the iMX8QP variant exists only on revision V1.1 of board. Link: https://www.nxp.com/products/i.MX8 Link: https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 Signed-off-by: Francesco Dolcini Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 971846c60490..65a68acf4377 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1334,7 +1334,7 @@ properties: - const: toradex,apalis-imx8 - const: fsl,imx8qm - - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules + - description: i.MX8QM/i.MX8QP Boards with Toradex Apalis iMX8 V1.1 Modules items: - enum: - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. V1.0/V1.1 Board @@ -1342,7 +1342,9 @@ properties: - toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board - toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board - const: toradex,apalis-imx8-v1.1 - - const: fsl,imx8qm + - enum: + - fsl,imx8qm + - fsl,imx8qp - description: i.MX8QXP based Boards items: From e8280244464c3534112c30491435754eff749337 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Tue, 23 Dec 2025 21:43:02 +0100 Subject: [PATCH 188/757] ARM: dts: imx: imx6sll: fix lcdif compatible Fix lcdif compatible according to bindings doc. dtbs_check tested only, a glance at the datasheet shows that it should be the correct fallback compatible. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sll.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi index 704870e8c10c..c96669605d1d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sll.dtsi @@ -657,7 +657,7 @@ }; lcdif: lcd-controller@20f8000 { - compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx6sll-lcdif", "fsl,imx6sx-lcdif"; reg = <0x020f8000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>, From 03bbb39d9c1f98ec9348ba8521aa2ae17c9f396a Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Tue, 23 Dec 2025 22:34:02 +0100 Subject: [PATCH 189/757] ARM: dts: imx: imx6sll-kobo-clara2e: add regulator for EPD Now there is a driver and binding for the JD9930, so add the information to the devicetree for revision b. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- .../dts/nxp/imx/imx6sll-kobo-clara2e-b.dts | 61 ++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts index f81aeacf5142..f5e88764a08c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clara2e-b.dts @@ -16,8 +16,67 @@ / { model = "Kobo Clara 2E"; compatible = "kobo,clara2e-b", "kobo,clara2e", "fsl,imx6sll"; + + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; }; &i2c2 { - /* EPD PMIC JD9930 at 0x18 */ + jd9930: pmic@18 { + compatible = "fitipower,jd9930", "fitipower,fp9931"; + reg = <0x18>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_jd9930_gpio>; + vin-supply = <&epd_pmic_supply>; + pg-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + en-ts-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + fitipower,tdly-ms = <2 2 2 2>; + + regulators { + vcom_reg: vcom { + regulator-name = "vcom"; + /* + * For optimal performance these should be + * tuned on a per batch basis e.g. using + * overlays. + */ + regulator-min-microvolt = <2352840>; + regulator-max-microvolt = <2352840>; + }; + + vposneg_reg: vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15060000>; + regulator-max-microvolt = <15060000>; + }; + + v3p3_reg: v3p3 { + regulator-name = "v3p3"; + }; + }; + }; +}; + +&iomuxc { + pinctrl_jd9930_gpio: jd9930-gpiogrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x17059 /* PG */ + MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* EN */ + MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x40010059 /* EN_TS */ + >; + }; + + pinctrl_epd_pmic_supply: epd-pmic-supplygrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059 + >; + }; }; From 73368efe2b47b8b3e579673c8fb11b106898b49c Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Tue, 23 Dec 2025 23:24:35 +0100 Subject: [PATCH 190/757] ARM: dts: imx: imx6sl: fix lcdif compatible Fix lcdif compatible according to bindings doc. dtbs_check tested only, a glance at the datasheet shows that it should be the correct fallback compatible. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi index 7381fb7f8912..13b0474aa42c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sl.dtsi @@ -776,7 +776,7 @@ }; lcdif: lcdif@20f8000 { - compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; + compatible = "fsl,imx6sl-lcdif", "fsl,imx6sx-lcdif"; reg = <0x020f8000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, From d703856872d5b875f46d1a781af1df6795780c20 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 31 Oct 2025 13:49:41 +0100 Subject: [PATCH 191/757] arm64: dts: colibri-imx8x: Add backlight Add a backlight node to colibri-imx8x. The node can be enabled from an overlay once display output is implemented. Signed-off-by: Philippe Schenker Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 014808774b0e..b19900b2272a 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -3,7 +3,21 @@ * Copyright 2019 Toradex */ +#include "dt-bindings/pwm/pwm.h" + / { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + power-supply = <®_module_3v3>; + pwms = <&adma_pwm 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + chosen { stdout-path = &lpuart3; }; From d4dc56d8224d1c5a20e06939c817b28a60fbc35e Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Fri, 31 Oct 2025 13:49:42 +0100 Subject: [PATCH 192/757] arm64: dts: colibri-imx8x: Add wi-fi 32kHz clock The Wi-Fi module requires a 32kHz clock to support Wi-Fi/BT low power operation. Setting the pinmuxing option on the connected pin to 32kHz is all needed to generated the signal. Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index b19900b2272a..7c258e8b5aa2 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -490,7 +490,7 @@ /* On-module PCIe for Wi-Fi */ &pcieb { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>; phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; phy-names = "pcie-phy"; reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; From abc8424e7f967c8dcbafdd99ff688e7a35441128 Mon Sep 17 00:00:00 2001 From: Philippe Schenker Date: Fri, 31 Oct 2025 13:49:43 +0100 Subject: [PATCH 193/757] arm64: dts: colibri-imx8x: Add cma memory Add CMA in device tree and set its size to 416MiB for all Colibri iMX8X. The size is tuned to be enough to play full HD video using gst-play and to fit in the SKU with the lowest amount of RAM (1GB). Signed-off-by: Philippe Schenker Signed-off-by: Max Krummenacher Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi index 7c258e8b5aa2..47895ff8cb24 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -86,6 +86,19 @@ regulator-name = "usbh_vbus"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + linux,cma-default; + reusable; + size = <0 0x1a000000>; + }; + }; + sound-card { compatible = "simple-audio-card"; simple-audio-card,bitclock-master = <&dailink_master>; From 6f6c18cba16fe5a8e6d60e5fd277059c2d18dbcc Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 29 Dec 2025 11:31:01 -0500 Subject: [PATCH 194/757] arm64: dts: imx8mp-evk: add camera ov5640 and related nodes Add camera ov5640 and related nodes. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 80 ++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 7ededc1a0617..b256be710ea1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -84,6 +84,27 @@ clock-frequency = <100000000>; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_2v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + reg_audio_3v3: regulator-audio-3v3 { compatible = "regulator-fixed"; regulator-name = "audio-3v3"; @@ -548,6 +569,30 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi0_pwn>, <&pinctrl_csi0_rst>, <&pinctrl_csi_mclk>; + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + assigned-clock-rates = <24000000>; + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + AVDD-supply = <®_2v8>; + DVDD-supply = <®_1v5>; + DOVDD-supply = <®_1v8>; + status = "okay"; + + port { + ov5640_mipi_0_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + data-lanes = <1 2>; + }; + }; + }; + hdmi@3d { compatible = "adi,adv7535"; reg = <0x3d>; @@ -652,6 +697,10 @@ */ }; +&isi_0 { + status = "okay"; +}; + &lcdif1 { status = "okay"; }; @@ -670,6 +719,19 @@ status = "okay"; }; +&mipi_csi_0 { + status = "okay"; + + ports { + port@0 { + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_0_ep>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { samsung,esc-clock-frequency = <10000000>; status = "okay"; @@ -843,6 +905,24 @@ >; }; + pinctrl_csi_mclk: csi_mclk_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x50 + >; + }; + + pinctrl_csi0_pwn: csi0_pwn_grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10 + >; + }; + + pinctrl_csi0_rst: csi0_rst_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 From 1e78a43ec0a0e8e7b291b3320844d6a2b2c8d497 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 30 Dec 2025 02:40:34 +0100 Subject: [PATCH 195/757] dt-bindings: tpm: Add st,st33tphf2ei2c Add the ST chip st33tphf2ei2c to the supported compatible strings of the TPM TIS I2C schema. The chip is compliant with the TCG PC Client TPM Profile specification. For reference, a databrief is available at: https://www.st.com/resource/en/data_brief/st33tphf2ei2c.pdf Acked-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml b/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml index af7720dc4a12..fdd7fd874e01 100644 --- a/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml +++ b/Documentation/devicetree/bindings/tpm/tcg,tpm-tis-i2c.yaml @@ -33,6 +33,7 @@ properties: - infineon,slb9673 - nuvoton,npct75x - st,st33ktpm2xi2c + - st,st33tphf2ei2c - const: tcg,tpm-tis-i2c - description: TPM 1.2 and 2.0 chips with vendor-specific I²C interface From 00398481e06b53fa120b408a0020d3281cfc8121 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 30 Dec 2025 02:40:35 +0100 Subject: [PATCH 196/757] arm64: dts: imx8mp: Update Data Modul i.MX8M Plus eDM SBC DT to rev.903 Update the DT to match newest Data Modul i.MX8M Plus eDM SBC rev.903 board which implements significant changes. Keep some of the rev.900 and rev.902 nodes in the DT so that a DTO can be used to support old rev.900 and rev.902 boards easily. The changes from rev.900 to rev.902 are: - Both ethernet PHYs replaced from AR8031 to BCM54213PE - Both ethernet PHYs MDIO address changed - PCIe WiFi now comes with dedicated regulator - I2C TPM chip address - Additional GPIO expander for LVDS panel control added - Current EEPROM I2C address changed - Another optional EEPROM added onto another I2C bus The changes from rev.902 to rev.903 are: - Additional GPIO expander for WiFi and LVDS panel control added - Multiple GPIOs are reassigned Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- .../freescale/imx8mp-data-modul-edm-sbc.dts | 148 +++++++++++++++--- 1 file changed, 129 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts index 16078ff60ef0..7e46537a22a0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts @@ -93,6 +93,17 @@ status = "disabled"; }; + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi>; + regulator-name = "WIFI_BT_RST#"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -190,7 +201,7 @@ &eqos { /* First ethernet */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; - phy-handle = <&phy_eqos>; + phy-handle = <&phy_eqos_bcm>; phy-mode = "rgmii-id"; status = "okay"; @@ -200,7 +211,7 @@ #size-cells = <0>; /* Atheros AR8031 PHY */ - phy_eqos: ethernet-phy@0 { + phy_eqos_ath: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; /* @@ -213,6 +224,7 @@ reset-deassert-us = <10000>; qca,keep-pll-enabled; vddio-supply = <&vddio_eqos>; + status = "disabled"; vddio_eqos: vddio-regulator { regulator-name = "VDDIO_EQOS"; @@ -224,13 +236,27 @@ regulator-name = "VDDH_EQOS"; }; }; + + /* Broadcom BCM54213PE PHY */ + phy_eqos_bcm: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * Dedicated ENET_INT# and ENET_WOL# signals are + * unused, the PHY does not provide cable detect + * interrupt. + */ + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; }; }; &fec { /* Second ethernet */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; - phy-handle = <&phy_fec>; + phy-handle = <&phy_fec_bcm>; phy-mode = "rgmii-id"; fsl,magic-packet; status = "okay"; @@ -240,7 +266,7 @@ #size-cells = <0>; /* Atheros AR8031 PHY */ - phy_fec: ethernet-phy@0 { + phy_fec_ath: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; /* @@ -253,6 +279,7 @@ reset-deassert-us = <10000>; qca,keep-pll-enabled; vddio-supply = <&vddio_fec>; + status = "disabled"; vddio_fec: vddio-regulator { regulator-name = "VDDIO_FEC"; @@ -264,6 +291,20 @@ regulator-name = "VDDH_FEC"; }; }; + + /* Broadcom BCM54213PE PHY */ + phy_fec_bcm: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * Dedicated ENET_INT# and ENET_WOL# signals are + * unused, the PHY does not provide cable detect + * interrupt. + */ + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; }; }; @@ -378,13 +419,26 @@ self-powered; }; - eeprom: eeprom@50 { + tpm: tpm@2e { + compatible = "st,st33tphf2ei2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + }; + + eeprom900: eeprom@50 { /* board rev.900 */ compatible = "atmel,24c32"; reg = <0x50>; pagesize = <32>; + status = "disabled"; + }; + + eeprom902: eeprom@51 { /* board rev.902 */ + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; }; rtc: rtc@68 { + #clock-cells = <1>; compatible = "st,m41t62"; reg = <0x68>; pinctrl-names = "default"; @@ -408,6 +462,46 @@ scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + + gpiolvds: io-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "BL_ENABLE_V", "SEL_BL_12V", + "SEL_PANEL_5V", "SEL_PANEL_12V", + "SEL_BL_PWM", "SEL_BL_EN", + "REVERSE_SCAN_PANEL", "GND_REV903"; + }; + + gpiowifi: io-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "BL_LVDS_ENABLE_3V3", "BL_LVDS_PWM_3V3", + "M2_BT_WAKE_3V3#", "M2_W_DISABLE2_3V3#", + "TFT_PANEL_ENABLE_3V3", "TPM_RESET_3V3#", + "CSI2_PD_3V3", "CSI2_RESET_3V3#"; + + /* BL_LVDS_PWM_3V3 is patch-wired to BL_PWM_3V3 on rev.903 */ + pwm-input-hog { + gpio-hog; + gpios = <1 0>; + input; + line-name = "BL_LVDS_PWM_3V3_HOG"; + }; + }; + + eepromlvds: eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + /* Optional EEPROM, disabled by default. */ + status = "disabled"; + }; }; &i2c3 { @@ -521,6 +615,7 @@ pinctrl-0 = <&pinctrl_pcie0>; fsl,max-link-speed = <3>; reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie0>; status = "okay"; }; @@ -598,7 +693,17 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; - status = "disabled"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw55572-bt"; + brcm,requires-autobaud-mode; + clocks = <&rtc 0>; + clock-names = "txco"; + max-speed = <921600>; + shutdown-gpios = <&gpiowifi 3 GPIO_ACTIVE_HIGH>; + }; }; &usb3_phy0 { @@ -686,8 +791,6 @@ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 /* ENET_RST# */ MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x6 - /* ENET_INT# */ - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000090 >; }; @@ -709,8 +812,6 @@ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f /* ENET2_RST# */ MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x6 - /* ENET2_INT# */ - MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 >; }; @@ -754,10 +855,6 @@ /* PG_V_IN_VAR# */ MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x40000000 - /* CSI2_PD_1V8 */ - MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x0 - /* CSI2_RESET_1V8# */ - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x0 /* DIS_USB_DN1 */ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0 @@ -771,8 +868,14 @@ /* GRAPHICS_PRSNT_1V8# */ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000000 + /* TOUCH_RESET_3V3# */ + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x2 + /* TOUCH_INT# */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40000140 /* CLK_CCM_CLKO1_3V3 */ MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x10 + /* ENET_INT# (rev.900,901) or M2_WDIS_BTIRQ_3V3# (rev.903) */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000092 >; }; @@ -875,12 +978,10 @@ fsl,pins = < /* M2_PCIE_RST# */ MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x2 - /* M2_W_DISABLE1_1V8# */ + /* M2_PCIE_WAKE_1V8# */ MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x2 - /* M2_W_DISABLE2_1V8# */ - MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x2 - /* CLK_M2_32K768 */ - MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x14 + /* M2_UART_WAKE_1V8# */ + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x40000002 /* M2_PCIE_WAKE# */ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40000140 /* M2_PCIE_CLKREQ# */ @@ -974,6 +1075,8 @@ fsl,pins = < MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x149 + MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x149 >; }; @@ -1100,4 +1203,11 @@ MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x26 >; }; + + pinctrl_wifi: wifi-grp { + fsl,pins = < + /* WIFI_BT_RST_3V3# */ + MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x40000090 + >; + }; }; From 77e18c63a38bd149f74a53e9c232254431e4de1c Mon Sep 17 00:00:00 2001 From: Joseph Guo Date: Tue, 30 Dec 2025 16:58:53 +0900 Subject: [PATCH 197/757] dt-bindings: arm: fsl: Add FRDM-IMX91 board Add the board FRDM-IMX91 in the binding document. Reviewed-by: Daniel Baluta Acked-by: Krzysztof Kozlowski Reviewed-by: Francesco Valla Tested-by: Francesco Valla Signed-off-by: Joseph Guo Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 65a68acf4377..433f555232e9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1415,6 +1415,7 @@ properties: items: - enum: - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board - const: fsl,imx91 - description: i.MX93 based Boards From b4bf5e55899e8c2662a6f0e221128f590ac5f331 Mon Sep 17 00:00:00 2001 From: Joseph Guo Date: Tue, 30 Dec 2025 16:58:54 +0900 Subject: [PATCH 198/757] arm64: dts: freescale: Add FRDM-IMX91 basic support The FRDM i.MX 91 development board is a low-cost and compact developmentboard featuring the i.MX 91 applications processor: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91 Add FRDM-IMX91 board dts support. - Enable ADC1. - Enable lpuart1 and lpuart5. - Enable network eqos and fec. - Enable I2C bus and children nodes under I2C bus. - Enable USB and related nodes. - Enable uSDHC1, uSDHC2 and uSDHC3. - Enable MU1 and MU2. - Enable Watchdog3. - Enable MQS Co-developed-by: Tom Zheng Signed-off-by: Tom Zheng Co-developed-by: Steven Yang Signed-off-by: Steven Yang Reviewed-by: Andrew Lunn Reviewed-by: Francesco Valla Tested-by: Francesco Valla Signed-off-by: Joseph Guo Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx91-11x11-frdm.dts | 906 ++++++++++++++++++ 2 files changed, 907 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c770b1212a34..ce8f937c2315 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -386,6 +386,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts new file mode 100644 index 000000000000..0d1acf8a55a5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts @@ -0,0 +1,906 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include "imx91.dtsi" + +/ { + compatible = "fsl,imx91-11x11-frdm", "fsl,imx91"; + model = "NXP i.MX91 11x11 FRDM Board"; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &bbnsm_rtc; + rtc1 = &pcf2131; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + stdout-path = &lpuart1; + }; + + flexcan_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + enable-gpios = <&pcal6524 23 GPIO_ACTIVE_LOW>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-k2 { + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + label = "Button K2"; + gpios = <&pcal6524 5 GPIO_PULL_UP>; + linux,code = ; + }; + + button-k3 { + interrupt-parent = <&pcal6524>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + label = "Button K3"; + gpios = <&pcal6524 6 GPIO_PULL_UP>; + linux,code = ; + }; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power"; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + bootph-pre-ram; + bootph-some-ram; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * This regulator defined as PDn pin of the IW610 wifi module. + * IW610 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW610 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_vdd_12v: regulator-vdd-12v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "reg_vdd_12v"; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vexp_3v3: regulator-vexp-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VEXP_3V3"; + vin-supply = <&buck4>; + gpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vexp_5v: regulator-vexp-5v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VEXP_5V"; + gpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x30000000>; + reusable; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + soc@0 { + bootph-all; + bootph-pre-ram; + }; + + sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + audio-codec = <&mqs1>; + audio-cpu = <&sai1>; + model = "mqs-audio"; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&clk { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&eqos { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_eqos>; + pinctrl-1 = <&pinctrl_eqos_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&fec { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + pinctrl-names = "default", "sleep"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy2: ethernet-phy@2 { + reg = <2>; + reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>; + reset-assert-us = <15000>; + reset-deassert-us = <100000>; + }; + }; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; + pinctrl-names = "default", "sleep"; + phys = <&flexcan_phy>; + status = "okay"; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcal6408: gpio@20 { + compatible = "nxp,pcal9554b"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_usdhc3_vmmc>; + status = "okay"; + }; +}; + +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio3>; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2237500>; + regulator-min-microvolt = <650000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK4"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK5"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <600000>; + regulator-name = "BUCK6"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1600000>; + regulator-name = "LDO1"; + }; + + ldo4: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <800000>; + regulator-name = "LDO4"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio3>; + + typec1_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; + + pcf2131: rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pcal6524>; + status = "okay"; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&mqs1 { + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + pinctrl-0 = <&pinctrl_mqs1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&sai1 { + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + status = "okay"; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + no-mmc; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e + MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe + MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e + MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_eqos_sleep: eqossleepgrp { + fsl,pins = < + MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e + MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e + MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e + MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e + MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e + MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e + MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e + MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e + MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e + MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e + MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e + MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e + MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e + MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e + MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e + MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe + MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e + MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e + MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e + MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e + MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e + MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe + MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e + >; + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = < + MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e + MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e + MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e + MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e + MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e + MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e + MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e + MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e + MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e + MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e + MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e + MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX91_PAD_GPIO_IO25__CAN2_TX 0x139e + MX91_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_flexcan2_sleep: flexcan2sleepgrp { + fsl,pins = < + MX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e + MX91_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + MX91_PAD_GPIO_IO08__GPIO2_IO8 0x3fe + MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x3fe + MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x3fe + MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x3fe + >; + }; + + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX91_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e + >; + bootph-pre-ram; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX91_PAD_UART1_RXD__LPUART1_RX 0x31e + MX91_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX91_PAD_DAP_TDI__LPUART5_RX 0x31e + MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe + MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { + fsl,pins = < + MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 + MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + bootph-pre-ram; + bootph-some-ram; + }; + + pinctrl_usdhc2_sleep: usdhc2sleepgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e + MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e + MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e + MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e + MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e + MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e + MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e + MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe + MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe + MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3sleepgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins = < + MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe + MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; From f0d0f087227c4b63538e4ed8292f1fa26f8d6633 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:24:58 +0100 Subject: [PATCH 199/757] arm64: dts: arm: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Acked-by: Vincenzo Frascino Message-Id: <20251223152457.155392-3-krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/morello-fvp.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/arm/morello-fvp.dts index 2072c0b72325..4a3f217555f7 100644 --- a/arch/arm64/boot/dts/arm/morello-fvp.dts +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -25,25 +25,25 @@ clock-output-names = "bp:clock24mhz"; }; - block_0: virtio_block@1c170000 { + block_0: virtio-block@1c170000 { compatible = "virtio,mmio"; reg = <0x0 0x1c170000 0x0 0x200>; interrupts = ; }; - net_0: virtio_net@1c180000 { + net_0: virtio-net@1c180000 { compatible = "virtio,mmio"; reg = <0x0 0x1c180000 0x0 0x200>; interrupts = ; }; - rng_0: virtio_rng@1c190000 { + rng_0: virtio-rng@1c190000 { compatible = "virtio,mmio"; reg = <0x0 0x1c190000 0x0 0x200>; interrupts = ; }; - p9_0: virtio_p9@1c1a0000 { + p9_0: virtio-p9@1c1a0000 { compatible = "virtio,mmio"; reg = <0x0 0x1c1a0000 0x0 0x200>; interrupts = ; From 5fc25d64c43c1e25a1a0184a894ab0721c6a524b Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 3 Jan 2026 11:27:05 +0530 Subject: [PATCH 200/757] dt-bindings: clock: qcom,x1e80100-gcc: Add missing UFS mux clocks Add some of the UFS symbol rx/tx muxes were not initially described. Signed-off-by: Taniya Das Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260103-ufs_symbol_clk-v2-1-51828cc76236@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,x1e80100-gcc.yaml | 8 +++++++- include/dt-bindings/clock/qcom,x1e80100-gcc.h | 3 +++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml index 1b15b5070954..881a5dd8d06f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml @@ -62,6 +62,9 @@ properties: - description: USB4_1 PHY max PIPE clock source - description: USB4_2 PHY PCIE PIPE clock source - description: USB4_2 PHY max PIPE clock source + - description: UFS PHY RX Symbol 0 clock source + - description: UFS PHY RX Symbol 1 clock source + - description: UFS PHY TX Symbol 0 clock source power-domains: description: @@ -121,7 +124,10 @@ examples: <&usb4_1_phy_pcie_pipe_clk>, <&usb4_1_phy_max_pipe_clk>, <&usb4_2_phy_pcie_pipe_clk>, - <&usb4_2_phy_max_pipe_clk>; + <&usb4_2_phy_max_pipe_clk>, + <&ufs_phy_rx_symbol_0>, + <&ufs_phy_rx_symbol_1>, + <&ufs_phy_tx_symbol_0>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h index 62aa12425592..d905804e6465 100644 --- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h +++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h @@ -387,6 +387,9 @@ #define GCC_USB4_2_PHY_RX0_CLK_SRC 377 #define GCC_USB4_2_PHY_RX1_CLK_SRC 378 #define GCC_USB4_2_PHY_SYS_CLK_SRC 379 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 380 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 381 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 382 /* GCC power domains */ #define GCC_PCIE_0_TUNNEL_GDSC 0 From 65b705cca009ffdf00ad7b649ac8a7e063373ddc Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Sat, 3 Jan 2026 11:27:07 +0530 Subject: [PATCH 201/757] arm64: dts: qcom: hamoa: Extend the gcc input clock list The recent dt-bindings were updated for the missing RX/TX symbol clocks for UFS. Extend the existing list to make sure the DT contains the expected amount of 'clocks' entries. Reviewed-by: Dmitry Baryshkov Reviewed-by: Abel Vesa Signed-off-by: Taniya Das Link: https://lore.kernel.org/r/20260103-ufs_symbol_clk-v2-3-51828cc76236@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index bb7c14d473c9..21ab6ef61520 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -834,6 +834,9 @@ <0>, <0>, <0>, + <0>, + <0>, + <0>, <0>; power-domains = <&rpmhpd RPMHPD_CX>; From 3802966a9c489708228b98b7265d8db87d8f6db3 Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Sat, 3 Jan 2026 10:00:23 +0100 Subject: [PATCH 202/757] arm64: dts: qcom: x1p42100-lenovo-thinkbook-16: force usb2-only mode on usb_1_ss2_dwc3 The usb_1_ss2 complex has 2 phys, usb_1_ss2_hsphy and usb_1_ss2_qmpphy. On this laptop, they are used for different peripherals: The hsphy for the fingerprint reader, the qmpphy to drive a hdmi bridge. The normal logical wiring for the dwc3 controller is to both phys. Delete the port@1 to the qmpphy. Signed-off-by: Jens Glathe Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260103-tb16-hdmi-v2-1-92b0930fa82e@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index 3186e79e862d..b4a40904f0a0 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -1560,6 +1560,8 @@ maximum-speed = "high-speed"; phys = <&usb_1_ss2_hsphy>; phy-names = "usb2-phy"; + + /delete-property/ port@1; }; &usb_1_ss2_hsphy { From 67ce203eee94946768397a6fa16c43ee5292f31a Mon Sep 17 00:00:00 2001 From: Jens Glathe Date: Sat, 3 Jan 2026 10:00:24 +0100 Subject: [PATCH 203/757] arm64: dts: qcom: x1p42100-lenovo-thinkbook-16: add hdmi bridge with enable pin Add TLMM 120 for hdmi bridge enable. In general this is the same setup as on the T14s. Since its using simple-bridge and also is Lenovo, we also use the same realtek,rtd2171 compatible. The real chip identity is not known yet. The bridge is wired with un-swapped lanes, though. Signed-off-by: Jens Glathe Link: https://lore.kernel.org/r/20260103-tb16-hdmi-v2-2-92b0930fa82e@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts index b4a40904f0a0..1e5eb8c5dc98 100644 --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts @@ -78,6 +78,47 @@ vdd-supply = <&vreg_cam_5p0>; }; + hdmi-bridge { + compatible = "realtek,rtd2171"; + + enable-gpios = <&tlmm 120 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -1038,6 +1079,14 @@ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -1327,6 +1376,19 @@ bias-disable; }; + hdmi_bridge_en: hdmi-bridge-en-state { + pins = "gpio120"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + }; + + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + kybd_default: kybd-default-state { pins = "gpio67"; function = "gpio"; @@ -1573,6 +1635,32 @@ status = "okay"; }; +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <0 1 2 3>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + }; + }; +}; + &usb_2 { status = "okay"; }; From eb1bcc1d3b4b6c7f7dddbe62ac229e4e3d8d5f8d Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Fri, 22 Aug 2025 09:53:16 +0530 Subject: [PATCH 204/757] arm64: dts: qcom: qcs8300: Enable TSENS support for QCS8300 SoC Add TSENS and thermal devicetree node for QCS8300 SoC. Signed-off-by: Gaurav Kohli Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250822042316.1762153-3-quic_gkohli@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 526 +++++++++++++++++++++++++++ 1 file changed, 526 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 816fa2af8a9a..468ec781487b 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4851,6 +4851,50 @@ <235 723 5>; }; + tsens2: thermal-sensor@c251000 { + compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c251000 0x0 0x1000>, + <0x0 0x0c224000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + tsens3: thermal-sensor@c252000 { + compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c252000 0x0 0x1000>, + <0x0 0x0c225000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + tsens0: thermal-sensor@c263000 { + compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c263000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c265000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-management@c300000 { compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; @@ -6220,6 +6264,488 @@ }; }; + thermal_zones: thermal-zones { + aoss-0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-0-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-0-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-0-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-0-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + gpuss0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + audio-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + audio-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camss-0-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + camss-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + pcie-0-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + pcie-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-0-0-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + cpuss0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-0-1-thermal { + thermal-sensors = <&tsens1 1>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-1-1-thermal { + thermal-sensors = <&tsens1 2>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-2-1-thermal { + thermal-sensors = <&tsens1 3>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-0-3-1-thermal { + thermal-sensors = <&tsens1 4>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss-1-thermal { + thermal-sensors = <&tsens1 5>; + + trips { + gpuss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens1 6>; + + trips { + video-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + camss-1-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + camss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + pcie-1-thermal { + thermal-sensors = <&tsens1 8>; + + trips { + pcie-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-0-1-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + cpuss0-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors = <&tsens2 0>; + + trips { + aoss2-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-0-thermal { + thermal-sensors = <&tsens2 1>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-0-thermal { + thermal-sensors = <&tsens2 2>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-0-thermal { + thermal-sensors = <&tsens2 3>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-0-thermal { + thermal-sensors = <&tsens2 4>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-0-0-thermal { + thermal-sensors = <&tsens2 5>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-1-0-thermal { + thermal-sensors = <&tsens2 6>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-2-0-thermal { + thermal-sensors = <&tsens2 7>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddrss-0-thermal { + thermal-sensors = <&tsens2 8>; + + trips { + ddrss-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-1-0-thermal { + thermal-sensors = <&tsens2 9>; + + trips { + cpuss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors = <&tsens3 0>; + + trips { + aoss3-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-0-1-thermal { + thermal-sensors = <&tsens3 1>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-1-1-thermal { + thermal-sensors = <&tsens3 2>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-2-1-thermal { + thermal-sensors = <&tsens3 3>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu-1-3-1-thermal { + thermal-sensors = <&tsens3 4>; + + trips { + cpu-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-0-1-thermal { + thermal-sensors = <&tsens3 5>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-1-1-thermal { + thermal-sensors = <&tsens3 6>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsp-0-2-1-thermal { + thermal-sensors = <&tsens3 7>; + + trips { + nsp-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + ddrss-1-thermal { + thermal-sensors = <&tsens3 8>; + + trips { + ddrss-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpuss-1-1-thermal { + thermal-sensors = <&tsens3 9>; + + trips { + cpuss1-critical { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From e8560ac937d92e16e636bbaf387f638b3198fa9c Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Dec 2025 06:15:02 +0200 Subject: [PATCH 205/757] arm64: dts: qcom: sm8650: Add CAMSS device tree node Add Qualcomm SM8650 CAMSS device tree node to the platform dtsi file, the SM8650 CAMSS IP contains * 6 x CSIPHY, * 3 x CSID, 2 x CSID Lite, * 3 x IFE, 2 x IFE Lite. Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20251204041505.131891-2-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 187 +++++++++++++++++++++++++++ 1 file changed, 187 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 07ae74851621..06eedd2cd782 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -5380,6 +5380,193 @@ }; }; + camss: isp@acb6000 { + compatible = "qcom,sm8650-camss"; + + reg = <0 0x0acb6000 0 0x1000>, + <0 0x0acb8000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acbc000 0 0x1000>, + <0 0x0accb000 0 0x1000>, + <0 0x0acd0000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accc000 0 0x2000>, + <0 0x0acd1000 0 0x2000>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cpas_fast_ahb", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "cpas_vfe_lite", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy_rx", + "gcc_axi_hf", + "qdss_debug_xo", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 + &mc_virt SLAVE_EBI1 0>; + interconnect-names = "ahb", + "hf_mnoc"; + + iommus = <&apps_smmu 0x800 0x20>, + <&apps_smmu 0x18a0 0x40>, + <&apps_smmu 0x1860 0x00>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", "ife1", "ife2", "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,sm8650-camcc"; reg = <0 0x0ade0000 0 0x20000>; From 0ddb0d63453f320806727604702b6f6636a645c3 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Dec 2025 06:15:03 +0200 Subject: [PATCH 206/757] arm64: dts: qcom: sm8650: Add description of MCLK pins Add fixed MCLK pin descriptions for all pins with such supported function. Reviewed-by: Bryan O'Donoghue Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251204041505.131891-3-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 112 +++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 06eedd2cd782..e528e9948faf 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -6109,6 +6109,118 @@ wakeup-parent = <&pdc>; + cam0_default: cam0-default-state { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam0_sleep: cam0-sleep-state { + pins = "gpio100"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam1_default: cam1-default-state { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam1_sleep: cam1-sleep-state { + pins = "gpio101"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam2_default: cam2-default-state { + pins = "gpio102"; + function = "cam_aon_mclk2"; + drive-strength = <2>; + bias-disable; + }; + + cam2_sleep: cam2-sleep-state { + pins = "gpio102"; + function = "cam_aon_mclk2"; + drive-strength = <2>; + bias-pull-down; + }; + + cam3_default: cam3-default-state { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam3_sleep: cam3-sleep-state { + pins = "gpio103"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam4_default: cam4-default-state { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-disable; + }; + + cam4_sleep: cam4-sleep-state { + pins = "gpio104"; + function = "cam_aon_mclk4"; + drive-strength = <2>; + bias-pull-down; + }; + + cam5_default: cam5-default-state { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam5_sleep: cam5-sleep-state { + pins = "gpio105"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam6_default: cam6-default-state { + pins = "gpio108"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam6_sleep: cam6-sleep-state { + pins = "gpio108"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + + cam7_default: cam7-default-state { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cam7_sleep: cam7-sleep-state { + pins = "gpio106"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + cci0_0_default: cci0-0-default-state { sda-pins { pins = "gpio113"; From 328407ba89ae6656c143967ba65465c50150aaf8 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Dec 2025 06:15:04 +0200 Subject: [PATCH 207/757] arm64: dts: qcom: sm8650-qrd: Enable CAMSS and Samsung S5KJN1 camera sensor Add support of Samsung S5KJN1 camera sensor connected to CSIPHY3 over MIPI D-PHY interface. Tested-by: Neil Armstrong # on SM8650-QRD Signed-off-by: Vladimir Zapolskiy Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20251204041505.131891-4-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 43 +++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index b2feac61a89f..f990e68c7a87 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -741,6 +741,49 @@ }; }; +&camss { + vdd-csiphy35-0p9-supply = <&vreg_l2i_0p88>; + vdd-csiphy35-1p2-supply = <&vreg_l3i_1p2>; + status = "okay"; + + ports { + port@3 { + csiphy3_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_tele>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + sensor@56 { + compatible = "samsung,s5kjn1"; + reg = <0x56>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam3_default>; + pinctrl-names = "default"; + afvdd-supply = <&vreg_l7m_2p96>; + vdda-supply = <&vreg_l4m_2p8>; + vddd-supply = <&vreg_l2m_1p056>; + vddio-supply = <&vreg_l3n_1p8>; + + port { + cam_tele: endpoint { + link-frequencies = /bits/ 64 <700000000>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + &gpi_dma1 { status = "okay"; }; From 1c20a021de58a23bdc264b91d75e944d19e49ba2 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Thu, 4 Dec 2025 06:15:05 +0200 Subject: [PATCH 208/757] arm64: dts: qcom: sm8650-hdk: Add support for the Rear Camera Card overlay To provide access to camera sensors a Rear Camera Card can be connected to SM8650-HDK board, the camera sensors are: * Samsung S5K33D ToF camera sensor, connected to CSI0 over MIPI D-PHY, * Sony IMX766 Wide camera sensor, connected to CSI1 over MIPI C-PHY, * Omnivision OV64B Ultrawide camera sensor, connected to CSI2 over MIPI C-PHY, * Samsung S5KJN1 Tele camera sensor, connected to CSI3 over MIPI D-PHY). Get the initial support of Samsung S5KJN1 camera sensor and two flash leds on the Rear Camera Card board by adding a board overlay. Signed-off-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20251204041505.131891-5-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../dts/qcom/sm8650-hdk-rear-camera-card.dtso | 88 +++++++++++++++++++ 2 files changed, 92 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 76cf0115a00a..02b8e4d761a1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -317,8 +317,12 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8550-samsung-q5q.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-sony-xperia-yodo-pdx234.dtb sm8650-hdk-display-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo +sm8650-hdk-display-card-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-display-card.dtbo sm8650-hdk-rear-camera-card.dtbo +sm8650-hdk-rear-camera-card-dtbs := sm8650-hdk.dtb sm8650-hdk-rear-camera-card.dtbo +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card-rear-camera-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-rear-camera-card.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso b/arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso new file mode 100644 index 000000000000..8a7c6d7634d3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk-rear-camera-card.dtso @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * SM8650-HDK Rear Camera Card overlay + * + * Copyright (c) 2025, Linaro Limited + */ + +#include +#include +#include + +/dts-v1/; +/plugin/; + +&camss { + vdd-csiphy35-0p9-supply = <&vreg_l2i_0p88>; + vdd-csiphy35-1p2-supply = <&vreg_l3i_1p2>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@3 { + reg = <3>; + + csiphy3_ep: endpoint { + data-lanes = <0 1 2 3>; + remote-endpoint = <&cam_tele>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + sensor@56 { + compatible = "samsung,s5kjn1"; + reg = <0x56>; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + reset-gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&cam3_default>; + pinctrl-names = "default"; + afvdd-supply = <&vreg_l7m_2p96>; + vdda-supply = <&vreg_l4m_2p8>; + vddd-supply = <&vreg_l2m_1p056>; + vddio-supply = <&vreg_l3n_1p8>; + + port { + cam_tele: endpoint { + link-frequencies = /bits/ 64 <700000000>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; From 6940c66825e4c27c53b33e367806ac1dc922583d Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Tue, 30 Dec 2025 18:03:25 +0530 Subject: [PATCH 209/757] arm64: dts: qcom: lemans: Add gpu and gmu nodes Add gpu and gmu nodes for Lemans chipset. Also, add the speedbin qfprom node and wire it up with GPU node. Signed-off-by: Puranam V G Tejaswi Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen Link: https://lore.kernel.org/r/20251230-a663-gpu-support-v9-1-186722e25387@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 119 +++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 0b154d57ba24..883f9e0ab45c 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -1098,6 +1098,18 @@ #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; + reg = <0x0 0x00784000 0x0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@240c { + reg = <0x240c 0x1>; + bits = <0 8>; + }; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x00800000 0x0 0x60000>; @@ -4135,6 +4147,113 @@ reg = <0x0 0x1fc0000 0x0 0x30000>; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-663.0", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-405000000 { + opp-hz = /bits/ 64 <405000000>; + opp-level = ; + opp-peak-kBps = <5285156>; + opp-supported-hw = <0x3>; + }; + + opp-530000000 { + opp-hz = /bits/ 64 <530000000>; + opp-level = ; + opp-peak-kBps = <12484375>; + opp-supported-hw = <0x2>; + }; + + opp-676000000 { + opp-hz = /bits/ 64 <676000000>; + opp-level = ; + opp-peak-kBps = <8171875>; + opp-supported-hw = <0x1>; + }; + + opp-778000000 { + opp-hz = /bits/ 64 <778000000>; + opp-level = ; + opp-peak-kBps = <10687500>; + opp-supported-hw = <0x1>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + opp-peak-kBps = <12484375>; + opp-supported-hw = <0x1>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sa8775p-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>; From 4a6488a8070b95702d6f5dec444fbddfaaaff8cf Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 30 Dec 2025 18:03:26 +0530 Subject: [PATCH 210/757] arm64: dts: qcom: lemans: Add GPU cooling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when reaching 105°C. Signed-off-by: Gaurav Kohli Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251230-a663-gpu-support-v9-2-186722e25387@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 55 +++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 883f9e0ab45c..14d9f31e7086 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -21,6 +21,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -7514,8 +7515,15 @@ thermal-sensors = <&tsens0 5>; + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss0_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7534,8 +7542,15 @@ thermal-sensors = <&tsens0 6>; + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss1_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7554,8 +7569,15 @@ thermal-sensors = <&tsens0 7>; + cooling-maps { + map0 { + trip = <&gpuss2_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss2_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7744,8 +7766,15 @@ thermal-sensors = <&tsens1 5>; + cooling-maps { + map0 { + trip = <&gpuss3_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss3_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7764,8 +7793,15 @@ thermal-sensors = <&tsens1 6>; + cooling-maps { + map0 { + trip = <&gpuss4_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss4_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; @@ -7784,8 +7820,15 @@ thermal-sensors = <&tsens1 7>; + cooling-maps { + map0 { + trip = <&gpuss5_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + trips { - trip-point0 { + gpuss5_alert0: trip-point0 { temperature = <105000>; hysteresis = <5000>; type = "passive"; From dbff283922e32eaa3d81233b69c02ef2abe7ee9b Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 30 Dec 2025 18:03:27 +0530 Subject: [PATCH 211/757] arm64: dts: qcom: lemans-evk: Enable Adreno 663 GPU Enable GPU for lemans-evk platform and provide path for zap shader. Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251230-a663-gpu-support-v9-3-186722e25387@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index b40fa203e4a2..28bf152f5fa8 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -454,6 +454,14 @@ status = "okay"; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sa8775p/a663_zap.mbn"; +}; + &i2c18 { status = "okay"; From 247b55ddf76ee65b1a63e5c834341a07996de07d Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 30 Dec 2025 18:03:28 +0530 Subject: [PATCH 212/757] arm64: dts: qcom: lemans-ride: Enable Adreno 663 GPU Enable GPU on both qcs9100-ride platforms and provide the path for zap shader. Reviewed-by: Dmitry Baryshkov Signed-off-by: Akhil P Oommen Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251230-a663-gpu-support-v9-4-186722e25387@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index c69aa2f41ce2..8fb7d1fc6d56 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -436,6 +436,14 @@ }; }; +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sa8775p/a663_zap.mbn"; +}; + &i2c11 { clock-frequency = <400000>; status = "okay"; From 29e87dc07d705bd92d57fff77703ca272779e6a0 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 22 Dec 2025 20:05:37 +0100 Subject: [PATCH 213/757] arm64: dts: qcom: sdm845-oneplus: Update firmware paths Conform to the new firmware path scheme. Includes cosmetic cleanups. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251222-oneplus6-new-fw-path-v1-1-a2d366f9eb89@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 23 ++++++++++++------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index db6dd04c51bb..f1c63794db97 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -181,8 +181,9 @@ }; &adsp_pas { + firmware-name = "qcom/sdm845/OnePlus/enchilada/adsp.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/oneplus6/adsp.mbn"; }; &apps_rsc { @@ -353,8 +354,9 @@ }; &cdsp_pas { + firmware-name = "qcom/sdm845/OnePlus/enchilada/cdsp.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/oneplus6/cdsp.mbn"; }; &gcc { @@ -370,7 +372,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/oneplus6/a630_zap.mbn"; + firmware-name = "qcom/sdm845/OnePlus/enchilada/a630_zap.mbn"; }; &i2c10 { @@ -422,7 +424,8 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/oneplus6/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/OnePlus/enchilada/ipa_fws.mbn"; + status = "okay"; }; @@ -474,8 +477,10 @@ /* Modem/wifi */ &mss_pil { + firmware-name = "qcom/sdm845/OnePlus/enchilada/mba.mbn", + "qcom/sdm845/OnePlus/enchilada/modem.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/oneplus6/mba.mbn", "qcom/sdm845/oneplus6/modem.mbn"; }; &pm8998_gpios { @@ -593,7 +598,8 @@ }; &slpi_pas { - firmware-name = "qcom/sdm845/oneplus6/slpi.mbn"; + firmware-name = "qcom/sdm845/OnePlus/enchilada/slpi.mbn"; + status = "okay"; }; @@ -744,7 +750,7 @@ * This path is relative to the qca/ * subdir under lib/firmware. */ - firmware-name = "oneplus6/crnv21.bin"; + firmware-name = "OnePlus/enchilada/crnv21.bin"; vddio-supply = <&vreg_s4a_1p8>; vddxo-supply = <&vreg_l7a_1p8>; @@ -906,8 +912,9 @@ }; &venus { + firmware-name = "qcom/sdm845/OnePlus/enchilada/venus.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/oneplus6/venus.mbn"; }; &wcd9340 { From 5eac5422c0c0a8a14800405b658e99beaacf90de Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 22 Dec 2025 20:05:38 +0100 Subject: [PATCH 214/757] arm64: dts: qcom: sdm845-axolotl: Update firmware paths Conform to the new firmware path scheme. Includes cosmetic cleanups. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251222-oneplus6-new-fw-path-v1-2-a2d366f9eb89@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-shift-axolotl.dts | 22 ++++++++++++------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index ddc2b3ca3bc5..a35c120361c1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -108,8 +108,9 @@ }; &adsp_pas { + firmware-name = "qcom/sdm845/SHIFT/axolotl/adsp.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/axolotl/adsp.mbn"; }; &apps_rsc { @@ -409,8 +410,9 @@ }; &cdsp_pas { + firmware-name = "qcom/sdm845/SHIFT/axolotl/cdsp.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/axolotl/cdsp.mbn"; }; &gcc { @@ -426,7 +428,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; + firmware-name = "qcom/sdm845/SHIFT/axolotl/a630_zap.mbn"; }; &i2c5 { @@ -458,7 +460,8 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/SHIFT/axolotl/ipa_fws.mbn"; + status = "okay"; }; @@ -502,8 +505,9 @@ }; &mss_pil { + firmware-name = "qcom/sdm845/SHIFT/axolotl/mba.mbn", "qcom/sdm845/SHIFT/axolotl/modem.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn"; }; &pm8998_gpios { @@ -597,7 +601,8 @@ }; &slpi_pas { - firmware-name = "qcom/sdm845/axolotl/slpi.mbn"; + firmware-name = "qcom/sdm845/SHIFT/axolotl/slpi.mbn"; + status = "okay"; }; @@ -673,7 +678,7 @@ * This path is relative to the qca/ * subdir under lib/firmware. */ - firmware-name = "axolotl/crnv21.bin"; + firmware-name = "SHIFT/axolotl/crnv21.bin"; vddio-supply = <&vreg_s4a_1p8>; vddxo-supply = <&vreg_l7a_1p8>; @@ -727,8 +732,9 @@ }; &venus { + firmware-name = "qcom/sdm845/SHIFT/axolotl/venus.mbn"; + status = "okay"; - firmware-name = "qcom/sdm845/axolotl/venus.mbn"; }; &wifi { From 7e46a9c78880f4a7589bb31f8887ea3edb0596b4 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 22 Dec 2025 20:05:39 +0100 Subject: [PATCH 215/757] arm64: dts: qcom: sdm845-samsung-starqltechn: Update firmware paths Conform to the new firmware path scheme. Includes cosmetic cleanups. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251222-oneplus6-new-fw-path-v1-3-a2d366f9eb89@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-samsung-starqltechn.dts | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts index 5d41a92cfebf..77f5872de6f1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-samsung-starqltechn.dts @@ -254,7 +254,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/starqltechn/a630_zap.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/a630_zap.mbn"; }; &mdss { @@ -699,7 +699,8 @@ }; &adsp_pas { - firmware-name = "qcom/sdm845/starqltechn/adsp.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/adsp.mbn"; + status = "okay"; }; @@ -904,20 +905,22 @@ }; &mss_pil { - firmware-name = "qcom/sdm845/starqltechn/mba.mbn", - "qcom/sdm845/starqltechn/modem.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/mba.mbn", + "qcom/sdm845/Samsung/starqltechn/modem.mbn"; + status = "okay"; }; &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/starqltechn/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/ipa_fws.mbn"; + status = "okay"; }; &slpi_pas { - firmware-name = "qcom/sdm845/starqltechn/slpi.mbn"; + firmware-name = "qcom/sdm845/Samsung/starqltechn/slpi.mbn"; cx-supply = <&slpi_regulator>; status = "okay"; From 86057e01967b8eeb8604904322003de044528e7a Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Mon, 22 Dec 2025 20:05:40 +0100 Subject: [PATCH 216/757] arm64: dts: qcom: sdm845-xiaomi-polaris: Update firmware paths Conform to the new firmware path scheme. Includes cosmetic cleanups. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251222-oneplus6-new-fw-path-v1-4-a2d366f9eb89@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-xiaomi-polaris.dts | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts index 30e88ff010a3..a44d6e776c82 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-polaris.dts @@ -370,7 +370,8 @@ }; &cdsp_pas { - firmware-name = "qcom/sdm845/polaris/cdsp.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/cdsp.mbn"; + status = "okay"; }; @@ -395,7 +396,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/polaris/a630_zap.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/a630_zap.mbn"; }; &ibb { @@ -410,7 +411,8 @@ &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/polaris/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/ipa_fws.mbn"; + status = "okay"; }; @@ -502,7 +504,9 @@ }; &mss_pil { - firmware-name = "qcom/sdm845/polaris/mba.mbn", "qcom/sdm845/polaris/modem.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/mba.mbn", + "qcom/sdm845/Xiaomi/polaris/modem.mbn"; + status = "okay"; }; @@ -623,7 +627,7 @@ compatible = "qcom,wcn3990-bt"; /* This path is relative to the qca/ subdir under lib/firmware. */ - firmware-name = "polaris/crnv21.bin"; + firmware-name = "Xiaomi/polaris/crnv21.bin"; vddio-supply = <&vreg_s4a_1p8>; vddxo-supply = <&vreg_l7a_1p8>; @@ -683,7 +687,8 @@ }; &venus { - firmware-name = "qcom/sdm845/polaris/venus.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/polaris/venus.mbn"; + status = "okay"; }; From 44d1c77a8af492f00d4c36c3641d6386bdc182eb Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 19 Dec 2025 21:44:07 +0530 Subject: [PATCH 217/757] arm64: dts: qcom: hamoa-iot-evk: Add vbus regulator support for Type-A ports The Multiport controller on Hamoa EVK platform is connected to Two Type-A ports. VBUS for each of these ports are provided by a TPS2559QWDRCTQ1 regulator, controlled from PMIC GPIOs. Add the necessary regulators and GPIO configuration to power these. Implement connector nodes to embed the vbus supply within them. Since there is no entity currently that can read vbus supply from a Type-A connector and control it, mark the supplies as always on. Reviewed-by: Konrad Dybcio Signed-off-by: Krishna Kurapati Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251219161407.2075701-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 36dd6599402b..88e3e7bed998 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "hamoa-iot-som.dtsi" +#include / { model = "Qualcomm Technologies, Inc. Hamoa IoT EVK"; @@ -48,6 +49,32 @@ stdout-path = "serial0:115200n8"; }; + connector3 { + compatible = "usb-a-connector"; + label = "USB-3-Type-A"; + power-role = "source"; + + vbus-supply = <®ulator_usb3_vbus>; + + port { + connector_3_in: endpoint { + }; + }; + }; + + connector6 { + compatible = "usb-a-connector"; + label = "USB-6-Type-A"; + power-role = "source"; + + vbus-supply = <®ulator_usb6_vbus>; + + port { + connector_4_in: endpoint { + }; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -344,6 +371,26 @@ regulator-boot-on; }; + regulator_usb3_vbus: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB3_VBUS"; + gpio = <&pm8550ve_9_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb3_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + + regulator_usb6_vbus: regulator-usb6-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB6_VBUS"; + gpio = <&pm8550ve_9_gpios 5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb6_en>; + pinctrl-names = "default"; + enable-active-high; + regulator-always-on; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -877,6 +924,22 @@ input-disable; output-enable; }; + + usb3_en: usb3-en-state { + pins = "gpio4"; + function = "normal"; + qcom,drive-strength = ; + output-enable; + power-source = <0>; + }; + + usb6_en: usb6-en-state { + pins = "gpio5"; + function = "normal"; + qcom,drive-strength = ; + output-enable; + power-source = <0>; + }; }; &pmc8380_5_gpios { From 8325294ca9688398ea55843f03ebd1479b9d2334 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20de=20Bretagne?= Date: Sat, 20 Dec 2025 16:26:29 +0100 Subject: [PATCH 218/757] dt-bindings: arm: qcom: Document Microsoft Surface Pro 11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the compatibles for the Qualcomm-based Microsoft Surface Pro 11, using its Denali codename. The LCD models are using the Qualcomm Snapdragon X1 Plus (X1P64100), the OLED ones are using the Qualcomm Snapdragon X1 Elite (X1E80100). Due to the difference in how the built-in panel is being handled between the OLED variant and LCD one, it is required to have two separate DTBs, so document the compatible string for both variants. Signed-off-by: Jérôme de Bretagne Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251220-surface-sp11-for-next-v6-1-81f7451edb77@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 4eb0a7a9ee4a..c0648c7b8109 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1080,6 +1080,12 @@ properties: - const: qcom,x1e78100 - const: qcom,x1e80100 + - items: + - const: microsoft,denali-lcd + - const: microsoft,denali + - const: qcom,x1p64100 + - const: qcom,x1e80100 + - items: - enum: - asus,vivobook-s15 @@ -1102,6 +1108,11 @@ properties: - const: qcom,hamoa-iot-som - const: qcom,x1e80100 + - items: + - const: microsoft,denali-oled + - const: microsoft,denali + - const: qcom,x1e80100 + - items: - enum: - asus,zenbook-a14-ux3407qa-lcd From 0d72ccaa1e840b4c8723a929b2febbedcf5f80cd Mon Sep 17 00:00:00 2001 From: Dale Whinham Date: Sat, 20 Dec 2025 16:26:32 +0100 Subject: [PATCH 219/757] arm64: dts: qcom: Add support for X1-based Surface Pro 11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add device trees for the Qualcomm X1E and X1P-based Microsoft Surface Pro 11 machines (codenamed 'Denali'). This device is very similar to the Surface Laptop 7 ('Romulus'). Use a similar strategy to x1-asus-zenbook-a14.dtsi so that we can create x1e and x1p-specific flavors of the device tree without too much code duplication. Hardware support is similar to other X1 machines. The most notable missing features are: - Touchscreen and pen - Cameras (and status LEDs) Signed-off-by: Dale Whinham Signed-off-by: Jérôme de Bretagne Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251220-surface-sp11-for-next-v6-4-81f7451edb77@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/x1-microsoft-denali.dtsi | 1322 +++++++++++++++++ .../qcom/x1e80100-microsoft-denali-oled.dts | 19 + .../dts/qcom/x1p64100-microsoft-denali.dts | 15 + 4 files changed, 1358 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts create mode 100644 arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 02b8e4d761a1..565e9b317a37 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -370,3 +370,5 @@ x1p42100-hp-omnibook-x14-el2-dtbs := x1p42100-hp-omnibook-x14.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-hp-omnibook-x14.dtb x1p42100-hp-omnibook-x14-el2.dtb x1p42100-lenovo-thinkbook-16-el2-dtbs := x1p42100-lenovo-thinkbook-16.dtb x1-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += x1p42100-lenovo-thinkbook-16.dtb x1p42100-lenovo-thinkbook-16-el2.dtb +x1p64100-microsoft-denali-el2-dtbs := x1p64100-microsoft-denali.dtb x1-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) += x1p64100-microsoft-denali.dtb x1p64100-microsoft-denali-el2.dtb diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi new file mode 100644 index 000000000000..d77be02848b5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi @@ -0,0 +1,1322 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2025 Dale Whinham + */ + +#include +#include +#include +#include + +#include "hamoa-pmics.dtsi" + +/ { + aliases { + serial0 = &uart2; + serial1 = &uart14; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&hall_int_n_default>; + pinctrl-names = "default"; + + switch-lid { + gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-source; + wakeup-event-action = ; + }; + }; + + pmic-glink { + compatible = "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>; + + /* Left-side bottom port */ + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint = <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; + }; + }; + }; + }; + + /* Left-side top port */ + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint = <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible = "shared-dma-pool"; + size = <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_EDP_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&rtmr1_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_wcn_3p3: regulator-wcn-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 214 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wcn_sw_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_wcn_0p95: regulator-wcn-0p95 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_0P95"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + vreg_wcn_1p9: regulator-wcn-1p9 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_WCN_1P9"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + vin-supply = <&vreg_wcn_3p3>; + }; + + sound { + compatible = "qcom,x1e80100-sndcard"; + model = "X1E80100-Microsoft-Surface-Pro-11"; + audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT", + "SpkrRight IN", "WSA WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb"; + + wsa-dai-link { + link-name = "WSA Playback"; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, + <&swr0 0>, <&lpass_wsamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + + codec { + sound-dai = <&lpass_vamacro 0>; + }; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; + + wcn7850-pmu { + compatible = "qcom,wcn7850-pmu"; + + vdd-supply = <&vreg_wcn_0p95>; + vddio-supply = <&vreg_l15b_1p8>; + vddaon-supply = <&vreg_wcn_0p95>; + vdddig-supply = <&vreg_wcn_0p95>; + vddrfa1p2-supply = <&vreg_wcn_1p9>; + vddrfa1p8-supply = <&vreg_wcn_1p9>; + + wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; + bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&wcn_wlan_bt_en>; + pinctrl-names = "default"; + + regulators { + vreg_pmu_rfa_cmn: ldo0 { + regulator-name = "vreg_pmu_rfa_cmn"; + }; + + vreg_pmu_aon_0p59: ldo1 { + regulator-name = "vreg_pmu_aon_0p59"; + }; + + vreg_pmu_wlcx_0p8: ldo2 { + regulator-name = "vreg_pmu_wlcx_0p8"; + }; + + vreg_pmu_wlmx_0p85: ldo3 { + regulator-name = "vreg_pmu_wlmx_0p85"; + }; + + vreg_pmu_btcmx_0p85: ldo4 { + regulator-name = "vreg_pmu_btcmx_0p85"; + }; + + vreg_pmu_rfa_0p8: ldo5 { + regulator-name = "vreg_pmu_rfa_0p8"; + }; + + vreg_pmu_rfa_1p2: ldo6 { + regulator-name = "vreg_pmu_rfa_1p2"; + }; + + vreg_pmu_rfa_1p8: ldo7 { + regulator-name = "vreg_pmu_rfa_1p8"; + }; + + vreg_pmu_pcie_0p9: ldo8 { + regulator-name = "vreg_pmu_pcie_0p9"; + }; + + vreg_pmu_pcie_1p8: ldo9 { + regulator-name = "vreg_pmu_pcie_1p8"; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob2>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l12-supply = <&vreg_s5j_1p2>; + vdd-l15-supply = <&vreg_s4c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name = "vreg_l1b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name = "vreg_l4b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name = "vreg_l8b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name = "vreg_l10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name = "vreg_l14b_3p0"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name = "vreg_s4c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name = "vreg_l2c_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name = "vreg_l3c_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "d"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s4c_1p8>; + vdd-s1-supply = <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name = "vreg_l1d_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name = "vreg_l2d_0p9"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name = "vreg_l3d_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + regulators-3 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-l2-supply = <&vreg_s1f_0p7>; + vdd-l3-supply = <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + regulators-4 { + compatible = "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id = "f"; + + vdd-l1-supply = <&vreg_s5j_1p2>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s5j_1p2>; + vdd-s1-supply = <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name = "vreg_s1f_0p7"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + }; + + regulators-6 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "i"; + + vdd-l1-supply = <&vreg_s4c_1p8>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name = "vreg_s1i_0p9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name = "vreg_s2i_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name = "vreg_l1i_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name = "vreg_l2i_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name = "vreg_l3i_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; + + regulators-7 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id = "j"; + + vdd-l1-supply = <&vreg_s1f_0p7>; + vdd-l2-supply = <&vreg_s5j_1p2>; + vdd-l3-supply = <&vreg_s1f_0p7>; + vdd-s5-supply = <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name = "vreg_s5j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name = "vreg_l1j_0p8"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name = "vreg_l2j_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1256000>; + regulator-initial-mode = ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name = "vreg_l3j_0p8"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + }; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_microcode_mem>; + firmware-name = "qcom/x1e80100/microsoft/qcdxkmsuc8380.mbn"; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + + status = "okay"; + + /* Something @39, @3e, @44 */ +}; + +&i2c3 { + clock-frequency = <400000>; + + status = "okay"; + + /* Left-side bottom port */ + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + + status = "okay"; + + /* Something @12, @14, @16, @18, @1a */ +}; + +&i2c7 { + clock-frequency = <400000>; + + status = "okay"; + + /* Left-side top port */ + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; +}; + +&lpass_vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>; + pinctrl-names = "default"; + + vdd-micb-supply = <&vreg_l1b_1p8>; + qcom,dmic-sample-rate = <4800000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp3 { + compatible = "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status = "okay"; + + aux-bus { + panel: panel { + compatible = "edp-panel"; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_3p3>; + + pinctrl-0 = <&edp_bl_en>; + pinctrl-names = "default"; + + port { + edp_panel_in: endpoint { + remote-endpoint = <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg = <1>; + + mdss_dp3_out: endpoint { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pcie4 { + status = "okay"; +}; + +&pcie4_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + +&pcie6a { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; + + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie6a_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie6a_phy { + vdda-phy-supply = <&vreg_l1d_0p8>; + vdda-pll-supply = <&vreg_l2j_1p2>; + + status = "okay"; +}; + +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; + + rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; +}; + +&pm8550ve_9_gpios { + rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; +}; + +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; /* 1.8V */ + input-disable; + output-enable; + }; +}; + +&pmc8380_5_gpios { + rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + }; +}; + +&qupv3_0 { + status = "okay"; +}; + +&qupv3_1 { + status = "okay"; +}; + +&qupv3_2 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/x1e80100/microsoft/Denali/qcadsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/x1e80100/microsoft/Denali/qccdsp8380.mbn", + "qcom/x1e80100/microsoft/Denali/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&smb2360_0 { + status = "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l2b_3p0>; +}; + +&smb2360_1 { + status = "okay"; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status = "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply = <&vreg_l3d_1p8>; + vdd3-supply = <&vreg_l8b_3p0>; +}; + +&swr0 { + status = "okay"; + + pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names = "default"; + + /* WSA8845, Left Speaker */ + left_spkr: speaker@0,0 { + compatible = "sdw20217020400"; + reg = <0 0>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <1 2 3 7 10 13>; + }; + + /* WSA8845, Right Speaker */ + right_spkr: speaker@0,1 { + compatible = "sdw20217020400"; + reg = <0 1>; + reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + vdd-1p8-supply = <&vreg_l15b_1p8>; + vdd-io-supply = <&vreg_l12b_1p2>; + qcom,port-mapping = <4 5 6 7 11 13>; + }; +}; + +&tlmm { + gpio-reserved-ranges = <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + hall_int_n_default: hall-int-n-state { + pins = "gpio2"; + function = "gpio"; + bias-disable; + }; + + nvme_reg_en: nvme-reg-en-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + edp_reg_en: edp-reg-en-state { + pins = "gpio70"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + ssam_state: ssam-state-state { + pins = "gpio91"; + function = "gpio"; + bias-disable; + }; + + wcn_wlan_bt_en: wcn-wlan-bt-en-state { + pins = "gpio116", "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie6a_default: pcie6a-default-state { + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + clkreq-n-pins { + pins = "gpio153"; + function = "pcie6a_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_sw_en: wcn-sw-en-state { + pins = "gpio214"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cam_indicator_en: cam-indicator-en-state { + pins = "gpio225"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart2 { + status = "okay"; + + embedded-controller { + compatible = "microsoft,surface-sam"; + + interrupts-extended = <&tlmm 91 IRQ_TYPE_EDGE_RISING>; + + current-speed = <4000000>; + + pinctrl-0 = <&ssam_state>; + pinctrl-names = "default"; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + max-speed = <3200000>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + }; +}; + +&usb_1_ss0_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_0_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l1j_0p8>; + + status = "okay"; +}; + +&usb_1_ss0 { + status = "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint = <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint = <&retimer_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply = <&vreg_l3j_0p8>; + vdda12-supply = <&vreg_l2j_1p2>; + + phys = <&smb2360_1_eusb2_repeater>; + + status = "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + status = "okay"; +}; + +&usb_1_ss1 { + status = "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint = <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint = <&retimer_ss1_ss_in>; +}; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts new file mode 100644 index 000000000000..07ce43ccf394 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-denali-oled.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Dale Whinham + */ + +/dts-v1/; + +#include "hamoa.dtsi" +#include "x1-microsoft-denali.dtsi" + +/ { + model = "Microsoft Surface Pro 11th Edition (OLED)"; + compatible = "microsoft,denali-oled", "microsoft,denali", + "qcom,x1e80100"; +}; + +&panel { + compatible = "samsung,atna30dw01", "samsung,atna33xc20"; +}; diff --git a/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts b/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts new file mode 100644 index 000000000000..d96202e2afc6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1p64100-microsoft-denali.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Dale Whinham + */ + +/dts-v1/; + +#include "hamoa.dtsi" +#include "x1-microsoft-denali.dtsi" + +/ { + model = "Microsoft Surface Pro 11th Edition (LCD)"; + compatible = "microsoft,denali-lcd", "microsoft,denali", + "qcom,x1p64100", "qcom,x1e80100"; +}; From 70101cb09c205e260df918ef367d9fe5098c464f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:00 +0100 Subject: [PATCH 220/757] arm64: dts: qcom: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' and before '{' characters. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251223152559.155703-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kaanapali.dtsi | 226 ++++++++++++------------ arch/arm64/boot/dts/qcom/lemans.dtsi | 2 +- 2 files changed, 114 insertions(+), 114 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi index 51f8b3e0749c..9ef57ad0ca71 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi @@ -1100,119 +1100,119 @@ compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; - interrupts =, - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; #iommu-cells = <2>; #global-interrupts = <1>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 14d9f31e7086..a89ad87d998a 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -5048,7 +5048,7 @@ port@1 { reg = <1>; - mdss0_dsi0_out: endpoint{ }; + mdss0_dsi0_out: endpoint { }; }; }; From 3d9bebf804b72841c838ca77cf5b783a89b68e85 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:01 +0100 Subject: [PATCH 221/757] arm64: dts: qcom: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251223152559.155703-5-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 468ec781487b..2b86a6baae01 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -929,7 +929,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@240c { + gpu_speed_bin: gpu-speed-bin@240c { reg = <0x240c 0x1>; bits = <0 8>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index b8a8dcbdfbe3..746e9deba526 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -634,7 +634,7 @@ #address-cells = <1>; #size-cells = <1>; - gpu_speed_bin: gpu_speed_bin@1a2 { + gpu_speed_bin: gpu-speed-bin@1a2 { reg = <0x1a2 0x2>; bits = <5 8>; }; From 4df4b572802cac0b0d46ef15379d7319366f3038 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:26:02 +0100 Subject: [PATCH 222/757] arm64: dts: qcom: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251223152559.155703-6-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/lemans.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi | 2 +- .../boot/dts/qcom/msm8994-huawei-angler-rev-101.dts | 2 +- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm630.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/sm6115.dtsi | 4 ++-- .../boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 +- 11 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 21ab6ef61520..f7d71793bc77 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3164,7 +3164,7 @@ mmss_noc: interconnect@1780000 { compatible = "qcom,x1e80100-mmss-noc"; - reg = <0 0x01780000 0 0x5B800>; + reg = <0 0x01780000 0 0x5b800>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -4165,7 +4165,7 @@ nsp_noc: interconnect@320c0000 { compatible = "qcom,x1e80100-nsp-noc"; - reg = <0 0x320C0000 0 0xe080>; + reg = <0 0x320c0000 0 0xe080>; qcom,bcm-voters = <&apps_bcm_voter>; @@ -4676,7 +4676,7 @@ lpass_lpicx_noc: interconnect@7430000 { compatible = "qcom,x1e80100-lpass-lpicx-noc"; - reg = <0 0x07430000 0 0x3A200>; + reg = <0 0x07430000 0 0x3a200>; qcom,bcm-voters = <&apps_bcm_voter>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index a89ad87d998a..148dc65ede3d 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -7142,7 +7142,7 @@ remoteproc_cdsp1: remoteproc@2a300000 { compatible = "qcom,sa8775p-cdsp1-pas"; - reg = <0x0 0x2A300000 0x0 0x10000>; + reg = <0x0 0x2a300000 0x0 0x10000>; interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index b8f2a01bcb96..1e718accf8f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -24,7 +24,7 @@ chassis-type = "handset"; qcom,msm-id = <251 0>, <252 0>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>; /* Bullhead firmware doesn't support PSCI */ /delete-node/ psci; diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 1aca11daf83c..7775532f154e 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -16,7 +16,7 @@ chassis-type = "handset"; /* required for bootloader to select correct board */ qcom,msm-id = <207 0x20000>; - qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; + qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>; qcom,board-id = <8026 0>; aliases { diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 846e5e5899aa..cdfe40da5d33 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1592,7 +1592,7 @@ gem_noc: interconnect@19100000 { compatible = "qcom,qdu1000-gem-noc"; - reg = <0x0 0x19100000 0x0 0xB8080>; + reg = <0x0 0x19100000 0x0 0xb8080>; qcom,bcm-voters = <&apps_bcm_voter>; #interconnect-cells = <2>; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 5334adebf278..4b9cd9aea0be 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3041,8 +3041,8 @@ qcom,dout-ports = <5>; qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; - qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; - qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 8b1a45a4e56e..90314cb49177 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -262,7 +262,7 @@ pwr_cluster_sleep_0: cluster-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "pwr-cluster-dynamic-retention"; - arm,psci-suspend-param = <0x400000F2>; + arm,psci-suspend-param = <0x400000f2>; entry-latency-us = <284>; exit-latency-us = <384>; min-residency-us = <9987>; @@ -272,7 +272,7 @@ pwr_cluster_sleep_1: cluster-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "pwr-cluster-retention"; - arm,psci-suspend-param = <0x400000F3>; + arm,psci-suspend-param = <0x400000f3>; entry-latency-us = <338>; exit-latency-us = <423>; min-residency-us = <9987>; @@ -282,7 +282,7 @@ pwr_cluster_sleep_2: cluster-sleep-0-2 { compatible = "arm,idle-state"; idle-state-name = "pwr-cluster-retention"; - arm,psci-suspend-param = <0x400000F4>; + arm,psci-suspend-param = <0x400000f4>; entry-latency-us = <515>; exit-latency-us = <1821>; min-residency-us = <9987>; @@ -292,7 +292,7 @@ perf_cluster_sleep_0: cluster-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "perf-cluster-dynamic-retention"; - arm,psci-suspend-param = <0x400000F2>; + arm,psci-suspend-param = <0x400000f2>; entry-latency-us = <272>; exit-latency-us = <329>; min-residency-us = <9987>; @@ -302,7 +302,7 @@ perf_cluster_sleep_1: cluster-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "perf-cluster-retention"; - arm,psci-suspend-param = <0x400000F3>; + arm,psci-suspend-param = <0x400000f3>; entry-latency-us = <332>; exit-latency-us = <368>; min-residency-us = <9987>; @@ -312,7 +312,7 @@ perf_cluster_sleep_2: cluster-sleep-1-2 { compatible = "arm,idle-state"; idle-state-name = "perf-cluster-retention"; - arm,psci-suspend-param = <0x400000F4>; + arm,psci-suspend-param = <0x400000f4>; entry-latency-us = <545>; exit-latency-us = <1609>; min-residency-us = <9987>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 5e2032c26ea3..88513b513871 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -870,7 +870,7 @@ <&apps_smmu 0x94 0x11>, <&apps_smmu 0x96 0x11>, <&apps_smmu 0x98 0x1>, - <&apps_smmu 0x9F 0>; + <&apps_smmu 0x9f 0>; }; crypto: crypto@1b3a000 { @@ -885,7 +885,7 @@ <&apps_smmu 0x94 0x11>, <&apps_smmu 0x96 0x11>, <&apps_smmu 0x98 0x1>, - <&apps_smmu 0x9F 0>; + <&apps_smmu 0x9f 0>; }; usb_qmpphy: phy@1615000 { diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts index 8848043f95f2..6e2bbf4f060a 100644 --- a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -14,7 +14,7 @@ compatible = "sony,pdx213", "qcom,sm6350"; chassis-type = "handset"; qcom,msm-id = <434 0x10000>, <459 0x10000>; - qcom,board-id = <0x1000B 0>; + qcom,board-id = <0x1000b 0>; chosen { #address-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index e3ec99972a28..d36a3d214db4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2381,7 +2381,7 @@ reg = <0x0 0x03100000 0x0 0x300000>, <0x0 0x03500000 0x0 0x300000>, <0x0 0x03900000 0x0 0x300000>, - <0x0 0x03D00000 0x0 0x300000>; + <0x0 0x03d00000 0x0 0x300000>; reg-names = "west", "east", "north", "south"; interrupts = ; gpio-ranges = <&tlmm 0 0 176>; diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3f0b57f428bb..c0734f6185e1 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3471,7 +3471,7 @@ <0x0 0x40000f20 0x0 0xa8>, <0x0 0x40001000 0x0 0x1000>, <0x0 0x40100000 0x0 0x100000>, - <0x0 0x01C03000 0x0 0x1000>; + <0x0 0x01c03000 0x0 0x1000>; reg-names = "parf", "dbi", "elbi", From 6710f10459c159da45e227f50b8db9c33ee906b2 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 17 Nov 2025 14:49:32 +0800 Subject: [PATCH 223/757] arm64: dts: qcom: qcs8300: add display dt nodes for MDSS, DPU, DisplayPort and eDP PHY Add devicetree changes to enable MDSS display-subsystem, display-controller(DPU), DisplayPort controller and eDP PHY for Qualcomm QCS8300 platform. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/r/20251117-dts_qcs8300-v7-1-bf42d39e7828@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 220 ++++++++++++++++++++++++++- 1 file changed, 219 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 2b86a6baae01..c389135f86ce 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4789,6 +4789,222 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,qcs8300-mdss"; + reg = <0x0 0x0ae00000 0x0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1000 0x402>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; + reg = <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x2008>; + reg-names = "mdp", "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz = /bits/ 64 <575000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo_l1>; + }; + }; + }; + + mdss_dp0_phy: phy@aec2a00 { + compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; + + reg = <0x0 0x0aec2a00 0x0 0x19c>, + <0x0 0x0aec2200 0x0 0xec>, + <0x0 0x0aec2600 0x0 0xec>, + <0x0 0x0aec2000 0x0 0x1c8>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + power-domains = <&rpmhpd RPMHPD_MX>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; + + reg = <0x0 0x0af54000 0x0 0x200>, + <0x0 0x0af54200 0x0 0x200>, + <0x0 0x0af55000 0x0 0xc00>, + <0x0 0x0af56000 0x0 0x09c>, + <0x0 0x0af57000 0x0 0x09c>, + <0x0 0x0af58000 0x0 0x09c>, + <0x0 0x0af59000 0x0 0x09c>, + <0x0 0x0af5a000 0x0 0x23c>, + <0x0 0x0af5b000 0x0 0x23c>; + + interrupts-extended = <&mdss 12>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; + assigned-clock-parents = <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>, + <&mdss_dp0_phy 1>; + phys = <&mdss_dp0_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sa8775p-dispcc0"; reg = <0x0 0x0af00000 0x0 0x20000>; @@ -4796,7 +5012,9 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <0>, <0>, <0>, + <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, + <0>, <0>, <0>, <0>, <0>, <0>; power-domains = <&rpmhpd RPMHPD_MMCX>; #clock-cells = <1>; From be4a8c25ae3a367eab0ae91ded89a96ae9627b72 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 17 Nov 2025 14:49:33 +0800 Subject: [PATCH 224/757] arm64: dts: qcom: qcs8300-ride: Enable Display Port Enable DPTX0 along with their corresponding PHYs for qcs8300-ride platform. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/r/20251117-dts_qcs8300-v7-2-bf42d39e7828@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 9bcb869dd270..4a8ac26846c6 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -24,6 +24,18 @@ stdout-path = "serial0:115200n8"; }; + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + regulator-usb2-vbus { compatible = "regulator-fixed"; regulator-name = "USB2_VBUS"; @@ -317,6 +329,30 @@ status = "okay"; }; +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + pinctrl-0 = <&dp_hot_plug_det>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + remote-endpoint = <&dp0_connector_in>; +}; + +&mdss_dp0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l4a>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -377,6 +413,12 @@ bias-pull-up; }; }; + + dp_hot_plug_det: dp-hot-plug-det-state { + pins = "gpio94"; + function = "edp0_hot"; + bias-disable; + }; }; &uart7 { From ff7cb4613b490cce4e213961b91f28b744d82ee1 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 22 Dec 2025 04:38:31 +0200 Subject: [PATCH 225/757] arm64: dts: qcom: sm8550-qrd: rename image sensor supply properties At first voltage supply properties of Samsung S5K3M5 image sensor got names following a pad name convention for Omnivision image sensors. Now the property names were corrected in the sensor dt bindings documentation, and it should be updated in the SM8550-QRD board dts file. Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Signed-off-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20251222023834.3284370-2-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 05c98fe2c25b..7abd862f3f4d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -748,9 +748,9 @@ pinctrl-0 = <&cam3_default>; pinctrl-names = "default"; afvdd-supply = <&vreg_l7n_2p96>; - avdd-supply = <&vreg_l4m_2p8>; - dovdd-supply = <&vreg_l5n_1p8>; - dvdd-supply = <&vreg_l2m_1p056>; + vdda-supply = <&vreg_l4m_2p8>; + vddd-supply = <&vreg_l2m_1p056>; + vddio-supply = <&vreg_l5n_1p8>; port { cam_tele: endpoint { From 8cadf9f0bbfcccc639b412b21d347108eddbb58d Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 22 Dec 2025 04:38:32 +0200 Subject: [PATCH 226/757] arm64: dts: qcom: sm8550-qrd: remove data-lanes property of image sensor Samsung S5K3M5 image sensor supports only 4-lane MIPI CSI-2 interface, which makes the sensor data-lanes property redundant, and it can be safely removed from the board dts file. Noteworthy that the property value is incorrect, because conventionally lanes enumeration of image sensors starts from index 1. Reviewed-by: Neil Armstrong Signed-off-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20251222023834.3284370-3-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 7abd862f3f4d..3d35a9c6fdb0 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -755,7 +755,6 @@ port { cam_tele: endpoint { link-frequencies = /bits/ 64 <602500000>; - data-lanes = <0 1 2 3>; remote-endpoint = <&csiphy3_ep>; }; }; From 4438d377f6d8bcaefe645dd436ab8f8617d815ec Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 22 Dec 2025 04:38:33 +0200 Subject: [PATCH 227/757] arm64: dts: qcom: sm8550-hdk-rear-camera-card: rename supply properties At first voltage supply properties of Samsung S5K3M5 image sensor got names following a pad name convention for Omnivision image sensors. Now the property names were corrected in the sensor dt bindings documentation, and it should be updated in the SM8550-HDK with the Rear Camera Card board dts file. Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong Signed-off-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20251222023834.3284370-4-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso b/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso index 66bec0fef766..e80de190eef9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso @@ -52,9 +52,9 @@ pinctrl-0 = <&cam3_default>; pinctrl-names = "default"; afvdd-supply = <&vreg_l7n_2p96>; - avdd-supply = <&vreg_l4m_2p8>; - dovdd-supply = <&vreg_l5n_1p8>; - dvdd-supply = <&vreg_l2m_1p056>; + vdda-supply = <&vreg_l4m_2p8>; + vddd-supply = <&vreg_l2m_1p056>; + vddio-supply = <&vreg_l5n_1p8>; port { cam_tele: endpoint { From 9494917da576038d754fbecd15b1f1bcd7b2e0ea Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 22 Dec 2025 04:38:34 +0200 Subject: [PATCH 228/757] arm64: dts: qcom: sm8550-hdk-rear-camera-card: remove optional property Samsung S5K3M5 image sensor supports only 4-lane MIPI CSI-2 interface, which makes the sensor data-lanes property redundant, and it can be safely removed from the board dts file. Noteworthy that the property value is incorrect, because conventionally lanes enumeration of image sensors starts from index 1. Reviewed-by: Neil Armstrong Signed-off-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20251222023834.3284370-5-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso b/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso index e80de190eef9..21bfba6a1182 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk-rear-camera-card.dtso @@ -59,7 +59,6 @@ port { cam_tele: endpoint { link-frequencies = /bits/ 64 <602500000>; - data-lanes = <0 1 2 3>; remote-endpoint = <&csiphy3_ep>; }; }; From c0d377798d6f6d3efddee5ef7d96b608a071f833 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Sat, 20 Dec 2025 12:38:57 +0100 Subject: [PATCH 229/757] arm64: dts: qcom: x1e80100-vivobook-s15: enable ps8830 retimers The Asus vivobook s15 has two usb type c ports on the left side, these use parade ps8830 retimers like the others, enable them to also enable dp altmode Reviewed-by: Konrad Dybcio Signed-off-by: Maud Spierings Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251220-asus_usbc_dp-v3-1-5e244d420d0f@hotmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e80100-asus-vivobook-s15.dts | 310 +++++++++++++++++- 1 file changed, 302 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index d4df21de0d95..ea8ad67e511f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -69,7 +69,15 @@ reg = <1>; pmic_glink_ss0_ss_in: endpoint { - remote-endpoint = <&usb_1_ss0_qmpphy_out>; + remote-endpoint = <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss0_con_sbu_out>; }; }; }; @@ -98,7 +106,15 @@ reg = <1>; pmic_glink_ss1_ss_in: endpoint { - remote-endpoint = <&usb_1_ss1_qmpphy_out>; + remote-endpoint = <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint = <&retimer_ss1_con_sbu_out>; }; }; }; @@ -147,6 +163,102 @@ regulator-boot-on; }; + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR0_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb0_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + + gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p15_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_1p8_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_RTMR1_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb1_pwr_3p3_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; @@ -506,15 +618,62 @@ &i2c1 { clock-frequency = <400000>; status = "okay"; - - /* PS8830 USB4 Retimer? @ 0x8 */ }; &i2c3 { clock-frequency = <400000>; status = "okay"; - /* PS8830 USB4 Retimer? @ 0x8 */ + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x08>; + + clocks = <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply = <&vreg_rtmr0_1p15>; + vdd33-supply = <&vreg_rtmr0_3p3>; + vdd33-cap-supply = <&vreg_rtmr0_3p3>; + vddar-supply = <&vreg_rtmr0_1p15>; + vddat-supply = <&vreg_rtmr0_1p15>; + vddio-supply = <&vreg_rtmr0_1p8>; + + reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr0_default>; + pinctrl-names = "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint = <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; }; &i2c5 { @@ -583,13 +742,78 @@ clock-frequency = <400000>; status = "okay"; - /* PS8830 USB4 Retimer? @ 0x8 */ + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply = <&vreg_rtmr1_1p15>; + vdd33-supply = <&vreg_rtmr1_3p3>; + vdd33-cap-supply = <&vreg_rtmr1_3p3>; + vddar-supply = <&vreg_rtmr1_1p15>; + vddat-supply = <&vreg_rtmr1_1p15>; + vddio-supply = <&vreg_rtmr1_1p8>; + + reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&rtmr1_default>; + pinctrl-names = "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint = <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint = <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; }; &mdss { status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -683,6 +907,37 @@ status = "okay"; }; +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins = "gpio10"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins = "gpio11"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins = "gpio4"; @@ -695,6 +950,17 @@ }; }; +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins = "gpio8"; + function = "normal"; + power-source = <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &qupv3_0 { status = "okay"; }; @@ -840,12 +1106,40 @@ }; }; + rtmr1_default: rtmr1-reset-n-active-state { + pins = "gpio176"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + tpad_default: tpad-default-state { pins = "gpio3"; function = "gpio"; bias-disable; }; + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins = "gpio188"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins = "gpio175"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins = "gpio186"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + wcn_bt_en: wcn-bt-en-state { pins = "gpio116"; function = "gpio"; @@ -914,7 +1208,7 @@ }; &usb_1_ss0_qmpphy_out { - remote-endpoint = <&pmic_glink_ss0_ss_in>; + remote-endpoint = <&retimer_ss0_ss_in>; }; &usb_1_ss1_hsphy { @@ -946,7 +1240,7 @@ }; &usb_1_ss1_qmpphy_out { - remote-endpoint = <&pmic_glink_ss1_ss_in>; + remote-endpoint = <&retimer_ss1_ss_in>; }; &usb_2 { From 34d76723c41018ef52480ca3849b3ed3afbd8b22 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Sat, 20 Dec 2025 12:38:58 +0100 Subject: [PATCH 230/757] arm64: dts: qcom: x1e80100-vivobook-s15: add HDMI port Enable the HDMI port on left side of the laptop. The display signal is routed through a simple Displayport to HDMI bridge. Reviewed-by: Konrad Dybcio Signed-off-by: Maud Spierings Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251220-asus_usbc_dp-v3-2-5e244d420d0f@hotmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/x1e80100-asus-vivobook-s15.dts | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index ea8ad67e511f..d5794189b98b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -37,6 +37,45 @@ }; }; + hdmi-bridge { + compatible = "parade,ps185hdm"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -814,6 +853,14 @@ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -1047,6 +1094,12 @@ bias-disable; }; + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + kybd_default: kybd-default-state { pins = "gpio67"; function = "gpio"; @@ -1243,6 +1296,34 @@ remote-endpoint = <&retimer_ss1_ss_in>; }; +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; +}; + &usb_2 { status = "okay"; }; From b7415c490d8d75b8dc7500b9c02cf8e5852110e6 Mon Sep 17 00:00:00 2001 From: Maud Spierings Date: Sat, 20 Dec 2025 12:38:59 +0100 Subject: [PATCH 231/757] arm64: dts: qcom: x1e80100-vivobook-s15: enable IRIS Enable IRIS to allow using the hardware-accelerated video codecs. The firmware is not upstream in linux-firmware yet, so users need to copy it from Windows to qcom/x1e80100/ASUSTeK/vivobook-s15/qcvss8380.mbn (just like GPU/ADSP/CDSP firmware). Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Maud Spierings Link: https://lore.kernel.org/r/20251220-asus_usbc_dp-v3-3-5e244d420d0f@hotmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index d5794189b98b..34467b84a2fa 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -833,6 +833,11 @@ }; }; +&iris { + firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcvss8380.mbn"; + status = "okay"; +}; + &mdss { status = "okay"; }; From d12cd85a4ff494bb73e2e8f8af7ed66851241941 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 17 Dec 2025 13:00:52 +0100 Subject: [PATCH 232/757] arm64: dts: qcom: hamoa: Add sound DAI prefixes for DP Sound DAI devices exposing same set of mixers, e.g. each DisplayPort controller, need to add dedicated prefix for these mixers to avoid conflicts and to allow ALSA to properly configure given instance. Suggested-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251217120051.98198-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index f7d71793bc77..120993685776 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5608,6 +5608,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort0"; status = "disabled"; @@ -5696,6 +5697,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort1"; status = "disabled"; @@ -5784,6 +5786,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort2"; status = "disabled"; @@ -5867,6 +5870,7 @@ phy-names = "dp"; #sound-dai-cells = <0>; + sound-name-prefix = "DisplayPort3"; status = "disabled"; From ba439ad9134c8b9ce033056c059cd161d30afec7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 17 Dec 2025 13:00:53 +0100 Subject: [PATCH 233/757] arm64: dts: qcom: x1e78100-t14s: Add audio playback over DisplayPort Add necessary DAI links and DAI name prefixes to enable audio playback over USB/DisplayPort and HDMI. The HDMI port is not yet enabled, but it should carry respective DAI name prefix regardless. Reviewed-by: Abel Vesa Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251217120051.98198-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 80ece9db875a..7aee9a20c6df 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -351,6 +351,54 @@ "VA DMIC1", "VA MIC BIAS1", "TX SWR_INPUT1", "ADC2_OUTPUT"; + displayport-0-dai-link { + link-name = "DisplayPort0 Playback"; + + codec { + sound-dai = <&mdss_dp0>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-1-dai-link { + link-name = "DisplayPort1 Playback"; + + codec { + sound-dai = <&mdss_dp1>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_1>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + displayport-2-dai-link { + link-name = "DisplayPort2 Playback"; + + codec { + sound-dai = <&mdss_dp2>; + }; + + cpu { + sound-dai = <&q6apmbedai DISPLAY_PORT_RX_2>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + wcd-playback-dai-link { link-name = "WCD Playback"; From 094a6bbe84d43f04485d565f8174af66d90eb6a7 Mon Sep 17 00:00:00 2001 From: Erikas Bitovtas Date: Mon, 8 Dec 2025 16:59:20 +0200 Subject: [PATCH 234/757] arm64: dts: qcom: msm8939-asus-z00t: add battery This device tracks remaining battery capacity percentage using voltage mode BMS. This commit enables the pm8916_bms node and adds a battery node to track its capacity. Battery properties were taken from the information printed on the battery itself and downstream device tree for a battery named "nvt+atl_3000mah" [1] [1] https://github.com/Asus-MSM8916/android_kernel_asus_msm8916/blob/10.x/arch/arm/boot/dts/qcom/ASUS_ZE550KL_1936167_3000mAh_3p4COV_VBMS_Final.dtsi Signed-off-by: Erikas Bitovtas Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251208-b4-battery-hall-v3-1-84e2157705a4@gmail.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/msm8939-asus-z00t.dts | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts index ebb548e62e02..d0f0f80dd326 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts @@ -20,6 +20,61 @@ serial0 = &blsp_uart2; }; + battery: battery { + compatible = "simple-battery"; + device-chemistry = "lithium-ion-polymer"; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + energy-full-design-microwatt-hours = <11500000>; + charge-full-design-microamp-hours = <3000000>; + + ocv-capacity-celsius = <(-20) 0 25 40 60>; + ocv-capacity-table-0 = <4378000 100>, <4220000 95>, <4125000 90>, + <4071000 85>, <3977000 80>, <3916000 75>, <3866000 70>, + <3838000 65>, <3822000 60>, <3809000 55>, <3797000 50>, + <3784000 45>, <3771000 40>, <3757000 35>, <3743000 30>, + <3726000 25>, <3707000 20>, <3688000 16>, <3670000 13>, + <3655000 11>, <3648000 10>, <3636000 9>, <3624000 8>, + <3612000 7>, <3592000 6>, <3569000 5>, <3540000 4>, + <3494000 3>, <3418000 2>, <3289000 1>, <3000000 0>; + + ocv-capacity-table-1 = <4378000 100>, <4292000 95>, <4226000 90>, + <4166000 85>, <4109000 80>, <4064000 75>, <3992000 70>, + <3942000 65>, <3898000 60>, <3859000 55>, <3826000 50>, + <3802000 45>, <3788000 40>, <3779000 35>, <3768000 30>, + <3752000 25>, <3732000 20>, <3712000 16>, <3696000 13>, + <3688000 11>, <3684000 10>, <3680000 9>, <3675000 8>, + <3669000 7>, <3658000 6>, <3636000 5>, <3599000 4>, + <3544000 3>, <3466000 2>, <3341000 1>, <3000000 0>; + + ocv-capacity-table-2 = <4372000 100>, <4306000 95>, <4247000 90>, + <4190000 85>, <4134000 80>, <4081000 75>, <4030000 70>, + <3984000 65>, <3930000 60>, <3884000 55>, <3850000 50>, + <3826000 45>, <3804000 40>, <3786000 35>, <3770000 30>, + <3753000 25>, <3734000 20>, <3712000 16>, <3693000 13>, + <3686000 11>, <3684000 10>, <3682000 9>, <3680000 8>, + <3676000 7>, <3668000 6>, <3643000 5>, <3600000 4>, + <3542000 3>, <3462000 2>, <3340000 1>, <3000000 0>; + + ocv-capacity-table-3 = <4365000 100>, <4304000 95>, <4246000 90>, + <4189000 85>, <4133000 80>, <4080000 75>, <4030000 70>, + <3985000 65>, <3933000 60>, <3886000 55>, <3852000 50>, + <3827000 45>, <3806000 40>, <3789000 35>, <3769000 30>, + <3746000 25>, <3726000 20>, <3706000 16>, <3688000 13>, + <3681000 11>, <3678000 10>, <3676000 9>, <3676000 8>, + <3672000 7>, <3660000 6>, <3634000 5>, <3588000 4>, + <3528000 3>, <3448000 2>, <3322000 1>, <3000000 0>; + + ocv-capacity-table-4 = <4358000 100>, <4298000 95>, <4240000 90>, + <4183000 85>, <4128000 80>, <4076000 75>, <4027000 70>, + <3983000 65>, <3935000 60>, <3887000 55>, <3852000 50>, + <3827000 45>, <3806000 40>, <3789000 35>, <3764000 30>, + <3738000 25>, <3715000 20>, <3695000 16>, <3677000 13>, + <3672000 11>, <3669000 10>, <3667000 9>, <3666000 8>, + <3662000 7>, <3652000 6>, <3622000 5>, <3577000 4>, + <3518000 3>, <3440000 2>, <3321000 1>, <3000000 0>; + }; + chosen { stdout-path = "serial0"; }; @@ -135,6 +190,12 @@ reg = <0x0 0x86800000 0x0 0x5500000>; }; +&pm8916_bms { + monitored-battery = <&battery>; + + status = "okay"; +}; + &pm8916_codec { qcom,micbias-lvl = <2800>; qcom,mbhc-vthreshold-low = <75 150 237 450 500>; From 931b763e63b317d65f2555ea396f39bacba35b7d Mon Sep 17 00:00:00 2001 From: Erikas Bitovtas Date: Mon, 8 Dec 2025 16:59:21 +0200 Subject: [PATCH 235/757] arm64: dts: qcom: msm8939-asus-z00t: add hall sensor This device uses ANPEC APX9131 hall sensor. It is a basic GPIO hall sensor for which a generic "gpio-keys" device tree node configuration suffices. Reviewed-by: Konrad Dybcio Signed-off-by: Erikas Bitovtas Link: https://lore.kernel.org/r/20251208-b4-battery-hall-v3-2-84e2157705a4@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts index d0f0f80dd326..ea90b00a2c8a 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-asus-z00t.dts @@ -82,7 +82,7 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-0 = <&gpio_keys_default>; + pinctrl-0 = <&gpio_hall_sensor_default>, <&gpio_keys_default>; pinctrl-names = "default"; button-volume-up { @@ -98,6 +98,15 @@ linux,code = ; debounce-interval = <15>; }; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + debounce-interval = <150>; + }; }; reg_sd_vmmc: regulator-sdcard-vmmc { @@ -301,6 +310,13 @@ bias-pull-up; }; + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + usb_id_default: usb-id-default-state { pins = "gpio110"; function = "gpio"; From 65ce09d2f164a3d91b5802ecd0783aa2c9a208c0 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 11 Dec 2025 00:32:23 +0530 Subject: [PATCH 236/757] dt-bindings: mailbox: qcom: Document SM8750 CPUCP mailbox controller Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm SM8750 SoCs. It is software compatible with X1E80100 CPUCP mailbox controller hence fallback to it. Signed-off-by: Jagadeesh Kona Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251211-sm8750-cpufreq-v1-1-394609e8d624@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 9122c3d2dc30..9d99af46e531 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - qcom,glymur-cpucp-mbox + - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: - qcom,x1e80100-cpucp-mbox From deed369e067b8406714154a6678a3e3d9b1c1131 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 11 Dec 2025 00:32:24 +0530 Subject: [PATCH 237/757] arm64: dts: qcom: SM8750: Enable CPUFreq support Add the cpucp mailbox, sram and SCMI nodes required to enable the CPUFreq support using the SCMI perf protocol on SM8750 SoCs. Signed-off-by: Jagadeesh Kona Reviewed-by: Konrad Dybcio Reviewed-by: Sibi Sankar Reviewed-by: Abel Vesa Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251211-sm8750-cpufreq-v1-2-394609e8d624@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 73 ++++++++++++++++++++++------ 1 file changed, 57 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index c0734f6185e1..260ab4fef6c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -35,8 +35,8 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd0>; - power-domain-names = "psci"; + power-domains = <&cpu_pd0>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; l2_0: l2-cache { compatible = "cache"; @@ -51,8 +51,8 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd1>; - power-domain-names = "psci"; + power-domains = <&cpu_pd1>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu2: cpu@200 { @@ -61,8 +61,8 @@ reg = <0x0 0x200>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd2>; - power-domain-names = "psci"; + power-domains = <&cpu_pd2>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu3: cpu@300 { @@ -71,8 +71,8 @@ reg = <0x0 0x300>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd3>; - power-domain-names = "psci"; + power-domains = <&cpu_pd3>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu4: cpu@400 { @@ -81,8 +81,8 @@ reg = <0x0 0x400>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd4>; - power-domain-names = "psci"; + power-domains = <&cpu_pd4>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu5: cpu@500 { @@ -91,8 +91,8 @@ reg = <0x0 0x500>; enable-method = "psci"; next-level-cache = <&l2_0>; - power-domains = <&cpu_pd5>; - power-domain-names = "psci"; + power-domains = <&cpu_pd5>, <&scmi_dvfs 0>; + power-domain-names = "psci", "perf"; }; cpu6: cpu@10000 { @@ -101,8 +101,8 @@ reg = <0x0 0x10000>; enable-method = "psci"; next-level-cache = <&l2_1>; - power-domains = <&cpu_pd6>; - power-domain-names = "psci"; + power-domains = <&cpu_pd6>, <&scmi_dvfs 1>; + power-domain-names = "psci", "perf"; l2_1: l2-cache { compatible = "cache"; @@ -117,8 +117,8 @@ reg = <0x0 0x10100>; enable-method = "psci"; next-level-cache = <&l2_1>; - power-domains = <&cpu_pd7>; - power-domain-names = "psci"; + power-domains = <&cpu_pd7>, <&scmi_dvfs 1>; + power-domain-names = "psci", "perf"; }; cpu-map { @@ -206,6 +206,21 @@ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; + + scmi { + compatible = "arm,scmi"; + mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names = "tx", "rx"; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #power-domain-cells = <1>; + }; + }; }; clk_virt: interconnect-0 { @@ -3743,6 +3758,13 @@ }; }; + cpucp_mbox: mailbox@16430000 { + compatible = "qcom,sm8750-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg = <0x0 0x16430000 0x0 0x8000>, <0x0 0x17830000 0x0 0x8000>; + interrupts = ; + #mbox-cells = <1>; + }; + apps_rsc: rsc@16500000 { compatible = "qcom,rpmh-rsc"; reg = <0x0 0x16500000 0x0 0x10000>, @@ -3954,6 +3976,25 @@ }; }; + sram: sram@17b4e000 { + compatible = "mmio-sram"; + reg = <0x0 0x17b4e000 0x0 0x400>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x17b4e000 0x400>; + + cpu_scp_lpri0: scp-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x200>; + }; + + cpu_scp_lpri1: scp-sram-section@200 { + compatible = "arm,scmi-shmem"; + reg = <0x200 0x200>; + }; + }; + /* cluster0 */ pmu@240b3400 { compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; From 89bce44320b4c39f3ea48591f7c04c961e404eae Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:05:28 +0900 Subject: [PATCH 238/757] arm64: dts: qcom: sm7225-fairphone-fp4: Add camera EEPROMs Add notes for the EEPROMs found on the main rear camera, ultra-wide rear camera and front camera. Also add some comments that act as placeholders for other nodes that will be added in the future, for the camera sensors and some VCM drivers. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251210-fp4-cam-prep-v1-2-0eacbff271ec@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 30 +++++++++++++++++-- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 4afbab570ca1..c2f856a56b2b 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -512,11 +512,28 @@ }; &cci0_i2c0 { - /* IMX582 @ 0x1a */ + /* Main cam (Sony IMX582) @ 0x1a */ + /* VCM driver (Onsemi LC898219XI) @ 0x28 */ + /* OIS driver (CML CM401) @ 0x30 */ + + eeprom@50 { + compatible = "giantec,gt24p128e", "atmel,24c128"; + reg = <0x50>; + vcc-supply = <&vreg_l6p>; + read-only; + }; }; &cci0_i2c1 { - /* IMX582 @ 0x1a */ + /* VCM driver (Dongwoon DW9800W) @ 0xc */ + /* Ultra-wide cam (Sony IMX582) @ 0x1a */ + + eeprom@50 { + compatible = "giantec,gt24p64a", "atmel,24c64"; + reg = <0x50>; + vcc-supply = <&vreg_l6p>; + read-only; + }; }; &cci1 { @@ -524,7 +541,14 @@ }; &cci1_i2c0 { - /* IMX576 @ 0x10 */ + /* Front cam (Sony IMX576) @ 0x10 */ + + eeprom@50 { + compatible = "giantec,gt24p64a", "atmel,24c64"; + reg = <0x50>; + vcc-supply = <&vreg_l6p>; + read-only; + }; }; &cdsp { From e1d3aeff520638d9d286f66e734c2cc8b489d5ee Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:05:29 +0900 Subject: [PATCH 239/757] arm64: dts: qcom: sm7225-fairphone-fp4: Add camera fixed regulators Add multiple fixed regulators that are found on the phone, which provide power to the cameras. Signed-off-by: Luca Weiss Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20251210-fp4-cam-prep-v1-3-0eacbff271ec@fairphone.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index c2f856a56b2b..0cfb24e3941d 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -246,6 +246,46 @@ }; }; }; + + vreg_32m_cam_dvdd_1p05: regulator-32m-cam-dvdd-1p05 { + compatible = "regulator-fixed"; + regulator-name = "32M_CAM_DVDD_1P05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&pm6150l_gpios 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_s8e>; + }; + + vreg_48m_ois_avdd0_1p8: regulator-48m-ois-avdd0-1p8 { + compatible = "regulator-fixed"; + regulator-name = "48M_OIS_AVDD0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pm6150l_gpios 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_bob>; + }; + + vreg_48m_uw_avdd0_1p8: regulator-48m-uw-avdd0-1p8 { + compatible = "regulator-fixed"; + regulator-name = "48M_UW_AVDD0_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_bob>; + }; + + vreg_ois_2p8: regulator-ois-2p8 { + compatible = "regulator-fixed"; + regulator-name = "OIS_2P8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&tlmm 72 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vreg_bob>; + }; }; &adsp { From 7a53133ac4b5b26924146bc1b044594894ccc400 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:05:30 +0900 Subject: [PATCH 240/757] arm64: dts: qcom: sm7225-fairphone-fp4: Enable CCI pull-up Enable vreg_l6p, which is the voltage source for the pull-up resistor of the CCI busses. This ensures that I2C communication works as expected. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251210-fp4-cam-prep-v1-4-0eacbff271ec@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 0cfb24e3941d..a3c2b26736f4 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -693,6 +693,8 @@ regulator-name = "vreg_l6p"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1800000>; + /* Pull-up for CCI I2C busses */ + regulator-always-on; }; vreg_l7p: ldo7 { From 252f98ecb3c71acd818592443496252ecd5ccd6f Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Mon, 10 Nov 2025 16:37:46 +0100 Subject: [PATCH 241/757] arm64: dts: qcom: sdm845-oneplus: add ath10k calibration variant SDM845-based Oneplus 6 and 6T have their own calibration files for the WCN3990 WiFi/Bluetooth radio with the ath10k driver. Add the calibration variant name to the DTS to reflect this to allow using the calibration files from linux-firmware. [David] Adjust the compatible as ath10k-calibration-variant is deprecated Signed-off-by: Dylan Van Assche Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251110-sdm845-calibration-variants-v1-1-2c536ada77c2@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index f1c63794db97..dc7120916fcd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -936,5 +936,6 @@ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + qcom,calibration-variant = "oneplus_sdm845"; qcom,snoc-host-cap-8bit-quirk; }; From ea6926f61a857531d02a72bb5b040e23573fb393 Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Mon, 10 Nov 2025 16:37:47 +0100 Subject: [PATCH 242/757] arm64: dts: qcom: sdm845-xiaomi-beryllium: Add ath10k calibration variant SDM845-based Xiaomi POCOPHONE F1 has its own calibration files for the WCN3990 WiFi/Bluetooth radio with the ath10k driver. Add the calibration variant name to the DTS to reflect this to allow using the calibration files from linux-firmware. [David] Adjust the compatible as ath10k-calibration-variant is deprecated Signed-off-by: Dylan Van Assche Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251110-sdm845-calibration-variants-v1-2-2c536ada77c2@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index 785006a15e97..ebcd01477f05 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -636,4 +636,7 @@ vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,calibration-variant = "xiaomi_beryllium"; }; + From 31deed7b05079b2eb24589d37778466a2a55f4f2 Mon Sep 17 00:00:00 2001 From: Dylan Van Assche Date: Mon, 10 Nov 2025 16:37:48 +0100 Subject: [PATCH 243/757] arm64: dts: qcom: sdm845-shift-axolotl: Add ath10k calibration variant SDM845-based SHIFTPHONES SHIFT6mq has its own calibration files for the WCN3990 WiFi/Bluetooth radio with the ath10k driver. Add the calibration variant name to the DTS to reflect this to allow using the calibration files from linux-firmware. [David] Adjust the compatible as ath10k-calibration-variant is deprecated Signed-off-by: Dylan Van Assche Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251110-sdm845-calibration-variants-v1-3-2c536ada77c2@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index a35c120361c1..51b041f91d3e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -746,5 +746,6 @@ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + qcom,calibration-variant = "shift_axolotl"; qcom,snoc-host-cap-8bit-quirk; }; From e814796dfcae8905682ac3ac2dd57f512a9f6726 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 11 Dec 2025 03:27:45 +0200 Subject: [PATCH 244/757] arm64: dts: qcom: sdm630: fix gpu_speed_bin size Historically sdm630.dtsi has used 1 byte length for the gpu_speed_bin cell, although it spans two bytes (offset 5, size 7 bits). It was being accepted by the kernel because before the commit 7a06ef751077 ("nvmem: core: fix bit offsets of more than one byte") the kernel didn't have length check. After this commit nvmem core rejects QFPROM on sdm630 / sdm660, making GPU and USB unusable on those platforms. Set the size of the gpu_speed_bin cell to 2 bytes, fixing the parsing error. While we are at it, update the length to 8 bits as pointed out by Alexey Minnekhanov. Fixes: b190fb010664 ("arm64: dts: qcom: sdm630: Add sdm630 dts file") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Alexey Minnekhanov Link: https://lore.kernel.org/r/20251211-sdm630-fix-gpu-v2-1-92f0e736dba0@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 90314cb49177..7f2650bc3ac1 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -598,8 +598,8 @@ }; gpu_speed_bin: gpu-speed-bin@41a0 { - reg = <0x41a2 0x1>; - bits = <5 7>; + reg = <0x41a2 0x2>; + bits = <5 8>; }; }; From d43019ef200d567454a8f68e60a5b2df01d8c706 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 Dec 2025 11:28:00 +0200 Subject: [PATCH 245/757] arm64: dts: qcom: sm8150-hdk,mtp: specify ZAP firmware name The DT file has GPU node enabled, but doesn't specify the file name of the ZAP firmware, which means using a default file name. Specify the name to the ZAP shader firmware, pointing to the file in the linux-firmware repo. Fixes: f30ac26def18 ("arm64: dts: qcom: add sm8150 GPU nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251213-zap-names-v1-1-c889af173911@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 4 ++++ arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index 0339a572f34d..1eea9c5c6684 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -387,6 +387,10 @@ status = "okay"; }; +&gpu_zap_shader { + firmware-name = "qcom/sm8150/a640_zap.mbn"; +}; + &i2c4 { clock-frequency = <100000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 12e8e1ada6d8..0f2d511624a8 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -358,6 +358,10 @@ status = "okay"; }; +&gpu_zap_shader { + firmware-name = "qcom/sm8150/a640_zap.mbn"; +}; + &pon { mode-bootloader = <0x2>; mode-recovery = <0x1>; From 95c121244a5d46435559bc74dbc7b5519394db08 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 Dec 2025 11:28:01 +0200 Subject: [PATCH 246/757] arm64: dts: qcom: sm8250-hdk: specify ZAP firmware name The DT file has GPU node enabled, but doesn't specify the file name of the ZAP firmware, which means using a default file name. Specify the name to the ZAP shader firmware, pointing to the file in the linux-firmware repo. Fixes: 04a3605b184e ("arm64: dts: qcom: add sm8250 GPU nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251213-zap-names-v1-2-c889af173911@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index f5c193c6c5f9..3ea9d2b1a7d5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -373,6 +373,10 @@ status = "okay"; }; +&gpu_zap_shader { + firmware-name = "qcom/sm8250/a650_zap.mbn"; +}; + &pon { mode-bootloader = <0x2>; mode-recovery = <0x1>; From 3845bc888660a238920fdba2f85fe284f01fb95f Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 14 Dec 2025 15:51:17 +0100 Subject: [PATCH 247/757] dt-bindings: arm: qcom: Add Pixel 3 and 3 XL Document the bindings for the Pixel 3 and 3 XL. Acked-by: Krzysztof Kozlowski Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251214-pixel-3-v7-1-b1c0cf6f224d@ixit.cz Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c0648c7b8109..c344d92da520 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -906,6 +906,8 @@ properties: - items: - enum: + - google,blueline + - google,crosshatch - huawei,planck - lenovo,yoga-c630 - lg,judyln From a678adbf2d22edcb9078f8ad56706891a0ac9e80 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 14 Dec 2025 15:51:24 +0100 Subject: [PATCH 248/757] arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL This adds initial device tree support for the following phones: - Google Pixel 3 (blueline) - Google Pixel 3 XL (crosshatch) Both phone boards use the same identifiers and differ only slightly in their connected peripherals. Supported functionality includes: - Debug UART - UFS - USB-C (peripheral mode) - Framebuffer (both u-boot and Linux) - Display (Pixel 3 only, and the driver needs work) - GPU - Bluetooth - Wi-Fi The rmtfs region is allocated using UIO, making it technically "dynamic." Its address and size can be read from sysfs: $ cat /sys/class/uio/uio0/name /sys/class/uio/uio0/maps/map0/addr 0x00000000f2701000 $ cat /sys/class/uio/uio0/maps/map0/size 0x0000000000200000 Like the OnePlus 6, the Pixel 3 requires 1 kB of reserved memory on either side of the rmtfs region to work around an XPU bug that would otherwise cause erroneous violations when accessing the rmtfs_mem region. Co-developed-by: Amit Pundir Signed-off-by: Amit Pundir Co-developed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Co-developed-by: Casey Connolly Signed-off-by: Casey Connolly Co-developed-by: Joel Selvaraj Signed-off-by: Joel Selvaraj Co-developed-by: Sumit Semwal Signed-off-by: Sumit Semwal Co-developed-by: Vinod Koul Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251214-pixel-3-v7-8-b1c0cf6f224d@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/sdm845-google-blueline.dts | 89 +++ .../boot/dts/qcom/sdm845-google-common.dtsi | 536 ++++++++++++++++++ .../dts/qcom/sdm845-google-crosshatch.dts | 36 ++ 4 files changed, 663 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 565e9b317a37..82beab1d7955 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -252,6 +252,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine-dtbs := sdm845-db845c.dtb sdm845-db845c-navigation-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-crosshatch.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-google-blueline.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts new file mode 100644 index 000000000000..fa89be500fb8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-blueline.dts @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model = "Google Pixel 3"; + compatible = "google,blueline", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours = <2970000>; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4400000>; +}; + +&framebuffer0 { + width = <1080>; + height = <2160>; + stride = <(1080 * 4)>; +}; + +&i2c2 { + clock-frequency = <1000000>; + + status = "okay"; + + /* ST,FTS @ 49 */ +}; + +&mdss_dsi0 { + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + status = "okay"; + + panel@0 { + compatible = "lg,sw43408-lh546wf1-ed01", "lg,sw43408"; + reg = <0>; + + vddi-supply = <&vreg_l14a_1p8>; + vpnl-supply = <&vreg_l28a_3p0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&panel_default>; + pinctrl-names = "default"; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; + qcom,te-source = "mdp_vsync_e"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vdda_mipi_dsi0_pll>; + + status = "okay"; +}; + +&tlmm { + panel_default: panel-default-state { + reset-pins { + pins = "gpio6"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + te-pins { + pins = "gpio12"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&wifi { + qcom,calibration-variant = "Google_blueline"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi new file mode 100644 index 000000000000..fd9788d5c3f5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-common.dtsi @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/delete-node/ &mpss_region; +/delete-node/ &venus_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &mba_region; +/delete-node/ &slpi_mem; +/delete-node/ &spss_mem; +/delete-node/ &rmtfs_mem; + +/ { + chassis-type = "handset"; + qcom,board-id = <0x00021505 0>; + qcom,msm-id = ; + + aliases { + serial0 = &uart9; + serial1 = &uart6; + }; + + battery: battery { + compatible = "simple-battery"; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0:115200n8"; + + /* Use display framebuffer as setup by bootloader */ + framebuffer0: framebuffer-0 { + compatible = "simple-framebuffer"; + memory-region = <&cont_splash_mem>; + + format = "a8r8g8b8"; + }; + }; + + reserved-memory { + cont_splash_mem: splash@9d400000 { + reg = <0 0x9d400000 0 0x02400000>; + no-map; + }; + + mpss_region: memory@8e000000 { + reg = <0 0x8e000000 0 0x9800000>; + no-map; + }; + + venus_mem: venus@97800000 { + reg = <0 0x97800000 0 0x500000>; + no-map; + }; + + cdsp_mem: cdsp-mem@97D00000 { + reg = <0 0x97D00000 0 0x800000>; + no-map; + }; + + mba_region: mba@98500000 { + reg = <0 0x98500000 0 0x200000>; + no-map; + }; + + slpi_mem: slpi@98700000 { + reg = <0 0x98700000 0 0x1400000>; + no-map; + }; + + spss_mem: spss@99B00000 { + reg = <0 0x99B00000 0 0x100000>; + no-map; + }; + + rmtfs_mem: rmtfs-region@f2700000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf2700000 0 0x202000>; + qcom,use-guard-pages; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "Volume keys"; + autorepeat; + + pinctrl-0 = <&volume_up_gpio>; + pinctrl-names = "default"; + + key-vol-up { + label = "Volume Up"; + linux,code = ; + gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: regulator-vreg-s4a-1p8 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pas { + firmware-name = "qcom/sdm845/Google/blueline/adsp.mbn"; + + status = "okay"; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdda_mipi_dsi0_pll: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + regulator-boot-on; + }; + + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l19a_3p3: ldo19 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + /* + * The touchscreen needs this to be 3.3v, which is apparently + * quite close to the hardware limit for this LDO (3.312v) + * It must be kept in high power mode to prevent TS brownouts + */ + regulator-allowed-modes = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2968000>; + regulator-initial-mode = ; + }; + + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_mipi_dsi0_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-boot-on; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + regulator-boot-on; + /* + * We can't properly bring the panel back if it gets turned off + * so keep it's regulators always on for now. + */ + regulator-always-on; + }; + }; + + regulators-1 { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; + + regulators-2 { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c1 { + /* actuator @0c */ + + /* front camera, imx355 @1a */ + + /* eeprom @50, at24 driver says 8K */ +}; + +&cdsp_pas { + firmware-name = "qcom/sdm845/Google/blueline/cdsp.mbn"; + + status = "okay"; +}; + +&gcc { + protected-clocks = , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/sdm845/Google/blueline/a630_zap.mbn"; +}; + +&i2c12 { + /* Bottom spkr (right) CS35L36 @ 40 */ + + /* Top spkr (left) CS35L36 @ 41 */ +}; + +&ipa { + firmware-name = "qcom/sdm845/Google/blueline/ipa_fws.mbn"; + memory-region = <&ipa_fw_mem>; + + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mss_pil { + firmware-name = "qcom/sdm845/Google/blueline/mba.mbn", + "qcom/sdm845/Google/blueline/modem.mbn"; + + status = "okay"; +}; + +&pm8998_gpios { + volume_up_gpio: vol-up-active-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <0>; + }; +}; + +&pm8998_resin { + linux,code = ; + + status = "okay"; +}; + +&pmi8998_charger { + monitored-battery = <&battery>; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&qup_uart9_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_uart9_tx { + drive-strength = <2>; + bias-disable; +}; + +&tlmm { + gpio-reserved-ranges = < 0 4>, /* SPI (Intel MNH Pixel Visual Core) */ + <81 4>; /* SPI (most likely Fingerprint Cards FPC1075) */ + + touchscreen_reset: ts-reset-state { + pins = "gpio99"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + touchscreen_pins: ts-pins-gpio-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + touchscreen_i2c_pins: qup-i2c2-gpio-state { + pins = "gpio27", "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart6 { + pinctrl-0 = <&qup_uart6_4pin>; + + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <800000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; + + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; + + status = "okay"; +}; + +&venus { + firmware-name = "qcom/sdm845/Google/blueline/venus.mbn"; + + status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts new file mode 100644 index 000000000000..2a81ca1d00b1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-google-crosshatch.dts @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "sdm845-google-common.dtsi" + +/ { + model = "Google Pixel 3 XL"; + compatible = "google,crosshatch", "qcom,sdm845"; +}; + +&battery { + charge-full-design-microamp-hours = <3480000>; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4400000>; +}; + +&dispcc { + /* Disable for now so simple-framebuffer continues working */ + status = "disabled"; +}; + +&framebuffer0 { + width = <1440>; + height = <2960>; + stride = <(1440 * 4)>; +}; + +&mdss { + /* Disable for now so simple-framebuffer continues working */ + status = "disabled"; +}; + +&wifi { + qcom,calibration-variant = "Google_crosshatch"; +}; From 0f15cbbf315c12a9c1004196d5beed8cce9dcf6d Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Mon, 8 Dec 2025 17:15:58 +0530 Subject: [PATCH 249/757] arm64: dts: qcom: monaco: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Gaurav Kohli Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251208114558.2343462-1-gaurav.kohli@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index c389135f86ce..96bfc35f955e 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -55,6 +55,7 @@ power-domain-names = "psci"; capacity-dmips-mhz = <1946>; dynamic-power-coefficient = <472>; + #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -79,6 +80,7 @@ power-domains = <&cpu_pd1>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; + #cooling-cells = <2>; dynamic-power-coefficient = <472>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; @@ -104,6 +106,7 @@ power-domains = <&cpu_pd2>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; + #cooling-cells = <2>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu2_opp_table>; @@ -129,6 +132,7 @@ power-domains = <&cpu_pd3>; power-domain-names = "psci"; capacity-dmips-mhz = <1946>; + #cooling-cells = <2>; dynamic-power-coefficient = <507>; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu2_opp_table>; @@ -154,6 +158,7 @@ power-domains = <&cpu_pd4>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; @@ -179,6 +184,7 @@ power-domains = <&cpu_pd5>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; @@ -204,6 +210,7 @@ power-domains = <&cpu_pd6>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; @@ -229,6 +236,7 @@ power-domains = <&cpu_pd7>; power-domain-names = "psci"; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; From e95ddac66a77077a021c9f2e6b3cf6dc236b655c Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Mon, 15 Dec 2025 10:24:51 +0530 Subject: [PATCH 250/757] arm64: dts: qcom: lemans: Enable cpufreq cooling devices Add cooling-cells property to the CPU nodes to support cpufreq cooling devices. Signed-off-by: Gaurav Kohli Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251215045451.3150894-1-gaurav.kohli@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 148dc65ede3d..d383d1f8bb9d 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -55,6 +55,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_0>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -84,6 +85,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_1>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -108,6 +110,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_2>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -132,6 +135,7 @@ qcom,freq-domain = <&cpufreq_hw 0>; next-level-cache = <&l2_3>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -156,6 +160,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&l2_4>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -186,6 +191,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&l2_5>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -210,6 +216,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&l2_6>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -234,6 +241,7 @@ qcom,freq-domain = <&cpufreq_hw 1>; next-level-cache = <&l2_7>; capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; dynamic-power-coefficient = <100>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY From d46a0900bdb95a4b1175fa821b46abc11664314b Mon Sep 17 00:00:00 2001 From: Khalid Faisal Ansari Date: Fri, 14 Nov 2025 15:45:45 +0530 Subject: [PATCH 251/757] arm64: dts: qcom: lemans-evk: Enable TPM (ST33) Enable ST33HTPM TPM over SPI16 on the LeMans IoT EVK by adding the required SPI and TPM nodes. Signed-off-by: Khalid Faisal Ansari Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251114-enable-tpm-lemans-v1-1-c8d8b580ace7@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 28bf152f5fa8..02f886e0d2ce 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -691,6 +691,16 @@ clock-frequency = <32768>; }; +&spi16 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + &tlmm { ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { From dce54bba172e351777d3ddcec9f7d03bea99ddf7 Mon Sep 17 00:00:00 2001 From: Khalid Faisal Ansari Date: Fri, 14 Nov 2025 15:47:37 +0530 Subject: [PATCH 252/757] arm64: dts: qcom: monaco-evk: Enable TPM (ST33) Enable ST33HTPM TPM over SPI10 on the Monaco IoT EVK by adding the required SPI and TPM nodes. Signed-off-by: Khalid Faisal Ansari Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251114-enable-tpm-monaco-v1-1-4ed566838698@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index bb35893da73d..f76ad689d7ae 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -434,6 +434,16 @@ status = "okay"; }; +&spi10 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + &tlmm { ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { From 1a5d6d70c3b0b9b2007cd57001266dc018b6098e Mon Sep 17 00:00:00 2001 From: Yingying Tang Date: Wed, 10 Dec 2025 11:28:17 +0800 Subject: [PATCH 253/757] arm64: dts: qcom: hamoa-iot-evk: Add WLAN node for Hamoa IoT EVK board WLAN card is connected to PCIe4 on Hamoa IoT EVK board. Add WLAN node to support power sequence for this WLAN card. Signed-off-by: Yingying Tang Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251210032817.1264850-1-yingying.tang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 26 +++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 88e3e7bed998..bac531421292 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -581,7 +581,7 @@ bt-enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; wlan-enable-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&wcn_bt_en>; + pinctrl-0 = <&wcn_bt_en>, <&wcn_wlan_en>; pinctrl-names = "default"; regulators { @@ -891,6 +891,23 @@ status = "okay"; }; +&pcie4_port0 { + wifi@0 { + compatible = "pci17cb,1107"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + vddaon-supply = <&vreg_pmu_aon_0p59>; + vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; + vddwlmx-supply = <&vreg_pmu_wlmx_0p85>; + vddrfacmn-supply = <&vreg_pmu_rfa_cmn>; + vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; + vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; + vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; + vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>; + vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>; + }; +}; + &pcie6a { vddpe-3v3-supply = <&vreg_nvme>; }; @@ -1206,6 +1223,13 @@ bias-disable; }; + wcn_wlan_en: wcn-wlan-en-state { + pins = "gpio117"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wwan_sw_en: wwan-sw-en-state { pins = "gpio221"; function = "gpio"; From a499c40ccd8e748ef363e2d13fb7a5c0ed6a788a Mon Sep 17 00:00:00 2001 From: Jingzhou Zhu Date: Mon, 8 Dec 2025 11:15:10 +0800 Subject: [PATCH 254/757] arm64: dts: qcom: sdm850-huawei-matebook-e-2019: Remove duplicate reserved-memroy nodes The adsp_mem and slpi_mem defined in sdm845.dtsi work well. Remove these nodes here to avoid redefinition. Signed-off-by: Jingzhou Zhu Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251208031511.3284-2-newwheatzjz@zohomail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts index 0ef9ea38a424..a5f025ae7dbe 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -30,9 +30,7 @@ /delete-node/ &ipa_fw_mem; /delete-node/ &ipa_gsi_mem; /delete-node/ &gpu_mem; -/delete-node/ &adsp_mem; /delete-node/ &wlan_msa_mem; -/delete-node/ &slpi_mem; / { model = "Huawei MateBook E 2019"; @@ -145,20 +143,11 @@ no-map; }; - adsp_mem: adsp@8c500000 { - reg = <0 0x8c500000 0 0x1a00000>; - no-map; - }; - ipa_fw_mem: ipa-fw@8df00000 { reg = <0 0x8df00000 0 0x100000>; no-map; }; - slpi_mem: slpi@96700000 { - reg = <0 0x96700000 0 0x1200000>; - }; - gpu_mem: gpu@97900000 { reg = <0 0x97900000 0 0x5000>; no-map; From bc11f6f1d2470fa59846be077555f9d4b7c2c0d3 Mon Sep 17 00:00:00 2001 From: Jingzhou Zhu Date: Mon, 8 Dec 2025 11:15:11 +0800 Subject: [PATCH 255/757] arm64: dts: qcom: sdm850-huawei-matebook-e-2019: Correct ipa_fw_mem for the driver to load successfully The ipa driver refuses to load with the old ipa_fw_mem in newer kernels. Shrinking its size to 0x5a000 fixes the problem. Fixes: aab69794b55d ("arm64: dts: qcom: Add support for Huawei MateBook E 2019") Signed-off-by: Jingzhou Zhu Link: https://lore.kernel.org/r/20251208031511.3284-3-newwheatzjz@zohomail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts index a5f025ae7dbe..f04865381870 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-huawei-matebook-e-2019.dts @@ -144,12 +144,12 @@ }; ipa_fw_mem: ipa-fw@8df00000 { - reg = <0 0x8df00000 0 0x100000>; + reg = <0 0x8df00000 0 0x5a000>; no-map; }; - gpu_mem: gpu@97900000 { - reg = <0 0x97900000 0 0x5000>; + gpu_mem: gpu@8df5a000 { + reg = <0 0x8df5a000 0 0x5000>; no-map; }; From e5e22c8ea49e62c390e3843a632727569f6470a2 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 8 Dec 2025 21:41:02 +0900 Subject: [PATCH 256/757] ARM: dts: qcom: msm8974-hammerhead: Update model property Many years have passed (more than 9 actually) since the introduction of the Nexus 5 dts to Linux and it's high time to update the model property to be a proper model name and thereby bringing it to the standards of the 2020s. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20251208-msm8974-hammerhead-model-v1-1-88975f30cbaa@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index b3127f0383cf..8f4a1fda9276 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -7,7 +7,7 @@ #include / { - model = "LGE MSM 8974 HAMMERHEAD"; + model = "LG Nexus 5"; compatible = "lge,hammerhead", "qcom,msm8974"; chassis-type = "handset"; From 9bf9c47cd8e54d0653147bc7a7e6c135607286be Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sat, 6 Dec 2025 18:45:42 +0100 Subject: [PATCH 257/757] arm64: dts: qcom: sdm845-oneplus-enchilada: Sort nodes alphabetically Sort the nodes by alphabet, no functional changes. Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251206-sdm845-oneplus-fb-v1-1-19b666b27d6e@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index a259eb9d45ae..4aa8a9353b67 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -30,16 +30,16 @@ }; }; +&bq27441_fg { + monitored-battery = <&battery>; +}; + &display_panel { status = "okay"; compatible = "samsung,sofef00"; }; -&bq27441_fg { - monitored-battery = <&battery>; -}; - &i2c4 { status = "okay"; From b0d5c96e860c28159541e7bb8ed277b0fee13a0c Mon Sep 17 00:00:00 2001 From: Sam Day Date: Sat, 6 Dec 2025 18:45:43 +0100 Subject: [PATCH 258/757] arm64: dts: qcom: sdm845-oneplus: Add framebuffer Introduce the framebuffer node, mostly useful for the u-boot and early boot stages. Signed-off-by: Sam Day Co-developed-by: David Heidelberg Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251206-sdm845-oneplus-fb-v1-2-19b666b27d6e@ixit.cz Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm845-oneplus-common.dtsi | 18 ++++++++++++++++++ .../boot/dts/qcom/sdm845-oneplus-enchilada.dts | 4 ++++ .../boot/dts/qcom/sdm845-oneplus-fajita.dts | 4 ++++ 3 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index dc7120916fcd..9d1ebfaaa2be 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -31,7 +31,20 @@ }; chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + stdout-path = "serial0:115200n8"; + + framebuffer: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + memory-region = <&cont_splash_mem>; + + format = "a8r8g8b8"; + stride = <(1080 * 4)>; + width = <1080>; + }; }; gpio-hall-sensor { @@ -75,6 +88,11 @@ }; reserved-memory { + cont_splash_mem: splash@9d400000 { + reg = <0 0x9d400000 0 0x02400000>; + no-map; + }; + /* * The rmtfs memory region in downstream is 'dynamically allocated' * but given the same address every time. Hard code it as this address is diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 4aa8a9353b67..dcaea15c6d43 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -40,6 +40,10 @@ compatible = "samsung,sofef00"; }; +&framebuffer { + height = <2280>; +}; + &i2c4 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index d6cd873aef0d..0542333a8357 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -35,6 +35,10 @@ compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01"; }; +&framebuffer { + height = <2340>; +}; + &i2c4 { /* nxp,tfa9894 @ 0x34 */ }; From 2a7dac907be27bd0b86a6f2df3f5feedcb538263 Mon Sep 17 00:00:00 2001 From: Robert Eckelmann Date: Fri, 5 Dec 2025 22:58:59 +0900 Subject: [PATCH 259/757] arm64: dts: qcom: sdm845-xiaomi-beryllium: Enable SLPI Enable the SLPI dsp on the Xiaomi Pocophone F1 with Qualcom SDM845 SoC. Signed-off-by: Robert Eckelmann Signed-off-by: David Heidelberg Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251205-slpi-v3-1-a1320a074345@gmail.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index ebcd01477f05..b2aafe1edcc4 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -425,6 +425,12 @@ cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>; }; +&slpi_pas { + firmware-name = "qcom/sdm845/Xiaomi/beryllium/slpi.mbn"; + + status = "okay"; +}; + &sound { compatible = "qcom,db845c-sndcard", "qcom,sdm845-sndcard"; pinctrl-0 = <&quat_mi2s_active From f4e6e3f827a0c53f38b3186335069d855ea9e9ff Mon Sep 17 00:00:00 2001 From: Robert Eckelmann Date: Fri, 5 Dec 2025 22:59:00 +0900 Subject: [PATCH 260/757] arm64: dts: qcom: sdm845-xiaomi-beryllium: Adjust firmware paths Firmware patht adjusted to include device maker "Xiaomi" Signed-off-by: Robert Eckelmann Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251205-slpi-v3-2-a1320a074345@gmail.com Signed-off-by: Bjorn Andersson --- .../dts/qcom/sdm845-xiaomi-beryllium-common.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index b2aafe1edcc4..fcee0933c171 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -136,7 +136,7 @@ &adsp_pas { status = "okay"; - firmware-name = "qcom/sdm845/beryllium/adsp.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/adsp.mbn"; }; &apps_rsc { @@ -229,7 +229,7 @@ &cdsp_pas { status = "okay"; - firmware-name = "qcom/sdm845/beryllium/cdsp.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/cdsp.mbn"; }; &gcc { @@ -249,7 +249,7 @@ }; &gpu_zap_shader { - firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/a630_zap.mbn"; }; &ibb { @@ -308,13 +308,14 @@ &mss_pil { status = "okay"; - firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/mba.mbn", + "qcom/sdm845/Xiaomi/beryllium/modem.mbn"; }; &ipa { qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/ipa_fws.mbn"; status = "okay"; }; @@ -618,7 +619,7 @@ &venus { status = "okay"; - firmware-name = "qcom/sdm845/beryllium/venus.mbn"; + firmware-name = "qcom/sdm845/Xiaomi/beryllium/venus.mbn"; }; &wcd9340 { From 5bde31dc7b17b668a02857c30359ac86c23c9e55 Mon Sep 17 00:00:00 2001 From: Robert Eckelmann Date: Fri, 5 Dec 2025 22:59:01 +0900 Subject: [PATCH 261/757] arm64: dts: qcom: sdm845-xiaomi-beryllium: Add placeholders and sort We know these devices are present, most of them are supported by downstream and close to the mainline kernels. This is very handy when rebasing the integration tree with the support. No functional changes. Reviewed-by: David Heidelberg Signed-off-by: Robert Eckelmann Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251205-slpi-v3-3-a1320a074345@gmail.com Signed-off-by: Bjorn Andersson --- .../qcom/sdm845-xiaomi-beryllium-common.dtsi | 29 ++++++++++++++----- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi index fcee0933c171..01b570d0880d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium-common.dtsi @@ -227,6 +227,12 @@ }; }; +&cci_i2c0 { + status = "okay"; + + /* IMX363 @ 10 */ +}; + &cdsp_pas { status = "okay"; firmware-name = "qcom/sdm845/Xiaomi/beryllium/cdsp.mbn"; @@ -261,6 +267,22 @@ qcom,discharge-resistor-kohms = <300>; }; +&ipa { + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; + + status = "okay"; +}; + +&i2c5 { + clock-frequency = <400000>; + + status = "okay"; + + /* TAS2559 @ 4C */ +}; + &lab { regulator-min-microvolt = <4600000>; regulator-max-microvolt = <6000000>; @@ -312,13 +334,6 @@ "qcom/sdm845/Xiaomi/beryllium/modem.mbn"; }; -&ipa { - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sdm845/Xiaomi/beryllium/ipa_fws.mbn"; - status = "okay"; -}; - &pm8998_gpios { vol_up_pin_a: vol-up-active-state { pins = "gpio6"; From fc4795cf96af49a03b72fc0f260f824d969243e8 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Thu, 4 Dec 2025 09:41:58 +0530 Subject: [PATCH 262/757] arm64: dts: qcom: monaco-evk: Enable AMC6821 fan controller Enable AMC6821 fan controller for monaco-evk platform and configure pwm polarity as inverted. Signed-off-by: Gaurav Kohli Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251204041158.2613340-1-gaurav.kohli@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index f76ad689d7ae..15cfb3aa3fa8 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include @@ -323,6 +324,16 @@ status = "okay"; + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + eeprom0: eeprom@50 { compatible = "atmel,24c256"; reg = <0x50>; From 6e6cf8ff9917c7927a0e571a340b4effc45548d5 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 2 Dec 2025 13:40:15 +0530 Subject: [PATCH 263/757] arm64: dts: qcom: sm8750: Add SDC2 nodes for sm8750 soc Add SD Card host controller for sm8750 soc. Signed-off-by: Sarthak Garg Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251202081017.2234677-2-sarthak.garg@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 54 ++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 260ab4fef6c6..8a471b2349be 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2597,6 +2597,60 @@ }; }; + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8750-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + iommus = <&apps_smmu 0x540 0x0>; + dma-coherent; + + bus-width = <4>; + max-sd-hs-hz = <37500000>; + + resets = <&gcc GCC_SDCC2_BCR>; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_hsphy: phy@88e3000 { compatible = "qcom,sm8750-m31-eusb2-phy"; reg = <0x0 0x88e3000 0x0 0x29c>; From add674d84596bfbcef956898327387d0d9489ab5 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 2 Dec 2025 13:40:16 +0530 Subject: [PATCH 264/757] arm64: dts: qcom: sm8750-mtp: Add SDC2 node for sm8750 mtp board Enable SD Card host controller for sm8750 mtp board. Signed-off-by: Sarthak Garg Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251202081017.2234677-3-sarthak.garg@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index c8cb521b4c26..bfde752f6365 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -1075,6 +1075,22 @@ status = "fail"; }; +&sdhc_2 { + cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &swr0 { status = "okay"; @@ -1194,6 +1210,13 @@ }; }; + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + wcd_default: wcd-reset-n-active-state { pins = "gpio101"; function = "gpio"; From 3d852462ecfeccddfe48b0eca2407118ba8efad4 Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Tue, 2 Dec 2025 13:40:17 +0530 Subject: [PATCH 265/757] arm64: dts: qcom: sm8750-qrd: Add SDC2 node for sm8750 qrd board Enable SD Card host controller for sm8750 qrd board. Signed-off-by: Sarthak Garg Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251202081017.2234677-4-sarthak.garg@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index b0cb61c5a603..439ffb202599 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -961,6 +961,22 @@ status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &swr0 { status = "okay"; @@ -1053,6 +1069,13 @@ /* reserved for secure world */ gpio-reserved-ranges = <36 4>, <74 1>; + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + spkr_0_sd_n_active: spkr-0-sd-n-active-state { pins = "gpio76"; function = "gpio"; From 3b226dc2a0c39de609ecb383a92d9ed99d7aebc8 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 28 Nov 2025 15:55:07 +0530 Subject: [PATCH 266/757] arm64: dts: qcom: lemans-evk: Add OTG support for primary USB controller Enable OTG support for primary USB controller on EVK Platform. Add HD3SS3220 Type-C port controller present between Type-C port and SoC that provides role switch notifications to controller. Signed-off-by: Krishna Kurapati Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251128102507.3206169-1-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 109 +++++++++++++++++++++++- arch/arm64/boot/dts/qcom/lemans.dtsi | 20 +++++ 2 files changed, 127 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 02f886e0d2ce..90fce947ca7e 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -38,6 +38,36 @@ stdout-path = "serial0:115200n8"; }; + connector-0 { + compatible = "usb-c-connector"; + label = "USB0-Type-C"; + data-role = "dual"; + power-role = "dual"; + + vbus-supply = <&vbus_supply_regulator_0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb0_con_hs_ep: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + usb0_con_ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + edp0-connector { compatible = "dp-connector"; label = "EDP0"; @@ -102,6 +132,15 @@ }; }; + vbus_supply_regulator_0: regulator-vbus-supply-0 { + compatible = "regulator-fixed"; + regulator-name = "vbus_supply_0"; + gpio = <&expander1 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + vmmc_sdc: regulator-vmmc-sdc { compatible = "regulator-fixed"; @@ -462,6 +501,43 @@ firmware-name = "qcom/sa8775p/a663_zap.mbn"; }; +&i2c11 { + status = "okay"; + + usb-typec@67 { + compatible = "ti,hd3ss3220"; + reg = <0x67>; + + interrupts-extended = <&pmm8654au_2_gpios 5 IRQ_TYPE_EDGE_FALLING>; + + id-gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb_id>, <&usb0_intr_state>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&usb0_con_ss_ep>; + }; + }; + + port@1 { + reg = <1>; + + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb_0_dwc3_ss>; + }; + }; + }; + }; +}; + &i2c18 { status = "okay"; @@ -615,6 +691,16 @@ status = "okay"; }; +&pmm8654au_2_gpios { + usb0_intr_state: usb0-intr-state { + pins = "gpio5"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + }; +}; + &qup_i2c19_default { drive-strength = <2>; bias-pull-up; @@ -764,11 +850,24 @@ }; }; + qup_i2c11_default: qup-i2c11-state { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + sd_cd: sd-cd-state { pins = "gpio36"; function = "gpio"; bias-pull-up; }; + + usb_id: usb-id-state { + pins = "gpio50"; + function = "gpio"; + bias-pull-up; + }; }; &uart10 { @@ -797,11 +896,17 @@ }; &usb_0 { - dr_mode = "peripheral"; - status = "okay"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&usb0_con_hs_ep>; +}; + +&usb_0_dwc3_ss { + remote-endpoint = <&hd3ss3220_out_ep>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l7a>; vdda18-supply = <&vreg_l6c>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index d383d1f8bb9d..d0d8711ea9c6 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4047,7 +4047,27 @@ snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; + usb-role-switch; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_0_dwc3_ss: endpoint { + }; + }; + }; }; usb_1: usb@a800000 { From 640565d3f3654b7e8848c5bcf01843f04bfa769a Mon Sep 17 00:00:00 2001 From: Hongyang Zhao Date: Wed, 26 Nov 2025 00:07:02 +0800 Subject: [PATCH 267/757] dt-bindings: arm: qcom: Add Thundercomm RUBIK Pi 3 Add compatible for the Thundercomm RUBIK Pi 3 board, which is based on the Qualcomm Dragonwing QCS6490 SoC. Reviewed-by: Roger Shimizu Acked-by: Krzysztof Kozlowski Signed-off-by: Hongyang Zhao Link: https://lore.kernel.org/r/20251126-rubikpi-next-20251125-v7-1-e46095b80529@thundersoft.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c344d92da520..acba980bdf4a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -354,6 +354,7 @@ properties: - qcom,qcs6490-rb3gen2 - radxa,dragon-q6a - shift,otter + - thundercomm,rubikpi3 - const: qcom,qcm6490 - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform From f055a39f6874b0e86926fe17f40b676cf287ac11 Mon Sep 17 00:00:00 2001 From: Hongyang Zhao Date: Wed, 26 Nov 2025 00:07:03 +0800 Subject: [PATCH 268/757] arm64: dts: qcom: Add qcs6490-rubikpi3 board dts Add DTS for Thundercomm qcs6490-rubikpi3 board which uses QCS6490 SoC. Works: - Bluetooth (AP6256) - Wi-Fi (AP6256) - Ethernet (AX88179B connected to UPD720201) - Two USB Type-A 3.0 ports (UPD720201 connected to PCIe0) - USB Type-A 2.0 port - USB Type-C - M.2 M-Key 2280 PCIe 3.0 - FAN - RTC - 40PIN: I2C x1, UART x1 Signed-off-by: Hongyang Zhao Reviewed-by: Roger Shimizu Reviewed-by: Christopher Obbard Tested-by: Christopher Obbard Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251126-rubikpi-next-20251125-v7-2-e46095b80529@thundersoft.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 1410 +++++++++++++++++ 2 files changed, 1411 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 82beab1d7955..f139e5334527 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -140,6 +140,7 @@ qcs6490-rb3gen2-industrial-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2 dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-thundercomm-rubikpi3.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts new file mode 100644 index 000000000000..0b64a0b91202 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -0,0 +1,1410 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Thundercomm All rights reserved. + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include "kodiak.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model = "Thundercomm RUBIK Pi 3"; + compatible = "thundercomm,rubikpi3", "qcom,qcm6490"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&kypd_vol_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,can-disable; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + pmic-glink { + compatible = "qcom,qcm6490-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu_in: endpoint { + remote-endpoint = <&usb1_sbu_mux>; + }; + }; + }; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + + /* cooling level (0, 1, 2, 3) : (0% duty, 25% duty, 50% duty, 100% duty) */ + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + pwms = <&pm8350c_pwm 3 1000000>; + + pinctrl-0 = <&fan_pwm_out_default>; + pinctrl-names = "default"; + }; + + vreg_eth_1v8: regulator-eth-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_eth_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usb_eth_power>; + pinctrl-names = "default"; + + vin-supply = <&vreg_usbhub_pwr_1v8>; + }; + + vreg_lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_lt9611_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 83 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <<9611_vcc_pin>; + pinctrl-names = "default"; + }; + + vreg_m2_1v8: regulator-m2-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_m2_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + + gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&m2_vcc_pin>; + pinctrl-names = "default"; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_usbhub_pwr_1v8: regulator-usbhub-pwr-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_usbhub_pwr_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usbhub_power>; + pinctrl-names = "default"; + + regulator-always-on; + }; + + vreg_usbhub_rest_1v8: regulator-usbhub-rest-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_usbhub_rest_1v8"; + regulator-min-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 136 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&usbhub_rest>; + pinctrl-names = "default"; + + vin-supply = <&vreg_eth_1v8>; + + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_wifi_1v8: regulator-wifi-1v8 { + compatible = "regulator-fixed"; + + regulator-name = "vreg_wifi_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <50000>; + + gpio = <&tlmm 125 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&wifi_reset_active>, + <&wifi_host_wake>, + <&wifi_power_on>; + pinctrl-names = "default"; + + regulator-always-on; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg = <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg = <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg = <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@86100000 { + reg = <0x0 0x86100000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@88900000 { + reg = <0x0 0x88900000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@8a700000 { + reg = <0x0 0x8a700000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@8ae00000 { + reg = <0x0 0x8ae00000 0x0 0x500000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@8b31a000 { + reg = <0x0 0x8b31a000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg = <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg = <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg = <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg = <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg = <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + thermal-zones { + quiet-thermal { + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + sdm-skin-thermal { + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + + usb1-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb1_sbu_default>; + pinctrl-names = "default"; + + mode-switch; + orientation-switch; + + port { + usb1_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu_in>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p972>; + vdd-l2-l7-supply = <&vreg_bob_3p296>; + vdd-l3-supply = <&vreg_s2b_0p876>; + vdd-l5-supply = <&vreg_s2b_0p876>; + vdd-l6-l9-l10-supply = <&vreg_s8b_1p272>; + vdd-l8-supply = <&vreg_s7b_0p972>; + vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p872>; + vdd-l13-supply = <&vreg_s7b_0p972>; + vdd-l14-l16-supply = <&vreg_s8b_1p272>; + + vreg_s1b_1p872: smps1 { + regulator-name = "vreg_s1b_1p872"; + regulator-min-microvolt = <1840000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s2b_0p876: smps2 { + regulator-name = "vreg_s2b_0p876"; + regulator-min-microvolt = <570070>; + regulator-max-microvolt = <1050000>; + }; + + vreg_s7b_0p972: smps7 { + regulator-name = "vreg_s7b_0p972"; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vreg_s8b_1p272: smps8 { + regulator-name = "vreg_s8b_1p272"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-initial-mode = ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name = "vreg_l1b_0p912"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name = "vreg_l2b_3p072"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p504: ldo3 { + regulator-name = "vreg_l3b_0p504"; + regulator-min-microvolt = <312000>; + regulator-max-microvolt = <910000>; + regulator-initial-mode = ; + }; + + vreg_l4b_0p752: ldo4 { + regulator-name = "vreg_l4b_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <820000>; + regulator-initial-mode = ; + }; + + reg_l5b_0p752: ldo5 { + regulator-name = "reg_l5b_0p752"; + regulator-min-microvolt = <552000>; + regulator-max-microvolt = <832000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p952: ldo7 { + regulator-name = "vreg_l7b_2p952"; + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + regulator-initial-mode = ; + }; + + vreg_l8b_0p904: ldo8 { + regulator-name = "vreg_l8b_0p904"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11b_1p504: ldo11 { + regulator-name = "vreg_l11b_1p504"; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l12b_0p751: ldo12 { + regulator-name = "vreg_l12b_0p751"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l13b_0p53: ldo13 { + regulator-name = "vreg_l13b_0p53"; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l14b_1p08: ldo14 { + regulator-name = "vreg_l14b_1p08"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l15b_0p765: ldo15 { + regulator-name = "vreg_l15b_0p765"; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + regulator-initial-mode = ; + }; + + vreg_l16b_1p1: ldo16 { + regulator-name = "vreg_l16b_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + }; + + vreg_l17b_1p7: ldo17 { + regulator-name = "vreg_l17b_1p7"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name = "vreg_l18b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name = "vreg_l19b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-l12-supply = <&vreg_s1b_1p872>; + vdd-l2-l8-supply = <&vreg_s1b_1p872>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply = <&vreg_bob_3p296>; + vdd-l10-supply = <&vreg_s7b_0p972>; + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_2p19: smps1 { + regulator-name = "vreg_s1c_2p19"; + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vreg_s2c_0p752: smps2 { + regulator-name = "vreg_s2c_0p752"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + }; + + vreg_s5c_0p752: smps5 { + regulator-name = "vreg_s5c_0p752"; + regulator-min-microvolt = <465000>; + regulator-max-microvolt = <1050000>; + }; + + vreg_s7c_0p752: smps7 { + regulator-name = "vreg_s7c_0p752"; + regulator-min-microvolt = <465000>; + regulator-max-microvolt = <800000>; + }; + + vreg_s9c_1p084: smps9 { + regulator-name = "vreg_s9c_1p084"; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p62: ldo2 { + regulator-name = "vreg_l2c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l3c_2p8: ldo3 { + regulator-name = "vreg_l3c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p62: ldo4 { + regulator-name = "vreg_l4c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p62: ldo5 { + regulator-name = "vreg_l5c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name = "vreg_l6c_2p96"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p62: ldo8 { + regulator-name = "vreg_l8c_1p62"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name = "vreg_l10c_0p88"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-name = "vreg_l11c_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p65: ldo12 { + regulator-name = "vreg_l12c_1p65"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_2p7: ldo13 { + regulator-name = "vreg_l13c_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob_3p296: bob { + regulator-name = "vreg_bob_3p296"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + }; +}; + +&gcc { + protected-clocks = , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs6490/a660_zap.mbn"; +}; + +/* Pin 3, 5 in 40-pin connector */ +&i2c1 { + status = "okay"; +}; + +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + lt9611_codec: hdmi-bridge@39 { + compatible = "lontium,lt9611"; + reg = <0x39>; + + interrupts-extended = <&tlmm 20 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vreg_lt9611_3v3>; + vcc-supply = <&vreg_lt9611_3v3>; + + pinctrl-0 = <<9611_irq_pin>, + <<9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&lpass_audiocc { + compatible = "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp { + status = "okay"; +}; + +&mdss_dp_out { + data-lanes = <0 1>; + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + +&mdss_dsi { + vdda-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi_phy { + vdds-supply = <&vreg_l10c_0p88>; + + status = "okay"; +}; + +&pcie0 { + perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&pcie0_clkreq_n>, + <&pcie0_reset_n>, + <&pcie0_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_clkreq_n>, + <&pcie1_reset_n>, + <&pcie1_wake_n>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&pm7325_gpios { + kypd_vol_up_n: kypd-vol-up-n-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm7325_temp_alarm { + io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + quiet-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + sdm-skin-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pm8350c_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_INDICATOR; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; +}; + +&pmk8350_rtc { + allow-set-time; + + status = "okay"; +}; + +&pmk8350_vadc { + channel@3 { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@44 { + reg = ; + label = "xo_therm"; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg = ; + label = "pm7325_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + channel@144 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_quiet_therm"; + }; + + channel@146 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + label = "pm7325_sdm_skin_therm"; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + + status = "okay"; +}; + +&qupv3_id_1 { + firmware-name = "qcom/qcm6490/qupv3fw.elf"; + + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs6490/Thundercomm/RubikPi3/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs6490/cdsp.mbn"; + + status = "okay"; +}; + +/* WIFI part of the AP6256 connected with SDIO */ +&sdhc_2 { + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_2p96>; + + non-removable; + keep-power-in-suspend; + /delete-property/ cd-gpios; + + status = "okay"; +}; + +/* Pin 19, 21, 23, 24 in 40-pin connector */ +&spi12 { + status = "okay"; +}; + +&thermal_zones { + cpu0-thermal { + trips { + cpu_tepid: cpu-tepid { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_warm: cpu-warm { + temperature = <80000>; + hysteresis = <5000>; + type = "active"; + }; + }; + + cooling-maps { + map-cpu-tepid { + cooling-device = <&fan0 1 1>; + trip = <&cpu_tepid>; + }; + + map-cpu-warm { + cooling-device = <&fan0 2 2>; + trip = <&cpu_warm>; + }; + + map-cpu-hot { + cooling-device = <&fan0 3 3>; + trip = <&cpu0_alert0>; + }; + }; + }; +}; + +/* Pin 8, 10 in 40-pin connector */ +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +/* BT part of the AP6256 connected with UART */ +&uart7 { + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-1 = <&qup_uart7_sleep_cts>, + <&qup_uart7_sleep_rts>, + <&qup_uart7_sleep_tx>, + <&qup_uart7_sleep_rx>; + pinctrl-names = "default", + "sleep"; + + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&sleep_clk>; + clock-names = "lpo"; + device-wakeup-gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&tlmm 137 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&bt_device_wake>, + <&bt_host_wake>, + <&bt_reset>; + pinctrl-names = "default"; + vbat-supply = <&vreg_wifi_1v8>; + vddio-supply = <&vreg_wifi_1v8>; + max-speed = <3000000>; + }; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda33-supply = <&vreg_l2b_3p072>; + vdda18-supply = <&vreg_l1c_1p8>; + + status = "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p912>; + + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vreg_l10c_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p072>; + + status = "okay"; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l7b_2p952>; + vcc-max-microamp = <800000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <900000>; + vccq2-supply = <&vreg_l9b_1p2>; + vccq2-max-microamp = <900000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + status = "okay"; +}; + +&venus { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in kodiak.dtsi */ +&pcie0_clkreq_n { + bias-pull-up; + drive-strength = <8>; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <8>; +}; + +&pm8350c_gpios { + fan_pwm_out_default: fan-pwm-out-default-state { + pins = "gpio8"; + function = "func1"; + power-source = <1>; + drive-push-pull; + output-high; + qcom,drive-strength = ; + }; +}; + +&qup_uart7_cts { + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + bias-disable; + drive-strength = <2>; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + bias-disable; + drive-strength = <2>; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + +&tlmm { + pcie1_reset_n: pcie1-reset-n-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <8>; + output-low; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + usb_eth_power: usb-eth-power-state { + pins = "gpio7"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + wifi_reset_active: wifi-reset-active-state { + pins = "gpio16"; + function = "gpio"; + drive-strength = <8>; + output-high; + bias-disable; + }; + + bt_reset: bt-reset-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio20"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio21"; + function = "gpio"; + drive-strength = <8>; + output-high; + input-disable; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts-state { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts-state { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx-state { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx-state { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + wifi_host_wake: wifi-host-wake-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + bt_device_wake: bt-device-wake-state { + pins = "gpio39"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + usb1_sbu_default: usb1-sbu-state { + sel-pins { + pins = "gpio52"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + oe-n-pins { + pins = "gpio53"; + function = "gpio"; + drive-strength = <8>; + output-high; + bias-disable; + }; + }; + + m2_vcc_pin: m2-vcc-state { + pins = "gpio56"; + function = "gpio"; + drive-strength = <8>; + output-high; + input-disable; + }; + + lt9611_vcc_pin: lt9611-vcc-pin-state { + pins = "gpio83"; + function = "gpio"; + drive-strength = <8>; + output-high; + input-disable; + }; + + usbhub_power: usbhub-power-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + pcie0_reset_n: pcie0-reset-n-state { + pins = "gpio87"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + wifi_power_on: wifi-power-on-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + usbhub_rest: usbhub-reset-state { + pins = "gpio136"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + bt_host_wake: bt-host-wake-state { + pins = "gpio137"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; +}; From d16ffac771715a8c94611b6f8088a3e800bcf5bf Mon Sep 17 00:00:00 2001 From: Riccardo Mereu Date: Thu, 20 Nov 2025 16:58:20 +0100 Subject: [PATCH 269/757] dt-bindings: vendor-prefixes: Add Arduino name Add entry for Arduino SRL (https://arduino.cc) Signed-off-by: Riccardo Mereu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251120155825.121483-2-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b7c6c528e018..2de0af95f5e6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -158,6 +158,8 @@ patternProperties: description: Arctic Sand "^arcx,.*": description: arcx Inc. / Archronix Inc. + "^arduino,.*": + description: Arduino SRL "^argon40,.*": description: Argon 40 Technologies Limited "^ariaboard,.*": From 311d173da672397a58498841299ec613ff9eb96b Mon Sep 17 00:00:00 2001 From: Riccardo Mereu Date: Thu, 20 Nov 2025 16:58:23 +0100 Subject: [PATCH 270/757] dt-bindings: arm: qcom: Add arduino imola, UnoQ codename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document Arduino imola, UnoQ codename. Arduino UnoQ combines Qualcomm Dragonwing™ QRB2210 microprocessor with STMicroelectronics STM32U585 microcontroller. Signed-off-by: Riccardo Mereu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251120155825.121483-5-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index acba980bdf4a..cade15d098bc 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -342,6 +342,7 @@ properties: - description: Qualcomm Technologies, Inc. Robotics RB1 items: - enum: + - arduino,imola - qcom,qrb2210-rb1 - const: qcom,qrb2210 - const: qcom,qcm2290 From 925ac1f6ec75a773e0ec8b91673b647f6d456ccb Mon Sep 17 00:00:00 2001 From: Riccardo Mereu Date: Thu, 20 Nov 2025 16:58:24 +0100 Subject: [PATCH 271/757] arm64: dts: qcom: agatti: add uart2 node uart2 is used in Arduino UnoQ as an interface between microprocessor and microcontroller. Signed-off-by: Riccardo Mereu Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251120155825.121483-6-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 8bf5c5583fc2..992a157c571f 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -562,6 +562,13 @@ bias-disable; }; + qup_uart2_default: qup-uart2-default-state { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-disable; + }; + qup_uart3_default: qup-uart3-default-state { pins = "gpio8", "gpio9", "gpio10", "gpio11"; function = "qup3"; @@ -1315,6 +1322,23 @@ status = "disabled"; }; + uart2: serial@4a88000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x04a88000 0x0 0x4000>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-names = "default"; + interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG + &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + status = "disabled"; + }; + i2c3: i2c@4a8c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x04a8c000 0x0 0x4000>; From 3f745bc0f11f66465e3fa19eb0c808c5b39cb0e5 Mon Sep 17 00:00:00 2001 From: Riccardo Mereu Date: Thu, 20 Nov 2025 16:58:25 +0100 Subject: [PATCH 272/757] arm64: dts: qcom: qrb2210: add dts for Arduino unoq MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Arduino UnoQ is a single-board computer combining Qualcomm Dragonwing™ QRB2210 microprocessor with STMicroelectronics STM32U585 microcontroller. Support to a simply boot to shell environment includes: - UART, I2C, SPI - onboard LEDS - eMMC - WLAN and BT Signed-off-by: Riccardo Mereu Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251120155825.121483-7-r.mereu.kernel@arduino.cc Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qrb2210-arduino-imola.dts | 459 ++++++++++++++++++ 2 files changed, 460 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f139e5334527..ce29b26473b3 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -146,6 +146,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-arduino-imola.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb diff --git a/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts new file mode 100644 index 000000000000..197ab6eb1666 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb2210-arduino-imola.dts @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (c) 2025, Arduino SRL + */ + +/dts-v1/; + +#include +#include "agatti.dtsi" +#include "pm4125.dtsi" + +/delete-node/ &cont_splash_memory; + +/ { + model = "Arduino UnoQ"; + compatible = "arduino,imola", "qcom,qrb2210", "qcom,qcm2290"; + chassis-type = "embedded"; + + aliases { + serial0 = &uart4; + serial1 = &uart2; + serial2 = &uart3; + sdhc1 = &sdhc_1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + pinctrl-0 = <&key_volp_n>, <&key_vold_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = ; + gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + linux,code = ; + gpios = <&tlmm 36 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led-bt { + label = "unoq:bt-blue2"; + function = LED_FUNCTION_BLUETOOTH; + color = ; + gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + + led-panic { + label = "unoq:panic-red2"; + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + + led-wlan { + label = "unoq:wlan-green2"; + function = LED_FUNCTION_WLAN; + color = ; + gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + ledb: led-user-blue { + label = "unoq:user-blue1"; + gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>; + color = ; + }; + + ledg: led-user-green { + label = "unoq:user-green1"; + gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; + color = ; + }; + + ledr: led-user-red { + label = "unoq:user-red1"; + gpios = <&tlmm 41 GPIO_ACTIVE_HIGH>; + color = ; + }; + }; + + multi-led { + compatible = "leds-group-multicolor"; + color = ; + function = LED_FUNCTION_INDICATOR; + leds = <&ledr>, <&ledg>, <&ledb>; + }; + + /* PM4125 charger out, supplied by VBAT */ + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&gpi_dma0 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcm2290/a702_zap.mbn"; +}; + +&i2c0 { + clock-frequency = <100000>; + + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + + status = "okay"; +}; + +&pm4125_vbus { + regulator-min-microamp = <500000>; + regulator-max-microamp = <500000>; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcm2290/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/qcm2290/modem.mbn"; + + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm4125_s3>; + vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>; + vdd_l13_l14_l15_l16-supply = <&pm4125_s4>; + + pm4125_s3: s3 { + /* 0.4V-1.6625V -> 1.3V (Power tree requirements) */ + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-boot-on; + }; + + pm4125_s4: s4 { + /* 1.2V-2.35V -> 2.05V (Power tree requirements) */ + regulator-min-microvolt = <2072000>; + regulator-max-microvolt = <2072000>; + regulator-boot-on; + }; + + pm4125_l2: l2 { + /* LPDDR4X VDD2 */ + regulator-min-microvolt = <1136000>; + regulator-max-microvolt = <1136000>; + regulator-always-on; + regulator-boot-on; + }; + + pm4125_l3: l3 { + /* LPDDR4X VDDQ */ + regulator-min-microvolt = <616000>; + regulator-max-microvolt = <616000>; + regulator-always-on; + regulator-boot-on; + }; + + pm4125_l4: l4 { + /* max = 3.05V -> max = 2.7 to disable 3V signaling (SDHCI2) */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2700000>; + regulator-allow-set-load; + }; + + pm4125_l5: l5 { + /* CSI/DSI */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm4125_l6: l6 { + /* DRAM PLL */ + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <928000>; + regulator-always-on; + regulator-boot-on; + }; + + pm4125_l7: l7 { + /* Wi-Fi CX */ + regulator-min-microvolt = <664000>; + regulator-max-microvolt = <664000>; + }; + + pm4125_l10: l10 { + /* Wi-Fi RFA */ + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l11: l11 { + /* ANX7625 DVDD1P0V/AVDD1P0V */ + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + pm4125_l12: l12 { + /* USB PHYs */ + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <928000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm4125_l13: l13 { + /* USB/QFPROM/PLLs */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm4125_l14: l14 { + /* SDHCI1 EMMC VCCQ */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + /* Broken hardware, never turn it off! */ + regulator-always-on; + }; + + pm4125_l15: l15 { + /* VDDIO */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-always-on; + regulator-boot-on; + }; + + pm4125_l20: l20 { + /* SDHCI1 EMMC */ + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + regulator-allow-set-load; + }; + + pm4125_l21: l21 { + /* USB HS */ + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3300000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm4125_l22: l22 { + /* Wi-Fi VDD */ + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + mmc-hs400-1_8v; + mmc-hs200-1_8v; + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; + +&spi5 { + status = "okay"; + + spidev@0 { + reg = <0>; + compatible = "arduino,unoq-mcu"; + pinctrl-0 = <&spidev_cs>; + pinctrl-names = "default"; + }; +}; + +&tlmm { + spidev_cs: spidev-cs-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + }; + + jmisc_gpio18: jmisc-gpio18-state { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + jmisc_gpio28: jmisc-gpio28-state { + pins = "gpio28"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + key_vold_n: key-vold-n-state { + pins = "gpio36"; + function = "gpio"; + bias-pull-up; + output-disable; + }; + + key_volp_n: key-volp-n-state { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; + output-disable; + }; + + jmisc_gpio98: jmisc-gpio98-state { + pins = "gpio98"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + jmisc_gpio99: jmisc-gpio99-state { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + jmisc_gpio100: jmisc-gpio100-state { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + jmisc_gpio101: jmisc-gpio101-state { + pins = "gpio101"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&uart2 { + status = "okay"; +}; + +/* UART connected to Bluetooth */ +&uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3988-bt"; + + vddio-supply = <&pm4125_l15>; + vddxo-supply = <&pm4125_l13>; + vddrf-supply = <&pm4125_l10>; + vddch0-supply = <&pm4125_l22>; + enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + max-speed = <3000000>; + }; +}; + +/* UART exposed in JCTL */ +&uart4 { + compatible = "qcom,geni-debug-uart"; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_hsphy { + vdd-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + vdda-phy-dpdm-supply = <&pm4125_l21>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + + status = "okay"; +}; + +&wifi { + vdd-0.8-cx-mx-supply = <&pm4125_l7>; + vdd-1.8-xo-supply = <&pm4125_l13>; + vdd-1.3-rfa-supply = <&pm4125_l10>; + vdd-3.3-ch0-supply = <&pm4125_l22>; + qcom,ath10k-calibration-variant = "ArduinoImola"; + firmware-name = "qcm2290"; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <38400000>; +}; From 60fb18fbc234efb2d59472a889282dba2df3402a Mon Sep 17 00:00:00 2001 From: George Moussalem Date: Mon, 18 Aug 2025 15:33:47 +0400 Subject: [PATCH 273/757] arm64: dts: qcom: ipq5018: Remove tsens v1 fallback compatible Remove qcom,tsens-v1 as fallback compatible since this IP has no RPM and, as such, must use its own init routine available in the driver. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem Link: https://lore.kernel.org/r/20250818-ipq5018-tsens-fix-v1-2-0f08cf09182d@outlook.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index f024b3cba33f..721b642acf8e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -340,7 +340,7 @@ }; tsens: thermal-sensor@4a9000 { - compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1"; + compatible = "qcom,ipq5018-tsens"; reg = <0x004a9000 0x1000>, <0x004a8000 0x1000>; From 0c1d1591f898d54eaa4c8f2a1535ab21bf4e42e4 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Sun, 16 Nov 2025 04:12:35 +0300 Subject: [PATCH 274/757] arm64: dts: qcom: sdm630: Add missing MDSS reset If the OS does not support recovering the state left by the bootloader it needs a way to reset display hardware, so that it can start from a clean state. Add a reference to the relevant reset. It fixes display init issue appeared in Linux v6.17: without reset device boots into black screen and you need to turn display off/on to "fix" it. Also sometimes it can boot into solid blue color with these messages in kernel log: hw recovery is not complete for ctl:2 [drm:dpu_encoder_phys_vid_prepare_for_kickoff:569] [dpu error]enc33 intf1 ctl 2 reset failure: -22 [drm:dpu_encoder_frame_done_timeout:2727] [dpu error]enc33 frame done timeout Fixes: 0e789b491ba0 ("pmdomain: core: Leave powered-on genpds on until sync_state") Cc: stable@vger.kernel.org # 6.17 Signed-off-by: Alexey Minnekhanov Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251116-sdm660-mdss-reset-v2-3-6219bec0a97f@postmarketos.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 7f2650bc3ac1..a13a747b0c88 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1563,6 +1563,7 @@ reg-names = "mdss_phys", "vbif_phys"; power-domains = <&mmcc MDSS_GDSC>; + resets = <&mmcc MDSS_BCR>; clocks = <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_AXI_CLK>, From c9b98b9dad9749bf2eb7336a6fca31a6af1039d7 Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Tue, 18 Nov 2025 15:52:25 +0100 Subject: [PATCH 275/757] arm64: dts: qcom: sdm845-oneplus: Don't mark ts supply boot-on The touchscreen isn't enabled by bootloader and doesn't need to be enabled at boot, only when the driver probes, thus remove the regulator-boot-on property. Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices") Signed-off-by: Casey Connolly Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251118-dts-oneplus-regulators-v2-1-3e67cea1e4e7@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 9d1ebfaaa2be..da21e435e857 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -166,7 +166,6 @@ gpio = <&tlmm 88 0>; enable-active-high; - regulator-boot-on; }; panel_vci_3v3: panel-vci-3v3-regulator { From 45d1f42d3e84b5880cf9fab1eb24a7818320eeb7 Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Tue, 18 Nov 2025 15:52:26 +0100 Subject: [PATCH 276/757] arm64: dts: qcom: sdm845-oneplus: Don't keep panel regulator always on The panel regulator doesn't need to be always on, so remove this property. Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices") Signed-off-by: Casey Connolly Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251118-dts-oneplus-regulators-v2-2-3e67cea1e4e7@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index da21e435e857..fb97b3836c75 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -291,7 +291,6 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; - regulator-always-on; }; vreg_l17a_1p3: ldo17 { From ad33ee060be46794a03d033894c9db3a9d6c1a0f Mon Sep 17 00:00:00 2001 From: Casey Connolly Date: Tue, 18 Nov 2025 15:52:27 +0100 Subject: [PATCH 277/757] arm64: dts: qcom: sdm845-oneplus: Mark l14a regulator as boot-on This regulator is used only for the display, which is enabled by the bootloader and left on for continuous splash. Mark it as such. Fixes: 288ef8a42612 ("arm64: dts: sdm845: add oneplus6/6t devices") Signed-off-by: Casey Connolly Signed-off-by: David Heidelberg Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251118-dts-oneplus-regulators-v2-3-3e67cea1e4e7@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index fb97b3836c75..5b121ea5520f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -291,6 +291,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-boot-on; }; vreg_l17a_1p3: ldo17 { From 2ffe611f896857ef542e60f9e1b3bc1869faabdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Mon, 17 Nov 2025 18:17:54 +0100 Subject: [PATCH 278/757] arm64: dts: qcom: msm8917: add reset for display subsystem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add reset for display subsystem. Reviewed-by: Konrad Dybcio Signed-off-by: Barnabás Czémán Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251117-mdss-resets-msm8917-msm8937-v2-3-a7e9bbdaac96@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8917.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qcom/msm8917.dtsi index 8a642fce2e40..6251189b8e6d 100644 --- a/arch/arm64/boot/dts/qcom/msm8917.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -996,7 +996,7 @@ clock-names = "iface", "bus", "vsync"; - + resets = <&gcc GCC_MDSS_BCR>; interrupts = ; interrupt-controller; From 3ad80ba51eb931c7fcba0bec5b1c9ca5f6d99cea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20Cz=C3=A9m=C3=A1n?= Date: Mon, 17 Nov 2025 18:17:55 +0100 Subject: [PATCH 279/757] arm64: dts: qcom: msm8937: add reset for display subsystem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add reset for display subsystem. Reviewed-by: Konrad Dybcio Signed-off-by: Barnabás Czémán Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251117-mdss-resets-msm8917-msm8937-v2-4-a7e9bbdaac96@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8937.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi index b93621080989..c94eb14e31bd 100644 --- a/arch/arm64/boot/dts/qcom/msm8937.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi @@ -1044,6 +1044,7 @@ clock-names = "iface", "bus", "vsync"; + resets = <&gcc GCC_MDSS_BCR>; interrupts = ; interrupt-controller; From e50c63e89236beb249507f986c3458b2b670cfd6 Mon Sep 17 00:00:00 2001 From: Tingguo Cheng Date: Fri, 14 Nov 2025 00:13:03 -0800 Subject: [PATCH 280/757] arm64: dts: qcom: hamoa-iot-evk: enable PWM RG LEDs Add RED and GREEN LED channels for the RGB device connected to PMC8380C PWM-LED pins. Omit BLUE channel to match default hardware setup where it's tied to EDL indicator. Signed-off-by: Tingguo Cheng Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251114-add-rgb-led-for-hamoa-iot-evk-v3-1-5df1fcd68374@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index bac531421292..aa0e0857e993 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "hamoa-iot-som.dtsi" #include @@ -959,6 +960,28 @@ }; }; +&pm8550_pwm { + status = "okay"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + }; +}; + &pmc8380_5_gpios { usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { pins = "gpio8"; From 512716f69610d81db958b781132370731c69e874 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Wed, 12 Nov 2025 12:21:23 +0800 Subject: [PATCH 281/757] arm64: dts: qcom: hamoa-iot-evk: Add backlight support for eDP panel The backlight on the Hamoa IoT EVK is controlled through a PWM signal. Aligned with other x1e80100-based platforms: the PWM signal is controlled by PMK8550, and the backlight enable signal is handled by PMC8380. Describe the backlight device and connect it to the eDP panel to allow for brightness control. Reviewed-by: Abel Vesa Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251112-hamoa_dvt_backlight-v3-1-f35b44af7fc4@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index aa0e0857e993..898b92627f84 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -19,6 +19,16 @@ serial1 = &uart14; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pmk8550_pwm 0 5000000>; + enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>; + power-supply = <&vreg_edp_bl>; + + pinctrl-0 = <&edp_bl_en>, <&edp_bl_pwm>; + pinctrl-names = "default"; + }; + wcd938x: audio-codec { compatible = "qcom,wcd9385-codec"; @@ -211,6 +221,22 @@ regulator-boot-on; }; + vreg_edp_bl: regulator-edp-bl { + compatible = "regulator-fixed"; + + regulator-name = "VBL9"; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + gpio = <&pmc8380_3_gpios 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&edp_bl_reg_en>; + pinctrl-names = "default"; + + regulator-boot-on; + }; + vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; @@ -867,6 +893,8 @@ aux-bus { panel { compatible = "edp-panel"; + + backlight = <&backlight>; power-supply = <&vreg_edp_3p3>; port { @@ -982,6 +1010,21 @@ }; }; +&pmc8380_3_gpios { + edp_bl_en: edp-bl-en-state { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + input-disable; + output-enable; + }; + + edp_bl_reg_en: edp-bl-reg-en-state { + pins = "gpio10"; + function = "normal"; + }; +}; + &pmc8380_5_gpios { usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { pins = "gpio8"; @@ -993,6 +1036,17 @@ }; }; +&pmk8550_gpios { + edp_bl_pwm: edp-bl-pwm-state { + pins = "gpio5"; + function = "func3"; + }; +}; + +&pmk8550_pwm { + status = "okay"; +}; + &smb2360_0 { status = "okay"; }; From c0c32a9e3493f9987fd6635bbaf7260dfc09ee29 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Mon, 10 Nov 2025 21:55:06 +0300 Subject: [PATCH 282/757] arm64: dts: qcom: sdm630/660: Add CDSP-related nodes In order to enable CDSP support for SDM660 SoC: * add shared memory p2p nodes for CDSP * add CDSP-specific smmu node * add CDSP peripheral image loader node Memory region for CDSP in SDM660 occupies the same spot as TZ buffer mem defined in sdm630.dtsi (which does not have CDSP). In sdm660.dtsi replace buffer_mem inherited from SDM630 with cdsp_region, which is also larger in size. SDM636 also doesn't have CDSP, so remove inherited from sdm660.dtsi related nodes and add buffer_mem back. Signed-off-by: Nickolay Goppen Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251110-qcom-sdm660-cdsp-adsp-dts-v3-1-d1f1c86e2e6d@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm636.dtsi | 23 ++-- arch/arm64/boot/dts/qcom/sdm660.dtsi | 161 +++++++++++++++++++++++++++ 3 files changed, 176 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index a13a747b0c88..b47a62b721b8 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -563,7 +563,7 @@ }; }; - soc@0 { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; diff --git a/arch/arm64/boot/dts/qcom/sdm636.dtsi b/arch/arm64/boot/dts/qcom/sdm636.dtsi index ae15d81fa3f9..38e6e3bfc3ce 100644 --- a/arch/arm64/boot/dts/qcom/sdm636.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm636.dtsi @@ -7,15 +7,20 @@ #include "sdm660.dtsi" -/* - * According to the downstream DTS, - * 636 is basically a 660 except for - * different CPU frequencies, Adreno - * 509 instead of 512 and lack of - * turing IP. These differences will - * be addressed when the aforementioned - * peripherals will be enabled upstream. - */ +/delete-node/ &remoteproc_cdsp; +/delete-node/ &cdsp_smmu; +/delete-node/ &cdsp_region; + +/ { + /delete-node/ smp2p-cdsp; + + reserved-memory { + buffer_mem: tzbuffer@94a00000 { + reg = <0x0 0x94a00000 0x00 0x100000>; + no-map; + }; + }; +}; &adreno_gpu { compatible = "qcom,adreno-509.0", "qcom,adreno"; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index ef4a563c0feb..c252f248ef15 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -9,6 +9,37 @@ #include "sdm630.dtsi" +/delete-node/ &buffer_mem; + +/ { + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts = ; + mboxes = <&apcs_glb 30>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + cdsp_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + cdsp_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + reserved-memory { + cdsp_region: cdsp@94a00000 { + reg = <0x0 0x94a00000 0x00 0x600000>; + no-map; + }; + }; +}; + &adreno_gpu { compatible = "qcom,adreno-512.0", "qcom,adreno"; operating-points-v2 = <&gpu_sdm660_opp_table>; @@ -247,6 +278,136 @@ <0>; }; +&soc { + cdsp_smmu: iommu@5180000 { + compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; + reg = <0x5180000 0x40000>; + #iommu-cells = <1>; + + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK>; + clock-names = "bus"; + + power-domains = <&gcc HLOS1_VOTE_TURING_ADSP_GDSC>; + + }; + + remoteproc_cdsp: remoteproc@1a300000 { + compatible = "qcom,sdm660-cdsp-pas"; + reg = <0x1a300000 0x00100>; + interrupts-extended = <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + memory-region = <&cdsp_region>; + power-domains = <&rpmpd SDM660_VDDCX>; + power-domain-names = "cx"; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts = ; + + label = "cdsp"; + mboxes = <&apcs_glb 29>; + qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&cdsp_smmu 3>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&cdsp_smmu 4>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&cdsp_smmu 5>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&cdsp_smmu 6>; + }; + + compute-cb@9 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <9>; + iommus = <&cdsp_smmu 7>; + }; + + compute-cb@10 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <10>; + iommus = <&cdsp_smmu 8>; + }; + + compute-cb@11 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <11>; + iommus = <&cdsp_smmu 9>; + }; + + compute-cb@12 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <12>; + iommus = <&cdsp_smmu 10>; + }; + + compute-cb@13 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <13>; + iommus = <&cdsp_smmu 11>; + }; + }; + }; + }; +}; + &tlmm { compatible = "qcom,sdm660-pinctrl"; }; From a044cc859dc93c7a32f0c24745242bd3f0a04db5 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Mon, 10 Nov 2025 21:55:07 +0300 Subject: [PATCH 283/757] arm64: dts: qcom: sdm630: Add missing vote clock and GDSC to lpass_smmu Add missing vote clock and GDSC to lpass_smmu node to make sure the required resources are enabled before attempting to access the hardware. Reviewed-by: Konrad Dybcio Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20251110-qcom-sdm660-cdsp-adsp-dts-v3-2-d1f1c86e2e6d@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index b47a62b721b8..502feaaa4aaf 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1217,6 +1217,11 @@ reg = <0x05100000 0x40000>; #iommu-cells = <1>; + clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; + clock-names = "bus"; + + power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; + #global-interrupts = <2>; interrupts = , From af2ce7296643767a81c96d12a8d367afc5091df2 Mon Sep 17 00:00:00 2001 From: Nickolay Goppen Date: Mon, 10 Nov 2025 21:55:08 +0300 Subject: [PATCH 284/757] arm64: dts: qcom: sdm630: Add FastRPC nodes to ADSP Add FastRPC subnode with compute-cb subnodes to ADSP node. Signed-off-by: Nickolay Goppen Link: https://lore.kernel.org/r/20251110-qcom-sdm660-cdsp-adsp-dts-v3-3-d1f1c86e2e6d@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 502feaaa4aaf..e38d9648a1ac 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2343,6 +2343,39 @@ }; }; }; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + qcom,non-secure-domain; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&lpass_smmu 3>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&lpass_smmu 7>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&lpass_smmu 8>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&lpass_smmu 9>; + }; + }; }; }; From ec593a86dfa1bbb5ef02165711f7ed8bb1046e29 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Fri, 7 Nov 2025 21:55:21 +0530 Subject: [PATCH 285/757] arm64: dts: qcom: qcs8300: Add support for camss Add changes to support the camera subsystem on the QCS8300. Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Signed-off-by: Vikram Sharma Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251107162521.511536-3-quic_vikramsa@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 172 +++++++++++++++++++++++++++ 1 file changed, 172 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 96bfc35f955e..e7b12b01928d 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -4784,6 +4784,178 @@ #power-domain-cells = <1>; }; + camss: isp@ac78000 { + compatible = "qcom,qcs8300-camss"; + + reg = <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0xf00>, + <0x0 0xac7c000 0x0 0xf00>, + <0x0 0xac84000 0x0 0xf00>, + <0x0 0xac88000 0x0 0xf00>, + <0x0 0xac8c000 0x0 0xf00>, + <0x0 0xac90000 0x0 0xf00>, + <0x0 0xac94000 0x0 0xf00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x400>, + <0x0 0xacad000 0x0 0x400>, + <0x0 0xacae000 0x0 0x400>, + <0x0 0xac4d000 0x0 0xf000>, + <0x0 0xac60000 0x0 0xf000>, + <0x0 0xac85000 0x0 0xd00>, + <0x0 0xac89000 0x0 0xd00>, + <0x0 0xac8d000 0x0 0xd00>, + <0x0 0xac91000 0x0 0xd00>, + <0x0 0xac95000 0x0 0xd00>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x2400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + }; + }; + camcc: clock-controller@ade0000 { compatible = "qcom,qcs8300-camcc"; reg = <0x0 0x0ade0000 0x0 0x20000>; From 3af51501e2b8c87564b5cda43b0e5c316cf54717 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Mon, 3 Nov 2025 18:51:40 +0200 Subject: [PATCH 286/757] arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks It seems the USB combo SS1 and SS2 ref clocks have another gate, unlike the SS0. These gates are part of the TCSR clock controller. At least on Dell XPS 13 (9345), if the ref clock provided by the TCSR clock controller for SS1 PHY is disabled on the clk_disable_unused late initcall, the PHY fails to initialize. It doesn't happen on the SS0 PHY and the SS2 is not used on this device. This doesn't seem to be a problem on CRD though. It might be that the RPMh has a vote for it from some other consumer and does not actually disable it when ther kernel drops its vote. Either way, these TCSR provided clocks seem to be the correct ones for the SS1 and SS2, so use them instead. Fixes: 4af46b7bd66f ("arm64: dts: qcom: x1e80100: Add USB nodes") Signed-off-by: Abel Vesa Reviewed-by: Neil Armstrong Reviewed-by: Taniya Das Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 120993685776..51ad2b2e6375 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -2940,7 +2940,7 @@ reg = <0 0x00fda000 0 0x4000>; clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_USB4_1_CLKREF_EN>, <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; clock-names = "aux", @@ -3011,7 +3011,7 @@ reg = <0 0x00fdf000 0 0x4000>; clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, + <&tcsr TCSR_USB4_2_CLKREF_EN>, <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; clock-names = "aux", From 00d3dbc4744dc3213c150fb33c47697a7c60fb2f Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 22 Oct 2025 10:31:40 +0300 Subject: [PATCH 287/757] arm64: dts: renesas: rzt2h-n2h-evk: Add note about SD1 1.8V modes 1.8V operation of SD1 requires the jumper to be placed on the correct pins of a connector on these Evaluation Kits. 1.8V is needed to achieve the higher rated speeds like SDR104. Add a note about it to make sure no one else spends too much time figuring this out. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251022073141.1989762-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts | 3 +++ arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index b7706d0bc3aa..d1474f1bd523 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -26,6 +26,9 @@ * P17_4 = SD1_CD; SW2[3] = ON * P08_5 = SD1_PWEN; SW2[3] = ON * P08_6 = SD1_IOVS; SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON + * To enable proper operation in 1.8V modes, CN77 must have pins 2 and 3 + * connected by the jumper. This connects SD1 power-supply control IC output + * back to VCC1833_7. */ #define SD1_MICRO_SD 1 diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 17c0c79fbd96..eaf73868783b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -30,6 +30,9 @@ /* * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON * P08_6 = SD1_IOVS; DSW5[3] = ON + * To enable proper operation in 1.8V modes, JP21 must have pins 2 and 3 + * connected by the jumper. This connects SD1 power-supply control IC output + * back to VCC1833_7. */ #define SD1_MICRO_SD 1 From 0154078db6abbc8f1adc216e1b20472f0b50aaf8 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 23 Oct 2025 22:23:12 +0100 Subject: [PATCH 288/757] arm64: dts: renesas: r9a09g057: Add FCPV and VSPD nodes Add FCPV and VSPD nodes to RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251023212314.679303-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 4df32d7e9998..59dc6025749b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1348,6 +1348,30 @@ }; }; }; + + fcpvd: fcp@16470000 { + compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + }; + + vspd: vsp@16480000 { + compatible = "renesas,r9a09g057-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x16480000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,fcp = <&fcpvd>; + }; }; stmmac_axi_setup: stmmac-axi-config { From ebb6adecb992d5c6f16a830b9361092a1e791755 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 23 Oct 2025 22:23:13 +0100 Subject: [PATCH 289/757] arm64: dts: renesas: r9a09g057: Add DU and DSI nodes Add DU and DSI nodes to RZ/V2H(P) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251023212314.679303-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 59dc6025749b..c09578d2c962 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1349,6 +1349,71 @@ }; }; + dsi: dsi@16430000 { + compatible = "renesas,r9a09g057-mipi-dsi"; + reg = <0 0x16430000 0 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, + <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, + <&cpg CPG_MOD 0xeb>; + clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg 0xd8>, <&cpg 0xd7>; + reset-names = "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + }; + }; + }; + }; + + du: display@16460000 { + compatible = "renesas,r9a09g057-du"; + reg = <0 0x16460000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + fcpvd: fcp@16470000 { compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv"; reg = <0 0x16470000 0 0x10000>; From 947acdadcae0b1759f082266893d277cfb5b29c1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 23 Oct 2025 22:23:14 +0100 Subject: [PATCH 290/757] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable DU and DSI Enable DU, DSI and adv7535 HDMI encoder on RZ/V2H Evaluation Kit. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251023212314.679303-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 445fce156f73..90d93116fabd 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -35,6 +35,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + keys: keys { compatible = "gpio-keys"; @@ -103,12 +114,36 @@ #clock-cells = <0>; clock-frequency = <32768>; }; + + /* 12MHz crystal for ADV7535 */ + y1: y1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -174,6 +209,42 @@ clock-frequency = <400000>; status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + interrupt-parent = <&pinctrl>; + interrupts = ; + clocks = <&y1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &i2c6 { From 71270e792c72da7c0078a0af67f7f15aa24c1403 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Sat, 1 Nov 2025 16:29:51 +0900 Subject: [PATCH 291/757] arm64: dts: renesas: r9a09g057h48-kakip: Enable SPI NOR Flash This enables W25Q256JWPIM NOR Flash connected to XSPI. Additionally, this adds fixed 1.8V regulator node (`reg_1p8v`) required for NOR Flash. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251101072951.2681630-1-iwamatsu@nigauri.org Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g057h48-kakip.dts | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts index adf3ab8aef2b..e8523bb6705a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -30,6 +30,15 @@ reg = <0x0 0x48000000 0x1 0xF8000000>; }; + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; @@ -112,6 +121,18 @@ pinmux = ; /* SD0_CD */ }; }; + + xspi_pins: xspi0 { + ctrl { + pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; + output-enable; + }; + + io { + pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3"; + renesas,output-impedance = <3>; + }; + }; }; &qextal_clk { @@ -134,3 +155,21 @@ status = "okay"; }; + +&xspi { + pinctrl-0 = <&xspi_pins>; + pinctrl-names = "default"; + assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>; + assigned-clock-rates = <133333334>; + status = "okay"; + + flash@0 { + /* W25Q256JWPIM */ + compatible = "jedec,spi-nor"; + reg = <0>; + vcc-supply = <®_1p8v>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; From 6569dced2b98fc44c55640efc735d301eeac2387 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 3 Nov 2025 20:03:47 +0000 Subject: [PATCH 292/757] arm64: dts: renesas: r9a09g056: Add FCPV and VSPD nodes Add FCPV and VSPD nodes to RZ/V2N SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251103200349.62087-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 8781c2fa7313..dd0908e8c156 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -955,6 +955,30 @@ }; }; }; + + fcpvd: fcp@16470000 { + compatible = "renesas,r9a09g056-fcpvd", "renesas,fcpv"; + reg = <0 0x16470000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + }; + + vspd: vsp@16480000 { + compatible = "renesas,r9a09g056-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x16480000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, + <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,fcp = <&fcpvd>; + }; }; stmmac_axi_setup: stmmac-axi-config { From d8332e5f3384c17b55025cfcf35733eeffeac3c5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 3 Nov 2025 20:03:48 +0000 Subject: [PATCH 293/757] arm64: dts: renesas: r9a09g056: Add DU and DSI nodes Add DU and DSI nodes to RZ/V2N SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251103200349.62087-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index dd0908e8c156..c276cdc730bd 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -956,6 +956,71 @@ }; }; + dsi: dsi@16430000 { + compatible = "renesas,r9a09g056-mipi-dsi", "renesas,r9a09g057-mipi-dsi"; + reg = <0 0x16430000 0 0x20000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "seq0", "seq1", "vin1", "rcv", + "ferr", "ppi", "debug"; + clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, + <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, + <&cpg CPG_MOD 0xeb>; + clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk"; + resets = <&cpg 0xd8>, <&cpg 0xd7>; + reset-names = "arst", "prst"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&du_out_dsi>; + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + }; + }; + }; + }; + + du: display@16460000 { + compatible = "renesas,r9a09g056-du", "renesas,r9a09g057-du"; + reg = <0 0x16460000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>, + <&cpg CPG_MOD 0xef>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg 0xdc>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + }; + fcpvd: fcp@16470000 { compatible = "renesas,r9a09g056-fcpvd", "renesas,fcpv"; reg = <0 0x16470000 0 0x10000>; From 9a5a73dca92aa120ec1ab8b510eb4dbbd653d4e2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 3 Nov 2025 20:03:49 +0000 Subject: [PATCH 294/757] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable DU and DSI Enable DU, DSI and adv7535 HDMI encoder on RZ/V2N Evaluation Kit. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251103200349.62087-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 066e66b5d51a..4445bebd96c9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -33,6 +33,17 @@ stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ @@ -82,12 +93,36 @@ #clock-cells = <0>; clock-frequency = <32768>; }; + + /* 12MHz oscillator for ADV7535 */ + y1: y1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -145,6 +180,40 @@ pinctrl-names = "default"; clock-frequency = <400000>; status = "okay"; + + adv7535: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3f>, <0x3c>, <0x38>; + reg-names = "main", "edid", "cec", "packet"; + clocks = <&y1>; + clock-names = "cec"; + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + a2vdd-supply = <®_1p8v>; + v3p3-supply = <®_3p3v>; + v1p2-supply = <®_1p8v>; + adi,dsi-lanes = <4>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; }; &i2c6 { From 92279daefc1740961404bca0a7f5149bf6b23dea Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 19 Nov 2025 11:05:02 +0000 Subject: [PATCH 295/757] arm64: dts: renesas: r9a09g057: Add USB3 PHY/Host nodes Add USB3 PHY/Host nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119110505.100253-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index c09578d2c962..a36961804494 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -1087,6 +1087,66 @@ status = "disabled"; }; + xhci0: usb@15850000 { + compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + xhci1: usb@15860000 { + compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15860000 0 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xb1>; + power-domains = <&cpg>; + resets = <&cpg 0xab>; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy0: usb-phy@15870000 { + compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G057_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G057_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb3_phy1: usb-phy@15880000 { + compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15880000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb2>, + <&cpg CPG_CORE R9A09G057_USB3_1_CLKCORE>, + <&cpg CPG_CORE R9A09G057_USB3_1_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xab>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; From 7ef7ba62ec5cd1d32fd282669d0ff947df255408 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 19 Nov 2025 11:05:03 +0000 Subject: [PATCH 296/757] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB3.0 PHYs and xHCI controllers Enable the USB3.0 (CH0) and USB3.1 (CH1) host controllers on the RZ/V2H Evaluation Kit. The CN4 stacked connector on the EVK provides access to both channels, with CH0 corresponding to USB3.0 and CH1 to USB3.1. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119110505.100253-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 90d93116fabd..962a544fc50a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -455,6 +455,16 @@ }; }; + usb30_pins: usb30 { + pinmux = , /* USB30_VBUSEN */ + ; /* USB30_OVRCURN */ + }; + + usb31_pins: usb31 { + pinmux = , /* USB31_VBUSEN */ + ; /* USB31_OVRCURN */ + }; + xspi_pins: xspi0 { ctrl { pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; @@ -521,10 +531,30 @@ status = "okay"; }; +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + &wdt1 { status = "okay"; }; +&xhci0 { + pinctrl-0 = <&usb30_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xhci1 { + pinctrl-0 = <&usb31_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &xspi { pinctrl-0 = <&xspi_pins>; pinctrl-names = "default"; From 9dd6097c353cf27e1e144d42030867dc8ed4bf56 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 19 Nov 2025 11:05:04 +0000 Subject: [PATCH 297/757] arm64: dts: renesas: r9a09g056: Add USB3 PHY/Host nodes Add USB3 PHY/Host nodes to RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119110505.100253-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index c276cdc730bd..ac8b4a4f5fb7 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -694,6 +694,36 @@ status = "disabled"; }; + xhci: usb@15850000 { + compatible = "renesas,r9a09g056-xhci", "renesas,r9a09g047-xhci"; + reg = <0 0x15850000 0 0x10000>; + interrupts = , + , + , + , + ; + interrupt-names = "all", "smi", "hse", "pme", "xhc"; + clocks = <&cpg CPG_MOD 0xaf>; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + status = "disabled"; + }; + + usb3_phy: usb-phy@15870000 { + compatible = "renesas,r9a09g056-usb3-phy", "renesas,r9a09g047-usb3-phy"; + reg = <0 0x15870000 0 0x10000>; + clocks = <&cpg CPG_MOD 0xb0>, + <&cpg CPG_CORE R9A09G056_USB3_0_CLKCORE>, + <&cpg CPG_CORE R9A09G056_USB3_0_REF_ALT_CLK_P>; + clock-names = "pclk", "core", "ref_alt_clk_p"; + power-domains = <&cpg>; + resets = <&cpg 0xaa>; + #phy-cells = <0>; + status = "disabled"; + }; + sdhi0: mmc@15c00000 { compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; reg = <0x0 0x15c00000 0 0x10000>; From f221ce9f7c13ce2c1c9e4fd79743d18fb098f19a Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 19 Nov 2025 11:05:05 +0000 Subject: [PATCH 298/757] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB3.0 PHY and xHCI controller Enable the USB3.0 (CH0) host controllers on the RZ/V2N Evaluation Kit. The CN4 connector on the EVK provides access to the USB3.0 channel. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119110505.100253-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 4445bebd96c9..89154875bb33 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -411,6 +411,11 @@ }; }; + usb3_pins: usb3 { + pinmux = , /* USB30_VBUSEN */ + ; /* USB30_OVRCURN */ + }; + xspi_pins: xspi0 { ctrl { pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP"; @@ -461,10 +466,20 @@ status = "okay"; }; +&usb3_phy { + status = "okay"; +}; + &wdt1 { status = "okay"; }; +&xhci { + pinctrl-0 = <&usb3_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &xspi { pinctrl-0 = <&xspi_pins>; pinctrl-names = "default"; From 40a4c75e7f7170f4dc9f077ae480fe5775a780a1 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 19 Nov 2025 16:35:20 +0200 Subject: [PATCH 299/757] arm64: dts: renesas: r9a08g045: Add PCIe node The RZ/G3S SoC has a variant (R9A08G045S33) which supports PCIe. Add the PCIe node. Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Acked-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251119143523.977085-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 876de634908e..997e6cf0bb82 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -845,6 +845,71 @@ status = "disabled"; }; + pcie: pcie@11e40000 { + compatible = "renesas,r9a08g045-pcie"; + reg = <0 0x11e40000 0 0x10000>; + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */ + <0 0 0 2 &pcie 0 0 0 1>, /* INTB */ + <0 0 0 3 &pcie 0 0 0 2>, /* INTC */ + <0 0 0 4 &pcie 0 0 0 3>; /* INTD */ + clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names = "aclk", "pm"; + resets = <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + power-domains = <&cpg>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + renesas,sysc = <&sysc>; + status = "disabled"; + + pcie_port0: pcie@0,0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + ranges; + device_type = "pci"; + vendor-id = <0x1912>; + device-id = <0x0033>; + #address-cells = <3>; + #size-cells = <2>; + }; + }; + gic: interrupt-controller@12400000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From 1a66160fb28abcd228f69e00bb183a4749f23805 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 19 Nov 2025 16:35:21 +0200 Subject: [PATCH 300/757] arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock Versa3 clock generator available on RZ/G3S SMARC Module provides the reference clock for SoC PCIe interface. Update the device tree to reflect this connection. Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Acked-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251119143523.977085-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 6f25ab617982..982f17aafbc5 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -168,6 +168,11 @@ }; }; +&pcie_port0 { + clocks = <&versa3 5>; + clock-names = "ref"; +}; + #if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 { From 73b73af99a49fd7bf0515741734660973fa2002a Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 19 Nov 2025 16:35:22 +0200 Subject: [PATCH 301/757] arm64: dts: renesas: rzg3s-smarc: Enable PCIe The RZ Smarc Carrier-II board has PCIe headers mounted on it. Enable PCIe support. Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea Acked-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20251119143523.977085-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 6b0bb2c441af..70af605168b0 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -155,6 +155,12 @@ status = "okay"; }; +&pcie { + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &phyrst { status = "okay"; }; @@ -186,6 +192,11 @@ line-name = "key-3-gpio-irq"; }; + pcie_pins: pcie { + pinmux = , /* PCIE_RST_OUT_B */ + ; /* PCIE_CLKREQ_B */ + }; + scif0_pins: scif0 { pinmux = , /* RXD */ ; /* TXD */ From fb8f11c7975ad6096437e6a6757c98c9c9475551 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 19 Nov 2025 18:14:33 +0200 Subject: [PATCH 302/757] arm64: dts: renesas: r9a09g077: Add SPI nodes Add support for the four SPI controllers on the Renesas RZ/T2H Soc. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119161434.595677-13-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index f5fa6ca06409..b0080392f75e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -165,6 +165,78 @@ status = "disabled"; }; + rspi0: spi@80007000 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 104>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@80007400 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007400 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 105>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@80007800 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007800 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 106>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi3: spi@81007000 { + compatible = "renesas,r9a09g077-rspi"; + reg = <0x0 0x81007000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, + <&cpg CPG_MOD 602>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, From 3c77f58d108c80c464a0676aeaa3dbf791883f19 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 19 Nov 2025 18:14:34 +0200 Subject: [PATCH 303/757] arm64: dts: renesas: r9a09g087: Add SPI nodes Add support for the four SPI controllers on the Renesas RZ/N2H Soc. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251119161434.595677-14-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 361a9235f00d..e273a9aca568 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -165,6 +165,78 @@ status = "disabled"; }; + rspi0: spi@80007000 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 104>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@80007400 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007400 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 105>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@80007800 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x80007800 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 106>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi3: spi@81007000 { + compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; + reg = <0x0 0x81007000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, + <&cpg CPG_MOD 602>; + clock-names = "pclk", "pclkspi"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, From 44cfd102ce28e749a07bb0f1668cf932077b1175 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 25 Nov 2025 17:52:06 +0100 Subject: [PATCH 304/757] arm64: dts: renesas: r9a09g047e57-smarc: Remove duplicate SW_LCD_EN SW_LCD_EN is defined twice. Fixes: 9e95446b0cf93a91 ("arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys") Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/1f93558c62f4461f50935644ec831a7d2cb52630.1764089463.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 0fd90d79b020..805c0f67b70d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -8,7 +8,6 @@ /dts-v1/; /* Switch selection settings */ -#define SW_LCD_EN 0 #define SW_GPIO8_CAN0_STB 0 #define SW_GPIO9_CAN1_STB 0 #define SW_LCD_EN 0 From b449dbc0bb0301277a6de444901a7122214c090d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Nov 2025 22:45:30 +0000 Subject: [PATCH 305/757] arm64: dts: renesas: r9a09g056: Add ICU node Add node for the Interrupt Control Unit IP found on the Renesas RZ/V2N SoC, and modify the pinctrl node as its interrupt parent is the ICU node. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251125224533.294235-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index ac8b4a4f5fb7..c72b3b484d05 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -183,12 +183,104 @@ #size-cells = <2>; ranges; + icu: interrupt-controller@10400000 { + compatible = "renesas,r9a09g056-icu"; + reg = <0 0x10400000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "nmi", + "port_irq0", "port_irq1", "port_irq2", + "port_irq3", "port_irq4", "port_irq5", + "port_irq6", "port_irq7", "port_irq8", + "port_irq9", "port_irq10", "port_irq11", + "port_irq12", "port_irq13", "port_irq14", + "port_irq15", + "tint0", "tint1", "tint2", "tint3", + "tint4", "tint5", "tint6", "tint7", + "tint8", "tint9", "tint10", "tint11", + "tint12", "tint13", "tint14", "tint15", + "tint16", "tint17", "tint18", "tint19", + "tint20", "tint21", "tint22", "tint23", + "tint24", "tint25", "tint26", "tint27", + "tint28", "tint29", "tint30", "tint31", + "int-ca55-0", "int-ca55-1", + "int-ca55-2", "int-ca55-3", + "icu-error-ca55", + "gpt-u0-gtciada", "gpt-u0-gtciadb", + "gpt-u1-gtciada", "gpt-u1-gtciadb"; + clocks = <&cpg CPG_MOD 0x5>; + power-domains = <&cpg>; + resets = <&cpg 0x36>; + }; + pinctrl: pinctrl@10410000 { compatible = "renesas,r9a09g056-pinctrl"; reg = <0 0x10410000 0 0x10000>; clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&icu>; gpio-ranges = <&pinctrl 0 0 96>; power-domains = <&cpg>; resets = <&cpg 0xa5>, <&cpg 0xa6>; From 7d8b4a6672ecaa8540bf4041fea09b5ea6d78070 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Nov 2025 22:45:31 +0000 Subject: [PATCH 306/757] arm64: dts: renesas: r9a09g056: Add DMAC nodes Add nodes for the DMAC IPs found on the Renesas RZ/V2N SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251125224533.294235-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 165 +++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index c72b3b484d05..05413551cbb1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -324,6 +324,171 @@ status = "disabled"; }; + dmac0: dma-controller@11400000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x11400000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x0>; + power-domains = <&cpg>; + resets = <&cpg 0x31>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 4>; + }; + + dmac1: dma-controller@14830000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x14830000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x1>; + power-domains = <&cpg>; + resets = <&cpg 0x32>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac2: dma-controller@14840000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x14840000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x2>; + power-domains = <&cpg>; + resets = <&cpg 0x33>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac3: dma-controller@12000000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x12000000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x3>; + power-domains = <&cpg>; + resets = <&cpg 0x34>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + + dmac4: dma-controller@12010000 { + compatible = "renesas,r9a09g056-dmac", "renesas,r9a09g057-dmac"; + reg = <0 0x12010000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 0x4>; + power-domains = <&cpg>; + resets = <&cpg 0x35>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 3>; + }; + ostm0: timer@11800000 { compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; reg = <0x0 0x11800000 0x0 0x1000>; From 4018dfc222a793f6a4fc5dfb98c883ef3782eb0f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Nov 2025 22:45:32 +0000 Subject: [PATCH 307/757] arm64: dts: renesas: r9a09g056: Add RSPI nodes Add nodes for the RSPI IPs found in the Renesas RZ/V2N SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251125224533.294235-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 05413551cbb1..4d37d02138ad 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -664,6 +664,69 @@ status = "disabled"; }; + rspi0: spi@12800000 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800000 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x54>, + <&cpg CPG_MOD 0x55>, + <&cpg CPG_MOD 0x56>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7b>, <&cpg 0x7c>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi1: spi@12800400 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800400 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x57>, + <&cpg CPG_MOD 0x58>, + <&cpg CPG_MOD 0x59>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7d>, <&cpg 0x7e>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rspi2: spi@12800800 { + compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; + reg = <0x0 0x12800800 0x0 0x400>; + interrupts = , + , + , + , + ; + interrupt-names = "idle", "error", "end", "rx", "tx"; + clocks = <&cpg CPG_MOD 0x5a>, + <&cpg CPG_MOD 0x5b>, + <&cpg CPG_MOD 0x5c>; + clock-names = "pclk", "pclk_sfr", "tclk"; + resets = <&cpg 0x7f>, <&cpg 0x80>; + reset-names = "presetn", "tresetn"; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From 41e60d92c88c0085511b38077dad2939bf63ddfc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Nov 2025 22:45:33 +0000 Subject: [PATCH 308/757] arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support Add support for the NMI connected user pushbutton on the RZ/V2N EVK. The button is wired to the SoC NMI input and can be used to wake the system from low-power states. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251125224533.294235-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts index 89154875bb33..9af50198d2f1 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -8,6 +8,7 @@ /dts-v1/; #include +#include #include "r9a09g056.dtsi" / { @@ -44,6 +45,18 @@ }; }; + keys: keys { + compatible = "gpio-keys"; + + key-wakeup { + interrupts-extended = <&icu 0 IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "NMI_SW"; + debounce-interval = <20>; + wakeup-source; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ From f2d5d0ba4cf7a080a4e42f462cbb1bddceac92c7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 27 Nov 2025 14:13:13 +0100 Subject: [PATCH 309/757] ARM: dts: renesas: r9a06g032: Add Ethernet switch interrupts The Ethernet switch device node still lacks interrupts. Add them. Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Link: https://patch.msgid.link/53d45eed3709cba589a4ef3e9ad198d7e44fd9a5.1764249063.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 8debb77803bb..7c143bd5d7c9 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -453,6 +453,12 @@ <&sysctrl R9A06G032_CLK_SWITCH>; clock-names = "hclk", "clk"; power-domains = <&sysctrl>; + interrupts = , + , + , + , + ; + interrupt-names = "dlr", "switch", "prp", "hub", "ptrn"; status = "disabled"; ethernet-ports { From ef601dbb5b80a0240dc479ca0aa5fbd746f23ca7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 29 Nov 2025 18:51:56 +0000 Subject: [PATCH 310/757] arm64: dts: renesas: r9a09g047: Add RSCI nodes Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251129185203.380002-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 220 +++++++++++++++++++++ 1 file changed, 220 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index d1bf16c6ff6b..cbb48ff5028f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -591,6 +591,226 @@ }; }; + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + wdt1: watchdog@14400000 { compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; reg = <0 0x14400000 0 0x400>; From ccf2044987b41dc589de6a86b35d3a4f8ea14762 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 29 Nov 2025 18:51:57 +0000 Subject: [PATCH 311/757] arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS SMARC2 board dtsi is common for multiple SoCs. So Move aliases to board DTS as SoC may have different IPs for a given alias. eg: RZ/G3S does not have RSCI interface. Reviewed-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://patch.msgid.link/20251129185203.380002-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 6 ++++++ arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 805c0f67b70d..50e075745474 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -35,6 +35,12 @@ compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047"; + aliases { + i2c0 = &i2c0; + serial3 = &scif0; + mmc1 = &sdhi1; + }; + vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd { compatible = "regulator-gpio"; regulator-name = "SD1_PVDD"; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index 8b3765b8267d..a6e8eb730096 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -37,12 +37,6 @@ stdout-path = "serial3:115200n8"; }; - aliases { - i2c0 = &i2c0; - serial3 = &scif0; - mmc1 = &sdhi1; - }; - can_transceiver0: can-phy0 { compatible = "ti,tcan1042"; #phy-cells = <0>; From 835666e7403c3ddc6f3122888d975464f8272efe Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 29 Nov 2025 18:51:58 +0000 Subject: [PATCH 312/757] arm64: dts: renesas: r9a09g047e57-smarc: Enable rsci{2,4,9} nodes Enable device rsci{2,4,9} nodes for the RZ/G3E SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251129185203.380002-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g047e57-smarc.dts | 58 +++++++++++++++++++ .../boot/dts/renesas/renesas-smarc2.dtsi | 7 +++ .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 4 ++ 3 files changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts index 50e075745474..696903dc7a63 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts @@ -12,6 +12,8 @@ #define SW_GPIO9_CAN1_STB 0 #define SW_LCD_EN 0 #define SW_PDM_EN 0 +#define SW_SER0_PMOD 1 +#define SW_SER2_EN 1 #define SW_SD0_DEV_SEL 0 #define SW_SDIO_M2E 0 @@ -37,6 +39,9 @@ aliases { i2c0 = &i2c0; + serial0 = &rsci4; + serial1 = &rsci9; + serial2 = &rsci2; serial3 = &scif0; mmc1 = &sdhi1; }; @@ -140,6 +145,28 @@ input-schmitt-enable; }; + rsci2_pins: rsci2 { + pinmux = , /* RXD2 */ + , /* TXD2 */ + , /* CTS2N */ + ; /* RTS2N */ + bias-pull-up; + }; + + rsci4_pins: rsci4 { + pinmux = , /* RXD4 */ + , /* TXD4 */ + , /* CTS4N */ + ; /* RTS4N */ + bias-pull-up; + }; + + rsci9_pins: rsci9 { + pinmux = , /* RXD9 */ + ; /* TXD9 */ + bias-pull-up; + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; @@ -176,6 +203,37 @@ }; }; +#if SW_SER0_PMOD && SW_SER2_EN +&rsci2 { + pinctrl-0 = <&rsci2_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if (!SW_LCD_EN) && (SW_SER0_PMOD) +&rsci4 { + pinctrl-0 = <&rsci4_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + + status = "okay"; +}; +#endif + +#if (!SW_LCD_EN) +&rsci9 { + pinctrl-0 = <&rsci9_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#endif + &scif0 { pinctrl-0 = <&scif_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi index a6e8eb730096..b607b5d6c259 100644 --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi @@ -13,6 +13,13 @@ * 0 - SMARC SDIO signal is connected to uSD1 * 1 - SMARC SDIO signal is connected to M.2 Key E connector * + * Please set the switch position SW_OPT_MUX.4 on the carrier board and the + * corresponding macro SW_SER0_PMOD on the board DTS: + * + * SW_SER0_PMOD: + * 0 - SER0 signals connect to M.2 Key-E, SER2 signals are unconnected + * 1 - SER0 signals connect to PMOD, SER2 signals connect to M.2 Key-E + * * Please set the switch position SW_GPIO_CAN_PMOD on the carrier board and the * corresponding macro SW_GPIO8_CAN0_STB/SW_GPIO8_CAN0_STB on the board DTS: * diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 7faa44510d98..eb0de21d6716 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -13,6 +13,10 @@ * 0 - SD0 is connected to eMMC (default) * 1 - SD0 is connected to uSD0 card * + * Switch position SYS.4, Macro SW_SER2_EN: + * 0 - Select Module DSI connector(GPIO) + * 1 - Select SER2 + * * Switch position SYS.5, Macro SW_LCD_EN: * 0 - Select Misc. Signals routing * 1 - Select LCD From f060bbe2c32941acc4738cc27039246593f49a33 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 1 Dec 2025 13:29:32 +0200 Subject: [PATCH 313/757] arm64: dts: renesas: r9a09g077: Add ICU support The Renesas RZ/T2H (R9A09G077) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251201112933.488801-4-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index b0080392f75e..63de8271f47c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -828,6 +828,79 @@ #power-domain-cells = <0>; }; + icu: interrupt-controller@802a0000 { + compatible = "renesas,r9a09g077-icu"; + reg = <0 0x802a0000 0 0x10000>, + <0 0x812a0000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "intcpu0", "intcpu1", "intcpu2", + "intcpu3", "intcpu4", "intcpu5", + "intcpu6", "intcpu7", "intcpu8", + "intcpu9", "intcpu10", "intcpu11", + "intcpu12", "intcpu13", "intcpu14", + "intcpu15", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "sei", + "ca55-err0", "ca55-err1", + "cr520-err0", "cr520-err1", + "cr521-err0", "cr521-err1", + "peri-err0", "peri-err1", + "dsmif-err0", "dsmif-err1", + "encif-err0", "encif-err1"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + power-domains = <&cpg>; + }; + pinctrl: pinctrl@802c0000 { compatible = "renesas,r9a09g077-pinctrl"; reg = <0 0x802c0000 0 0x10000>, From d42c64cf161644929de081e541afbab33acb231a Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Mon, 1 Dec 2025 13:29:33 +0200 Subject: [PATCH 314/757] arm64: dts: renesas: r9a09g087: Add ICU support The Renesas RZ/N2H (R9A09G087) SoC has an Interrupt Controller (ICU) block that routes external interrupts to the GIC's SPIs, with the ability of level-translation, and can also produce software and aggregate error interrupts. Add support for it. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251201112933.488801-5-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index e273a9aca568..9809a6a9c1c0 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -831,6 +831,79 @@ #power-domain-cells = <0>; }; + icu: interrupt-controller@802a0000 { + compatible = "renesas,r9a09g087-icu", "renesas,r9a09g077-icu"; + reg = <0 0x802a0000 0 0x10000>, + <0 0x812a0000 0 0x10000>; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "intcpu0", "intcpu1", "intcpu2", + "intcpu3", "intcpu4", "intcpu5", + "intcpu6", "intcpu7", "intcpu8", + "intcpu9", "intcpu10", "intcpu11", + "intcpu12", "intcpu13", "intcpu14", + "intcpu15", + "irq0", "irq1", "irq2", "irq3", + "irq4", "irq5", "irq6", "irq7", + "irq8", "irq9", "irq10", "irq11", + "irq12", "irq13", "irq14", "irq15", + "sei", + "ca55-err0", "ca55-err1", + "cr520-err0", "cr520-err1", + "cr521-err0", "cr521-err1", + "peri-err0", "peri-err1", + "dsmif-err0", "dsmif-err1", + "encif-err0", "encif-err1"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; + power-domains = <&cpg>; + }; + pinctrl: pinctrl@802c0000 { compatible = "renesas,r9a09g087-pinctrl"; reg = <0 0x802c0000 0 0x10000>, From 50f51092bff57a143906a428056ff103fa75ef21 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 5 Dec 2025 17:12:53 +0200 Subject: [PATCH 315/757] arm64: dts: renesas: r9a09g077: Add DMAC support The Renesas RZ/T2H (R9A09G077) SoC has three instances of the DMAC IP. Add support for them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251205151254.2970669-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 63de8271f47c..2db5f5e94f7c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -342,6 +342,96 @@ status = "disabled"; }; + dmac0: dma-controller@800c0000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c0000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac1: dma-controller@800c1000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c1000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac2: dma-controller@800c2000 { + compatible = "renesas,r9a09g077-dmac"; + reg = <0 0x800c2000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + gmac0: ethernet@80100000 { compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; reg = <0 0x80100000 0 0x10000>; From 57a0c2d36c646a64c117de534b787abe0a0b8bcf Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 5 Dec 2025 17:12:54 +0200 Subject: [PATCH 316/757] arm64: dts: renesas: r9a09g087: Add DMAC support The Renesas RZ/N2H (R9A09G087) SoC has three instances of the DMAC IP. Add support for them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251205151254.2970669-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 9809a6a9c1c0..f3225694b4cb 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -342,6 +342,96 @@ status = "disabled"; }; + dmac0: dma-controller@800c0000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c0000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 0>; + }; + + dmac1: dma-controller@800c1000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c1000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 1>; + }; + + dmac2: dma-controller@800c2000 { + compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; + reg = <0 0x800c2000 0 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; + power-domains = <&cpg>; + #dma-cells = <1>; + dma-channels = <16>; + renesas,icu = <&icu 2>; + }; + gmac0: ethernet@80100000 { compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; From f3d22e5f6392d05d61438455bce40bfb766bf2b4 Mon Sep 17 00:00:00 2001 From: Ovidiu Panait Date: Tue, 9 Dec 2025 09:11:15 +0000 Subject: [PATCH 317/757] arm64: dts: renesas: r9a09g056: Add TSU nodes The Renesas RZ/V2N SoC includes a Thermal Sensor Unit (TSU) block designed to measure the junction temperature. The device provides real-time temperature measurements for thermal management, utilizing two dedicated channels for temperature sensing: - TSU0, which is located near the DRP-AI block - TSU1, which is located near the CPU and DRP-AI block Since TSU1 is physically closer the CPU and the highest temperature spot, it is used for CPU throttling through a passive trip and cooling map. TSU0 is configured only with a critical trip. Add TSU nodes along with thermal zones and keep them enabled in the SoC DTSI. Signed-off-by: Ovidiu Panait Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251209091115.8541-4-ovidiu.panait.rb@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 75 ++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index 4d37d02138ad..d942ac1f7865 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -83,6 +83,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -93,6 +94,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -103,6 +105,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -113,6 +116,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -303,6 +307,32 @@ resets = <&cpg 0x30>; }; + tsu0: thermal@11000000 { + compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu"; + reg = <0 0x11000000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x109>; + resets = <&cpg 0xf7>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x320>; + }; + + tsu1: thermal@14002000 { + compatible = "renesas,r9a09g056-tsu", "renesas,r9a09g047-tsu"; + reg = <0 0x14002000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; + xspi: spi@11030000 { compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi"; reg = <0 0x11030000 0 0x10000>, @@ -1403,6 +1433,51 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + sensor1_thermal: sensor1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor2_thermal: sensor2-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu1>; + + cooling-maps { + map0 { + trip = <&sensor2_target>; + cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, + <&cpu2 0 3>, <&cpu3 0 3>; + contribution = <1024>; + }; + }; + + trips { + sensor2_target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From 556a9d46fd8a5e4455b594570ad01152cb0381be Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:13:18 +0900 Subject: [PATCH 318/757] arm64: dts: renesas: r8a77980: Add SWDT node Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215031318.2219-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 8cd7f68d026b..0e81bef180a0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -139,6 +139,15 @@ status = "disabled"; }; + swdt: watchdog@e6030000 { + compatible = "renesas,r8a77980-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6030000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_CORE R8A77980_CLK_OSC>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77980", "renesas,rcar-gen3-gpio"; From cb12cfa7f650cfa315994a43ce7f795f62d19e15 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:13:19 +0900 Subject: [PATCH 319/757] arm64: dts: renesas: condor/v3hsk: Mark SWDT as reserved This watchdog can't be used with Linux because the firmware needs it on R-Car V3H boards. Sadly, it doesn't mark the node as reserved, so this is added manually here. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215031318.2219-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/condor-common.dtsi | 5 +++++ arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 9fe9c722187d..38d486e7b8c3 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -554,3 +554,8 @@ &scif_clk { clock-frequency = <14745600>; }; + +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index 2da63b4daa0a..87a9bb44cad6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -289,3 +289,8 @@ &scif_clk { clock-frequency = <14745600>; }; + +/* Firmware should reserve it but sadly doesn't */ +&swdt { + status = "reserved"; +}; From 860d9b042c5d99dacb76f29ea79b74e9a0a1ea84 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:15 +0900 Subject: [PATCH 320/757] arm64: dts: renesas: r8a77970: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-9-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1007ee48adc3..1f6676e2795a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1209,6 +1209,38 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a77970-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77970_CLK_R>, + <&cpg CPG_CORE R8A77970_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 325>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a77970-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77970_CLK_R>, + <&cpg CPG_CORE R8A77970_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 324>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 84e41ebccda4577ac9b41040b265e27c8905215d Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:16 +0900 Subject: [PATCH 321/757] arm64: dts: renesas: r8a77980: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-10-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 0e81bef180a0..86b7792d68fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1591,6 +1591,86 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 325>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 324>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 321>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 309>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a77980-wwdt", + "renesas,rcar-gen3-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A77980_CLK_R>, + <&cpg CPG_CORE R8A77980_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 403>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 65be6f4a468c9005b6b28d9fcae21f12a97b9086 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:17 +0900 Subject: [PATCH 322/757] arm64: dts: renesas: r8a779a0: Add WWDT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested-by: Niklas Söderlund Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-11-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 160 ++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 4b101a6dc49d..0483a5d0714a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -3032,6 +3032,166 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1200>, <&cpg 1318>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1201>, <&cpg 1319>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1202>, <&cpg 1320>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1203>, <&cpg 1321>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1204>, <&cpg 1322>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1205>, <&cpg 1323>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1206>, <&cpg 1324>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt7: watchdog@fff20000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff20000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1207>, <&cpg 1325>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt8: watchdog@fff30000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff30000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1208>, <&cpg 1326>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt9: watchdog@fff40000 { + compatible = "renesas,r8a779a0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff40000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779A0_CLK_R>, + <&cpg CPG_CORE R8A779A0_CLK_CP>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 1209>, <&cpg 1327>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From b7c182ff3218ca31f97d102e6c958d184159eb1e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:18 +0900 Subject: [PATCH 323/757] arm64: dts: renesas: r8a779f0: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-12-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 160 ++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 0ebf8e5dd2f9..cbb161c863ac 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -1297,6 +1297,166 @@ interrupts = ; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1200>, <&cpg 1318>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1201>, <&cpg 1319>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1202>, <&cpg 1320>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1203>, <&cpg 1321>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1204>, <&cpg 1322>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1205>, <&cpg 1323>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1206>, <&cpg 1324>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt7: watchdog@fff20000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff20000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1207>, <&cpg 1325>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt8: watchdog@fff30000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff30000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1208>, <&cpg 1326>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + + wwdt9: watchdog@fff40000 { + compatible = "renesas,r8a779f0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff40000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779F0_CLK_R>, + <&cpg CPG_CORE R8A779F0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 1209>, <&cpg 1327>; + reset-names = "cnt", "bus"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From 2dc4f97074c867e823f3f8b08f04e7d031a8acad Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:19 +0900 Subject: [PATCH 324/757] arm64: dts: renesas: r8a779g0: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-13-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 112 ++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index ff2bd1908a45..82a7278836e5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2544,6 +2544,118 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1200>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1201>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1202>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1203>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1204>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1205>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779g0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 1206>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From aca3bbde0fdb263081b5ff1e60f066704dd1a19e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 15 Dec 2025 12:47:20 +0900 Subject: [PATCH 325/757] arm64: dts: renesas: r8a779h0: Add WWDT nodes Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251215034715.3406-14-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 112 ++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 4dc0e5304f72..74bc4c4854ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -2183,6 +2183,118 @@ }; }; + wwdt0: watchdog@ffc90000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffc90000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1200>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt1: watchdog@ffca0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffca0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1201>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt2: watchdog@ffcb0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcb0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1202>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt3: watchdog@ffcc0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcc0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1203>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt4: watchdog@ffcf0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffcf0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1204>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt5: watchdog@ffef0000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xffef0000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1205>; + reset-names = "cnt"; + status = "disabled"; + }; + + wwdt6: watchdog@fff10000 { + compatible = "renesas,r8a779h0-wwdt", + "renesas,rcar-gen4-wwdt"; + reg = <0 0xfff10000 0 0x10>; + interrupts = , + ; + interrupt-names = "pretimeout", "error"; + clocks = <&cpg CPG_CORE R8A779H0_CLK_R>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCRT>; + clock-names = "cnt", "bus"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 1206>; + reset-names = "cnt"; + status = "disabled"; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; From aa7b4bbcb3a1ddf11a94f1500b05a39041efb7b4 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Mon, 5 Jan 2026 15:55:24 +0530 Subject: [PATCH 326/757] arm64: dts: qcom: qcs6490-rb3gen2: Add TC9563 PCIe switch node Add a node for the TC9563 PCIe switch, which has three downstream ports. Two embedded Ethernet devices are present on one of the downstream ports. As all these ports are present in the node represent the downstream ports and embedded endpoints. Power to the TC9563 is supplied through two LDO regulators, controlled by two GPIOs, which are added as fixed regulators. Configure the TC9563 through I2C. Reviewed-by: Bjorn Andersson Acked-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Signed-off-by: Krishna Chaitanya Chundru Link: https://lore.kernel.org/r/20260105-tc9563-v1-1-642fd1fe7893@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 128 +++++++++++++++++++ 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index c2ccbb67f800..076069f14495 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2424,7 +2424,7 @@ status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index f29a352b0288..e3d2f01881ae 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -262,6 +262,30 @@ }; }; + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_0P9"; + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <899400>; + regulator-max-microvolt = <899400>; + enable-active-high; + pinctrl-0 = <&ntn_0p9_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <4300>; + }; + + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_NTN_1P8"; + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&ntn_1p8_en>; + pinctrl-names = "default"; + regulator-enable-ramp-delay = <10000>; + }; + wcn6750-pmu { compatible = "qcom,wcn6750-pmu"; pinctrl-0 = <&bt_en>; @@ -803,6 +827,78 @@ status = "okay"; }; +&pcie1_port0 { + pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vdd_ntn_0p9>; + vdd18-supply = <&vdd_ntn_1p8>; + vdd09-supply = <&vdd_ntn_0p9>; + vddio1-supply = <&vdd_ntn_1p8>; + vddio2-supply = <&vdd_ntn_1p8>; + vddio18-supply = <&vdd_ntn_1p8>; + + i2c-parent = <&i2c0 0x77>; + + resx-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_n>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins = "gpio6"; @@ -1081,6 +1177,38 @@ }; }; +&pm8350c_gpios { + ntn_0p9_en: ntn-0p9-en-state { + pins = "gpio2"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + ntn_1p8_en: ntn-1p8-en-state { + pins = "gpio3"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; + + tc9563_resx_n: tc9563-resx-state { + pins = "gpio1"; + function = "normal"; + + bias-disable; + input-disable; + output-enable; + power-source = <0>; + }; +}; + &tlmm { gpio-reserved-ranges = <32 2>, /* ADSP */ <48 4>; /* NFC */ From a502697b840d8377742e1f31000cb52695df33e7 Mon Sep 17 00:00:00 2001 From: Vincent Knecht Date: Sun, 4 Jan 2026 19:31:53 +0100 Subject: [PATCH 327/757] arm64: dts: qcom: msm8939: Add camss and cci MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the camera subsystem and CCI used to interface with cameras on the Snapdragon 615. Signed-off-by: Vincent Knecht [André: Make order of items the same as in 8916] Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Signed-off-by: André Apitzsch Link: https://lore.kernel.org/r/20260104-camss-8x39-vbif-v9-1-0d47c7afbb2f@apitzsch.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi | 4 + arch/arm64/boot/dts/qcom/msm8939.dtsi | 146 +++++++++++++++++++ 2 files changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi index adb96cd8d643..659d127b1bc3 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi @@ -11,6 +11,10 @@ #include "msm8939.dtsi" #include "pm8916.dtsi" +&camss { + vdda-supply = <&pm8916_l2>; +}; + &mdss_dsi0 { vdda-supply = <&pm8916_l2>; vddio-supply = <&pm8916_l6>; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index eb64ec35e7f0..d4d7b0c9206c 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1436,6 +1436,145 @@ }; }; + camss: isp@1b0ac00 { + compatible = "qcom,msm8939-camss"; + reg = <0x01b0ac00 0x200>, + <0x01b00030 0x4>, + <0x01b0b000 0x200>, + <0x01b00038 0x4>, + <0x01b08000 0x100>, + <0x01b08400 0x100>, + <0x01b0a000 0x500>, + <0x01b00020 0x10>, + <0x01b10000 0x1000>, + <0x01b08800 0x100>, + <0x01b40000 0x200>; + reg-names = "csiphy0", + "csiphy0_clk_mux", + "csiphy1", + "csiphy1_clk_mux", + "csid0", + "csid1", + "ispif", + "csi_clk_mux", + "vfe0", + "csid2", + "vfe0_vbif"; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CSI0_AHB_CLK>, + <&gcc GCC_CAMSS_CSI0_CLK>, + <&gcc GCC_CAMSS_CSI0PHY_CLK>, + <&gcc GCC_CAMSS_CSI0PIX_CLK>, + <&gcc GCC_CAMSS_CSI0RDI_CLK>, + <&gcc GCC_CAMSS_CSI1_AHB_CLK>, + <&gcc GCC_CAMSS_CSI1_CLK>, + <&gcc GCC_CAMSS_CSI1PHY_CLK>, + <&gcc GCC_CAMSS_CSI1PIX_CLK>, + <&gcc GCC_CAMSS_CSI1RDI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>, + <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AHB_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_CSI2_AHB_CLK>, + <&gcc GCC_CAMSS_CSI2_CLK>, + <&gcc GCC_CAMSS_CSI2PHY_CLK>, + <&gcc GCC_CAMSS_CSI2PIX_CLK>, + <&gcc GCC_CAMSS_CSI2RDI_CLK>; + clock-names = "top_ahb", + "ispif_ahb", + "csiphy0_timer", + "csiphy1_timer", + "csi0_ahb", + "csi0", + "csi0_phy", + "csi0_pix", + "csi0_rdi", + "csi1_ahb", + "csi1", + "csi1_phy", + "csi1_pix", + "csi1_rdi", + "ahb", + "vfe0", + "csi_vfe0", + "vfe_ahb", + "vfe_axi", + "csi2_ahb", + "csi2", + "csi2_phy", + "csi2_pix", + "csi2_rdi"; + + interrupts = , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csid0", + "csid1", + "ispif", + "vfe0", + "csid2"; + + iommus = <&apps_iommu 3>; + + power-domains = <&gcc VFE_GDSC>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + cci: cci@1b0c000 { + compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; + reg = <0x01b0c000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, + <19200000>; + pinctrl-0 = <&cci0_default>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: gpu@1c00000 { compatible = "qcom,adreno-405.0", "qcom,adreno"; reg = <0x01c00000 0x10000>; @@ -1500,6 +1639,13 @@ #iommu-cells = <1>; qcom,iommu-secure-id = <17>; + /* vfe */ + iommu-ctx@3000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x3000 0x1000>; + interrupts = ; + }; + /* mdp_0: */ iommu-ctx@4000 { compatible = "qcom,msm-iommu-v1-ns"; From 09d87fdd83894bf3df4ecb79296d03c7a1ac24c3 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 19 Dec 2025 23:01:08 +0530 Subject: [PATCH 328/757] arm64: dts: qcom: sm8750-mtp: Add eusb2 repeater tuning parameters Add eusb2 repeater tuning parameters for MTP platform. Signed-off-by: Krishna Kurapati Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251219173108.2119296-4-krishna.kurapati@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index bfde752f6365..e77fe0ce91ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -1039,10 +1039,14 @@ }; &pmih0108_eusb2_repeater { - status = "okay"; + qcom,tune-usb2-preem = /bits/ 8 <0x3>; + qcom,tune-usb2-amplitude = /bits/ 8 <0xa>; + qcom,squelch-detector-bp = <(-2000)>; vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; + + status = "okay"; }; &qupv3_1 { From 0907cab01ff9746ecf08592edd9bd85d2636be58 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 24 Dec 2025 12:53:29 +0200 Subject: [PATCH 329/757] arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs The DP PHYs on X1E80100 need the ref clock which is provided by the TCSR CC. The current X Elite devices supported upstream work fine without this clock, because the boot firmware leaves this clock enabled. But we should not rely on that. Also, even though this change breaks the ABI, it is needed in order to make the driver disables this clock along with the other ones, for a proper bring-down of the entire PHY. So lets attach it to each of the DP PHYs in order to do that. Cc: stable@vger.kernel.org # v6.9 Fixes: 1940c25eaa63 ("arm64: dts: qcom: x1e80100: Add display nodes") Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20251224-phy-qcom-edp-add-missing-refclk-v5-3-3f45d349b5ac@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 51ad2b2e6375..03629639dcfb 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -5929,9 +5929,11 @@ <0 0x0aec2000 0 0x1c8>; clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; power-domains = <&rpmhpd RPMHPD_MX>; @@ -5949,9 +5951,11 @@ <0 0x0aec5000 0 0x1c8>; clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>; + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_EDP_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; power-domains = <&rpmhpd RPMHPD_MX>; From 7db5fbe508deedec6c183d5056cf3c504c027f40 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 26 Dec 2025 02:39:23 +0200 Subject: [PATCH 330/757] arm64: dts: qcom: msm8994-octagon: Fix Analog Devices vendor prefix of AD7147 Trivial change, Analog Devices vendor prefix is "adi", but there is a valid "ad" vendor prefix of another company, this may explain why the issue hasn't been discovered by the automatic tests. A problem of not described compatible value is out of this change scope. Fixes: c636eeb751f6 ("arm64: dts: qcom: msm8994-octagon: Add AD7147 and APDS9930 sensors") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251226003923.3341904-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index 4c983b10dd92..7ace3540ef0a 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -378,7 +378,7 @@ status = "okay"; sideinteraction: touch@2c { - compatible = "ad,ad7147_captouch"; + compatible = "adi,ad7147_captouch"; reg = <0x2c>; pinctrl-names = "default", "sleep"; From a1a515c21dd70d1b761ccbf6efc9dd1ba6d26d77 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 24 Dec 2025 03:09:13 +0200 Subject: [PATCH 331/757] arm64: dts: qcom: x1e80100-medion-sprchrgd-14-s1: correct firmware paths Per the agreement, the firmware paths (even for devices not supported in linux-firmware) should follow the SoC/Vendor/device pattern. Update firmware names for Medion SPRCHRGD 14 S1 to follow that pattern. Fixes: 8cf65490cdb0 ("arm64: dts: qcom: Add dts for Medion SPRCHRGD 14 S1") Cc: Georg Gottleuber Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251224-fix-medion-v1-1-305747dff79a@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts index 9155435484fb..20a33e6f27ee 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts @@ -793,7 +793,7 @@ status = "okay"; zap-shader { - firmware-name = "qcom/x1e80100/medion/qcdxkmsuc8380.mbn"; + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcdxkmsuc8380.mbn"; }; }; @@ -937,7 +937,7 @@ }; &iris { - firmware-name = "qcom/x1e80100/medion/qcvss8380.mbn"; + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcvss8380.mbn"; status = "okay"; }; @@ -1141,15 +1141,15 @@ }; &remoteproc_adsp { - firmware-name = "qcom/x1e80100/medion/qcadsp8380.mbn", - "qcom/x1e80100/medion/adsp_dtbs.elf"; + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qcadsp8380.mbn", + "qcom/x1e80100/Medion/sprchrgd-14-s1/adsp_dtbs.elf"; status = "okay"; }; &remoteproc_cdsp { - firmware-name = "qcom/x1e80100/medion/qccdsp8380.mbn", - "qcom/x1e80100/medion/cdsp_dtbs.elf"; + firmware-name = "qcom/x1e80100/Medion/sprchrgd-14-s1/qccdsp8380.mbn", + "qcom/x1e80100/Medion/sprchrgd-14-s1/cdsp_dtbs.elf"; status = "okay"; }; From 173c43d0e4a435a95568d6b912d0d45c37d6d75f Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 24 Dec 2025 15:50:24 +0530 Subject: [PATCH 332/757] arm64: dts: qcom: lemans: add QCrypto node Add Qualcomm Crypto Engine device node for LeMans platform. QCE and Crypto DMA nodes patch was applied as part of the commit 7ff3da43ef44 ("arm64: dts: qcom: sa8775p: add QCrypto nodes"), however was partially reverted by commit 92979f12a201 ("arm64: dts: qcom: sa8775p: Partially revert "arm64: dts: qcom: sa8775p: add QCrypto nodes"") due to compatible-string being miss-matched against schema. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abhinaba Rakshit Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251224-enable-qualcomm-crypto-engine-for-lemans-v2-1-a707e3d38765@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index d0d8711ea9c6..7c46f493300c 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2790,6 +2790,18 @@ <&apps_smmu 0x481 0x00>; }; + crypto: crypto@1dfa000 { + compatible = "qcom,sa8775p-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + ctcu@4001000 { compatible = "qcom,sa8775p-ctcu"; reg = <0x0 0x04001000 0x0 0x1000>; From 6691966f4afc06c674b7679a772b7423cd16c545 Mon Sep 17 00:00:00 2001 From: Abhinaba Rakshit Date: Wed, 24 Dec 2025 14:03:02 +0530 Subject: [PATCH 333/757] arm64: dts: qcom: monaco: add QCrypto node Add Qualcomm Crypto Engine device node for Monaco platform. QCE and Crypto DMA nodes patch was applied as part of commit a86d84409947 ("arm64: dts: qcom: qcs8300: add QCrypto nodes"), however was partially reverted by commit cdc117c40537 ("arm64: dts: qcom: qcs8300: Partially revert "arm64: dts: qcom: qcs8300: add QCrypto nodes"") due to compatible string being mismatched against schema. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abhinaba Rakshit Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251224-enable-qualcomm-crypto-engine-for-monaco-v3-1-6073430bbc13@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index e7b12b01928d..97f24b8f22ea 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2358,6 +2358,18 @@ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; + crypto: crypto@1dfa000 { + compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0x0 0x01dfa000 0x0 0x6000>; + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x481 0x0>; + interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>; From 1c6192ec9c4ab8bdb7b2cf8763b7ef7e38671ffe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 29 Dec 2025 12:57:35 +0100 Subject: [PATCH 334/757] arm64: dts: qcom: sm8750: Fix BAM DMA probing Bindings always required "qcom,num-ees" and "num-channels" properties, as reported by dtbs_check: sm8750-mtp.dtb: dma-controller@1dc4000 (qcom,bam-v1.7.4): 'anyOf' conditional failed, one must be fixed: 'qcom,powered-remotely' is a required property 'num-channels' is a required property 'qcom,num-ees' is a required property 'clocks' is a required property 'clock-names' is a required property However since commit 5068b5254812 ("dmaengine: qcom: bam_dma: Fix DT error handling for num-channels/ees") missing properties are actually fatal and BAM does not probe: bam-dma-engine 1dc4000.dma-controller: num-channels unspecified in dt bam-dma-engine 1dc4000.dma-controller: probe with driver bam-dma-engine failed with error -22 Fixes: eeb0f3e4ea67 ("arm64: dts: qcom: sm8750: Add QCrypto nodes") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251229115734.205744-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 8a471b2349be..0a6f2a449c20 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2088,6 +2088,8 @@ <&apps_smmu 0x481 0>; qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; qcom,controlled-remotely; }; From 8d83fd4f08f655d0fd3c9c1fdfb7243f9116126c Mon Sep 17 00:00:00 2001 From: Harshal Dev Date: Tue, 23 Dec 2025 10:18:16 +0530 Subject: [PATCH 335/757] arm64: dts: qcom: x1e80100: add TRNG node The x1e80100 SoC has a True Random Number Generator, add the node with the correct compatible set. Reviewed-by: Dmitry Baryshkov Tested-by: Wenjia Zhang Reviewed-by: Konrad Dybcio Signed-off-by: Harshal Dev Reviewed-by: Abel Vesa Link: https://lore.kernel.org/r/20251223-trng_dt_binding_x1e80100-v4-2-5bfe781f9c7b@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 03629639dcfb..a559f6340af9 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3063,6 +3063,11 @@ }; }; + rng: rng@10c3000 { + compatible = "qcom,x1e80100-trng", "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + cnoc_main: interconnect@1500000 { compatible = "qcom,x1e80100-cnoc-main"; reg = <0 0x01500000 0 0x14400>; From 46a7c01e7e9d296ba09bad579ae0277cfb558b24 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 28 Nov 2025 18:49:24 +0800 Subject: [PATCH 336/757] arm64: dts: qcom: qcs8300: enable pcie0 Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/r/20251128104928.4070050-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 181 ++++++++++++++++++++++++++- 1 file changed, 180 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 97f24b8f22ea..994fbca4fcae 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -912,7 +912,7 @@ #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <0>, + <&pcie0_phy>, <0>, <0>, <0>, @@ -2264,6 +2264,185 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pcie0: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>, + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_0_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55>; + + operating-points-v2 = <&pcie0_opp_table>; + + status = "disabled"; + + pcie0_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + }; + + pcieport0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie0_phy>; + }; + }; + + pcie0_phy: phy@1c04000 { + compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x01c04000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_hc: ufs@1d84000 { compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; From 33967eadb2153d92ea1de6e9c9ac8ade21c74d86 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 28 Nov 2025 18:49:25 +0800 Subject: [PATCH 337/757] arm64: dts: qcom: qcs8300-ride: enable pcie0 interface Add configurations in devicetree for PCIe0, board related gpios, PMIC regulators, etc for qcs8300-ride board. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/r/20251128104928.4070050-4-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index 4a8ac26846c6..e204dbd54f72 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -353,6 +353,25 @@ status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -398,6 +417,29 @@ }; &tlmm { + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; From 7565ec0170201aca07c9e1c3b5b6f213c5024599 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 28 Nov 2025 18:49:26 +0800 Subject: [PATCH 338/757] arm64: dts: qcom: qcs8300: enable pcie1 Add configurations in devicetree for PCIe1, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s. Acked-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/r/20251128104928.4070050-5-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 193 ++++++++++++++++++++++++++- 1 file changed, 192 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 994fbca4fcae..31b4145a1d23 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -913,7 +913,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <0>, + <&pcie1_phy>, <0>, <0>, <0>, @@ -2443,6 +2443,197 @@ status = "disabled"; }; + pcie1: pci@1c10000 { + device_type = "pci"; + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config", + "mhi"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <4>; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + power-domains = <&gcc GCC_PCIE_1_GDSC>; + + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + + operating-points-v2 = <&pcie1_opp_table>; + + status = "disabled"; + + pcie1_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* GEN 1 x1 */ + opp-2500000 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <250000 1>; + }; + + /* GEN 1 x2 and GEN 2 x1 */ + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <500000 1>; + }; + + /* GEN 1 x4 and GEN 2 x2 */ + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <1000000 1>; + }; + + /* GEN 2 x4 */ + opp-20000000 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + }; + + /* GEN 3 x1 */ + opp-8000000 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + opp-peak-kBps = <984500 1>; + }; + + /* GEN 3 x2 and GEN 4 x1 */ + opp-16000000 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <1969000 1>; + }; + + /* GEN 3 x4 and GEN 4 x2 */ + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <3938000 1>; + }; + + /* GEN 4 x4 */ + opp-64000000 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_nom>; + opp-peak-kBps = <7876000 1>; + }; + }; + + pcieport1: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie1_phy>; + }; + }; + + pcie1_phy: phy@1c14000 { + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x01c14000 0x0 0x4000>; + + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe", + "pipediv2"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + ufs_mem_hc: ufs@1d84000 { compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; From cdb613a84527197f88f8bff3c5ee015e611a8373 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 28 Nov 2025 18:49:27 +0800 Subject: [PATCH 339/757] arm64: dts: qcom: qcs8300-ride: enable pcie1 interface Add configurations in devicetree for PCIe1, board related gpios, PMIC regulators, etc for qcs8300-ride platform. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/r/20251128104928.4070050-6-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index e204dbd54f72..c04e0ad53eec 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -372,6 +372,25 @@ status = "okay"; }; +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; @@ -456,6 +475,29 @@ }; }; + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + dp_hot_plug_det: dp-hot-plug-det-state { pins = "gpio94"; function = "edp0_hot"; From 41e2424651f7c679382bb9e32225d3b541d4aa8d Mon Sep 17 00:00:00 2001 From: Sushrut Shree Trivedi Date: Fri, 28 Nov 2025 18:49:28 +0800 Subject: [PATCH 340/757] arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1. PCIe0 is routed to an m.2 E key connector on the mainboard for wifi attaches while PCIe1 routes to a standard PCIe x4 expansion slot. Hence, enable the PCIe0 and PCIe1 controller and phy-nodes. Signed-off-by: Sushrut Shree Trivedi Signed-off-by: Ziyue Zhang Link: https://lore.kernel.org/r/20251128104928.4070050-7-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 85 +++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 15cfb3aa3fa8..565418b86b2a 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -411,6 +411,44 @@ status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l6a>; + vdda-pll-supply = <&vreg_l5a>; + + status = "okay"; +}; + +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcieport1 { + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; +}; + &qupv3_id_0 { firmware-name = "qcom/qcs8300/qupv3fw.elf"; status = "okay"; @@ -456,6 +494,30 @@ }; &tlmm { + + pcie0_default_state: pcie0-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + ethernet0_default: ethernet0-default-state { ethernet0_mdc: ethernet0-mdc-pins { pins = "gpio5"; @@ -479,6 +541,29 @@ bias-pull-up; }; + pcie1_default_state: pcie1-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c15_default: qup-i2c15-state { pins = "gpio91", "gpio92"; function = "qup1_se7"; From c84b6dc36b2f81b79145459a9805302fe5e658f8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:25:36 +0100 Subject: [PATCH 341/757] arm64: dts: ti: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' and before '{' characters. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251223152535.155571-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index 2b233bc0323d..a5d5dc0a7bec 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -669,7 +669,7 @@ pinctrl-0 = <&ospi0_pins_default>; status = "okay"; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts index 4bb92fde6ab8..5ba4ed56755b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts @@ -224,7 +224,7 @@ status = "okay"; }; -&main_i2c0{ +&main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; clock-frequency = <400000>; @@ -466,7 +466,7 @@ pinctrl-0 = <&pinctrl_mmc1>; disable-wp; bootph-all; - status="okay"; + status = "okay"; }; &ti_csi2rx0 { From 234a884d67fe3b5741481e6991f7ccf140c206ae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:25:37 +0100 Subject: [PATCH 342/757] arm64: dts: ti: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251223152535.155571-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 18 +++--- .../dts/ti/k3-am642-phyboard-electra-rdk.dts | 6 +- ...phyboard-electra-x27-gpio1-spi1-uart3.dtso | 4 +- .../ti/k3-am65-iot2050-arduino-connector.dtsi | 58 +++++++++---------- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 +- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 2 +- .../boot/dts/ti/k3-am68-sk-base-board.dts | 14 ++--- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 26 ++++----- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 4 +- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ++++---- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 4 +- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-j722s.dtsi | 2 +- .../dts/ti/k3-j784s4-j742s2-evm-common.dtsi | 4 +- 18 files changed, 90 insertions(+), 90 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi index ec9dd931fe92..34954df692a3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -514,7 +514,7 @@ pinctrl-single,pins = < AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */ AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */ - AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */ AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */ AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */ AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */ diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts index ef719c6334fc..4f7f6f95b02e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -283,7 +283,7 @@ pinctrl-single,pins = < AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ - AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x011c, PIN_INPUT, 0) /* () MMC2_CLKLB */ AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index d872cc671094..1b1d3970888b 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -84,7 +84,7 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01840000 0x00 0xC0000>, /* GICR */ + <0x00 0x01840000 0x00 0xc0000>, /* GICR */ <0x01 0x00000000 0x00 0x2000>, /* GICC */ <0x01 0x00010000 0x00 0x1000>, /* GICH */ <0x01 0x00020000 0x00 0x2000>; /* GICV */ @@ -685,14 +685,14 @@ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; - dmas = <&main_pktdma 0xC500 15>, - <&main_pktdma 0xC501 15>, - <&main_pktdma 0xC502 15>, - <&main_pktdma 0xC503 15>, - <&main_pktdma 0xC504 15>, - <&main_pktdma 0xC505 15>, - <&main_pktdma 0xC506 15>, - <&main_pktdma 0xC507 15>, + dmas = <&main_pktdma 0xc500 15>, + <&main_pktdma 0xc501 15>, + <&main_pktdma 0xc502 15>, + <&main_pktdma 0xc503 15>, + <&main_pktdma 0xc504 15>, + <&main_pktdma 0xc505 15>, + <&main_pktdma 0xc506 15>, + <&main_pktdma 0xc507 15>, <&main_pktdma 0x4500 15>; dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index e4afa8c0a8ca..793538f94942 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -206,8 +206,8 @@ pinctrl-single,pins = < AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */ AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */ - AM64X_IOPAD(0x01A8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */ - AM64X_IOPAD(0x01AC, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */ + AM64X_IOPAD(0x01a8, PIN_OUTPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */ + AM64X_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */ >; }; @@ -300,7 +300,7 @@ main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ - AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso index bea8efa3e909..39306bf8eec1 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso @@ -29,9 +29,9 @@ main_spi1_pins_default: main-spi1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */ - AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */ + AM64X_IOPAD(0x021c, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */ AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */ - AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */ + AM64X_IOPAD(0x022c, PIN_INPUT, 0) /* (A15) SPI1_D1 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi index 7ff0abd7c62e..6c7fdaf1f2c4 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-arduino-connector.dtsi @@ -138,28 +138,28 @@ d2_uart0_ctsn: d2-uart0-ctsn-pins { pinctrl-single,pins = < /* (P1) MCU_UART0_CTSn */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4) >; }; d2_gpio: d2-gpio-pins { pinctrl-single,pins = < /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7) >; }; d2_gpio_pullup: d2-gpio-pullup-pins { pinctrl-single,pins = < /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 7) >; }; d2_gpio_pulldown: d2-gpio-pulldown-pins { pinctrl-single,pins = < /* (P5) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT_PULLDOWN, 7) >; }; @@ -348,42 +348,42 @@ a2_gpio: a2-gpio-pins { pinctrl-single,pins = < /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7) >; }; a2_gpio_pullup: a2-gpio-pullup-pins { pinctrl-single,pins = < /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 7) >; }; a2_gpio_pulldown: a2-gpio-pulldown-pins { pinctrl-single,pins = < /* (L5) WKUP_GPIO0_43 */ - AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) + AM65X_WKUP_IOPAD(0x007c, PIN_INPUT_PULLDOWN, 7) >; }; a3_gpio: a3-gpio-pins { pinctrl-single,pins = < /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7) >; }; a3_gpio_pullup: a3-gpio-pullup-pins { pinctrl-single,pins = < /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x006c, PIN_INPUT, 7) >; }; a3_gpio_pulldown: a3-gpio-pulldown-pins { pinctrl-single,pins = < /* (M5) WKUP_GPIO0_39 */ - AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) + AM65X_WKUP_IOPAD(0x006c, PIN_INPUT_PULLDOWN, 7) >; }; @@ -411,21 +411,21 @@ a5_gpio: a5-gpio-pins { pinctrl-single,pins = < /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) + AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 7) >; }; a5_gpio_pullup: a5-gpio-pullup-pins { pinctrl-single,pins = < /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) + AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLUP, 7) >; }; a5_gpio_pulldown: a5-gpio-pulldown-pins { pinctrl-single,pins = < /* (N5) WKUP_GPIO0_35 */ - AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) + AM65X_WKUP_IOPAD(0x005c, PIN_INPUT_PULLDOWN, 7) >; }; @@ -533,28 +533,28 @@ d5_ehrpwm1_a: d5-ehrpwm1-a-pins { pinctrl-single,pins = < /* (AF17) EHRPWM1_A */ - AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) + AM65X_IOPAD(0x008c, PIN_OUTPUT, 5) >; }; d5_gpio: d5-gpio-pins { pinctrl-single,pins = < /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT, 7) + AM65X_IOPAD(0x008c, PIN_INPUT, 7) >; }; d5_gpio_pullup: d5-gpio-pullup-pins { pinctrl-single,pins = < /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) + AM65X_IOPAD(0x008c, PIN_INPUT_PULLUP, 7) >; }; d5_gpio_pulldown: d5-gpio-pulldown-pins { pinctrl-single,pins = < /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) + AM65X_IOPAD(0x008c, PIN_INPUT_PULLDOWN, 7) >; }; @@ -589,84 +589,84 @@ d7_ehrpwm3_a: d7-ehrpwm3-a-pins { pinctrl-single,pins = < /* (AH15) EHRPWM3_A */ - AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) + AM65X_IOPAD(0x00ac, PIN_OUTPUT, 5) >; }; d7_gpio: d7-gpio-pins { pinctrl-single,pins = < /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT, 7) + AM65X_IOPAD(0x00ac, PIN_INPUT, 7) >; }; d7_gpio_pullup: d7-gpio-pullup-pins { pinctrl-single,pins = < /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) + AM65X_IOPAD(0x00ac, PIN_INPUT_PULLUP, 7) >; }; d7_gpio_pulldown: d7-gpio-pulldown-pins { pinctrl-single,pins = < /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) + AM65X_IOPAD(0x00ac, PIN_INPUT_PULLDOWN, 7) >; }; d8_ehrpwm4_a: d8-ehrpwm4-a-pins { pinctrl-single,pins = < /* (AG15) EHRPWM4_A */ - AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) + AM65X_IOPAD(0x00c0, PIN_OUTPUT, 5) >; }; d8_gpio: d8-gpio-pins { pinctrl-single,pins = < /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT, 7) + AM65X_IOPAD(0x00c0, PIN_INPUT, 7) >; }; d8_gpio_pullup: d8-gpio-pullup-pins { pinctrl-single,pins = < /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) + AM65X_IOPAD(0x00c0, PIN_INPUT_PULLUP, 7) >; }; d8_gpio_pulldown: d8-gpio-pulldown-pins { pinctrl-single,pins = < /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) + AM65X_IOPAD(0x00c0, PIN_INPUT_PULLDOWN, 7) >; }; d9_ehrpwm5_a: d9-ehrpwm5-a-pins { pinctrl-single,pins = < /* (AD15) EHRPWM5_A */ - AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) + AM65X_IOPAD(0x00cc, PIN_OUTPUT, 5) >; }; d9_gpio: d9-gpio-pins { pinctrl-single,pins = < /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT, 7) + AM65X_IOPAD(0x00cc, PIN_INPUT, 7) >; }; d9_gpio_pullup: d9-gpio-pullup-pins { pinctrl-single,pins = < /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) + AM65X_IOPAD(0x00cc, PIN_INPUT_PULLUP, 7) >; }; d9_gpio_pulldown: d9-gpio-pulldown-pins { pinctrl-single,pins = < /* (AD15) GPIO0_51 */ - AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) + AM65X_IOPAD(0x00cc, PIN_INPUT_PULLDOWN, 7) >; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index a9a4e7401a49..f3ee73e64d69 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -266,7 +266,7 @@ minipcie_pins_default: minipcie-default-pins { pinctrl-single,pins = < /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ - AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) + AM65X_WKUP_IOPAD(0x003c, PIN_OUTPUT, 7) >; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 61c11dc92d9c..d6ee7b9a6b68 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -884,7 +884,7 @@ #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, - <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; + <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07fd0000>; ti,syscon-pcie-id = <&scm_conf 0x210>; ti,syscon-pcie-mode = <&scm_conf 0x4060>; bus-range = <0x0 0xff>; @@ -905,7 +905,7 @@ #address-cells = <3>; #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, - <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; + <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07fd0000>; ti,syscon-pcie-id = <&scm_conf 0x210>; ti,syscon-pcie-mode = <&scm_conf 0x4070>; bus-range = <0x0 0xff>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 46c58162eca0..e0262c2743eb 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -190,7 +190,7 @@ pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ - AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x004c, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */ >; bootph-all; diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 88f202f266c6..8178333fb2b4 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -359,15 +359,15 @@ mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ @@ -392,7 +392,7 @@ mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ >; }; @@ -422,13 +422,13 @@ mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ - J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ + J721S2_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ - J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ + J721S2_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ - J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ + J721S2_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index abe2f21e0e1d..e56772a334c5 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -264,24 +264,24 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ + J784S4_IOPAD(0x0c4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ - J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ - J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ - J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ - J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ - J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06c, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00c, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0b8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ - J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ - J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ - J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ - J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ + J784S4_IOPAD(0x0cc, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ + J784S4_IOPAD(0x08c, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ >; @@ -347,8 +347,8 @@ main_mcan7_pins_default: main-mcan7-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ - J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ + J784S4_IOPAD(0x09c, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index fec1db8b133d..dc5c02a025f8 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -212,7 +212,7 @@ reg = <0x0 0x40f04200 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; + pinctrl-single,function-mask = <0x0000000f>; status = "reserved"; }; @@ -222,7 +222,7 @@ reg = <0x0 0x40f04280 0x0 0x28>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x0000000F>; + pinctrl-single,function-mask = <0x0000000f>; status = "reserved"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 050776cb4df8..689ba2ff81f7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -443,29 +443,29 @@ rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < - J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x01c, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ - J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ - J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02c, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ - J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ - J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x1b0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1a0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ - J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ - J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x1d0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11c, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ - J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ - J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x19c, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1b4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ - J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x00c, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ - J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ + J721E_IOPAD(0x17c, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ - J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ + J721E_IOPAD(0x18c, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index b6e22c242951..ba109cc5b2bc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -41,7 +41,7 @@ reg = <0x000>; device_type = "cpu"; enable-method = "psci"; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; @@ -55,7 +55,7 @@ reg = <0x001>; device_type = "cpu"; enable-method = "psci"; - i-cache-size = <0xC000>; + i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; d-cache-size = <0x8000>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 2a7f9c519735..fd01437726ab 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -87,7 +87,7 @@ wkup_pmx1: pinctrl@4301c038 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c038 0x00 0x02C>; + reg = <0x00 0x4301c038 0x00 0x02c>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts index 7baf5764862b..e66330c71593 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -436,7 +436,7 @@ mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ - J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */ + J722S_MCU_IOPAD(0x03c, PIN_OUTPUT, 0) /*(C1) MCU_MCAN1_TX */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index cdc8570e54b2..c8b634c34677 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -162,7 +162,7 @@ <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ - <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */ + <0x00 0x301c0000 0x00 0x301c0000 0x00 0x00001000>, /* DPHY-TX */ <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi index e50735577737..ff3a85cbc524 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi @@ -509,10 +509,10 @@ J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ - J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ - J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ >; }; }; From 24571ecbda52f7a43a7dad1f7706bfa81fb1fa79 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Thu, 6 Nov 2025 10:00:27 +0100 Subject: [PATCH 343/757] ARM: dts: ti/omap: omap4-epson-embt2ws: add powerbutton There is a power button connected to the PMIC, so describe it to be able to power off the device in a convenient manner. Signed-off-by: Andreas Kemnade Link: https://patch.msgid.link/20251106-twl6030-button-v4-3-fdf1aa6e1e9a@kernel.org Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts index c90f43cc2fae..673df1b693f2 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts +++ b/arch/arm/boot/dts/ti/omap/omap4-epson-embt2ws.dts @@ -229,6 +229,11 @@ interrupts = <11>; }; + pwrbutton { + compatible = "ti,twl6030-pwrbutton"; + interrupts = <0>; + }; + ldo2: regulator-ldo2 { compatible = "ti,twl6032-ldo2"; regulator-min-microvolt = <1000000>; From 60884f7a982770b1a64d61be7f96214538756390 Mon Sep 17 00:00:00 2001 From: Yegor Yefremov Date: Mon, 17 Nov 2025 12:35:35 +0100 Subject: [PATCH 344/757] ARM: dts: omap: enable panic-indicator option Use onrisc:red:power as a panic indicator. Signed-off-by: Yegor Yefremov Link: https://patch.msgid.link/20251117113535.2248177-1-yegorslists@googlemail.com Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi index ed194469973e..a827153ba6bb 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-baltos-leds.dtsi @@ -22,6 +22,7 @@ linux,default-trigger = "default-on"; gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; default-state = "on"; + panic-indicator; }; led_wlan: led-wlan { label = "onrisc:blue:wlan"; From 25332069532ac030b1185bb8084c1a5298c12bea Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Tue, 18 Nov 2025 16:48:55 +0100 Subject: [PATCH 345/757] ARM: dts: tps65910: Add gpio & interrupt properties The binding document ti,tps65910.yaml requires the controller and cells properties for both gpio and interrupts. As they have const and fixed values a default can be provided for all users. Signed-off-by: Alexander Stein Link: https://patch.msgid.link/20251118154856.2015184-1-alexander.stein@ew.tq-group.com Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/tps65910.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi index a941d1e62328..f5a776229023 100644 --- a/arch/arm/boot/dts/tps65910.dtsi +++ b/arch/arm/boot/dts/tps65910.dtsi @@ -10,6 +10,10 @@ &tps { compatible = "ti,tps65910"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; regulators { #address-cells = <1>; From 3d43205d0efb4da3e799e969c92e70e4d9e4d124 Mon Sep 17 00:00:00 2001 From: "Kory Maincent (TI.com)" Date: Thu, 4 Dec 2025 10:23:44 +0100 Subject: [PATCH 346/757] ARM: dts: Drop am335x-base0033 devicetree Remove the am335x-base0033 devicetree as it has been non-functional since 2017 (Linunx v4.14) when the ti,tilcdc,slave binding was removed. The HDMI output on this board has been broken for over 8 years without any reported issues or attempts to fix it, indicating this devicetree is no longer in active use. Signed-off-by: Kory Maincent (TI.com) Acked-by: Enric Balletbo i Serra Link: https://patch.msgid.link/20251204092346.1076836-1-kory.maincent@bootlin.com Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/Makefile | 1 - arch/arm/boot/dts/ti/omap/am335x-base0033.dts | 92 ------------------- 2 files changed, 93 deletions(-) delete mode 100644 arch/arm/boot/dts/ti/omap/am335x-base0033.dts diff --git a/arch/arm/boot/dts/ti/omap/Makefile b/arch/arm/boot/dts/ti/omap/Makefile index 14e500846875..3f54b515c471 100644 --- a/arch/arm/boot/dts/ti/omap/Makefile +++ b/arch/arm/boot/dts/ti/omap/Makefile @@ -86,7 +86,6 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-baltos-ir2110.dtb \ am335x-baltos-ir3220.dtb \ am335x-baltos-ir5221.dtb \ - am335x-base0033.dtb \ am335x-bone.dtb \ am335x-boneblack.dtb \ am335x-boneblack-wireless.dtb \ diff --git a/arch/arm/boot/dts/ti/omap/am335x-base0033.dts b/arch/arm/boot/dts/ti/omap/am335x-base0033.dts deleted file mode 100644 index 46078af4b7a3..000000000000 --- a/arch/arm/boot/dts/ti/omap/am335x-base0033.dts +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION - * - * Copyright (C) 2013 ISEE 2007 SL - https://www.isee.biz - */ - -#include "am335x-igep0033.dtsi" - -/ { - model = "IGEP COM AM335x on AQUILA Expansion"; - compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; - - hdmi { - compatible = "ti,tilcdc,slave"; - i2c = <&i2c0>; - pinctrl-names = "default", "off"; - pinctrl-0 = <&nxp_hdmi_pins>; - pinctrl-1 = <&nxp_hdmi_off_pins>; - status = "okay"; - }; - - leds_base { - pinctrl-names = "default"; - pinctrl-0 = <&leds_base_pins>; - - compatible = "gpio-leds"; - - led0 { - label = "base:red:user"; - gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ - default-state = "off"; - }; - - led1 { - label = "base:green:user"; - gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ - default-state = "off"; - }; - }; -}; - -&am33xx_pinmux { - nxp_hdmi_pins: nxp-hdmi-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) - AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) - >; - }; - nxp_hdmi_off_pins: nxp-hdmi-off-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ - >; - }; - - leds_base_pins: leds-base-pins { - pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ - AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ - >; - }; -}; - -&lcdc { - status = "okay"; -}; - -&i2c0 { - eeprom: eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; From 9da91ec4a6b22238d9178cbc5679467ea4261df3 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 12 Dec 2025 14:32:12 -0600 Subject: [PATCH 347/757] ARM: dts: ti: Drop unused .dtsi These .dtsi files are not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251212203226.458694-6-robh@kernel.org Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/am3703.dtsi | 14 -- arch/arm/boot/dts/ti/omap/am3715.dtsi | 10 - .../boot/dts/ti/omap/omap3430es1-clocks.dtsi | 237 ------------------ 3 files changed, 261 deletions(-) delete mode 100644 arch/arm/boot/dts/ti/omap/am3703.dtsi delete mode 100644 arch/arm/boot/dts/ti/omap/am3715.dtsi delete mode 100644 arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi diff --git a/arch/arm/boot/dts/ti/omap/am3703.dtsi b/arch/arm/boot/dts/ti/omap/am3703.dtsi deleted file mode 100644 index 2b994ae790c9..000000000000 --- a/arch/arm/boot/dts/ti/omap/am3703.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel - */ - -#include "omap36xx.dtsi" - -&iva { - status = "disabled"; -}; - -&sgx_module { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/ti/omap/am3715.dtsi b/arch/arm/boot/dts/ti/omap/am3715.dtsi deleted file mode 100644 index ab328e8c0bd8..000000000000 --- a/arch/arm/boot/dts/ti/omap/am3715.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (C) 2020 André Hentschel - */ - -#include "omap36xx.dtsi" - -&iva { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi deleted file mode 100644 index 6e754d265f18..000000000000 --- a/arch/arm/boot/dts/ti/omap/omap3430es1-clocks.dtsi +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Device Tree Source for OMAP3430 ES1 clock data - * - * Copyright (C) 2013 Texas Instruments, Inc. - */ -&cm_clocks { - gfx_l3_ck: gfx_l3_ck@b10 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&l3_ick>; - reg = <0x0b10>; - ti,bit-shift = <0>; - }; - - gfx_l3_fck: gfx_l3_fck@b40 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&l3_ick>; - ti,max-div = <7>; - reg = <0x0b40>; - ti,index-starts-at-one; - }; - - gfx_l3_ick: gfx_l3_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&gfx_l3_ck>; - clock-mult = <1>; - clock-div = <1>; - }; - - gfx_cg1_ck: gfx_cg1_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <1>; - }; - - gfx_cg2_ck: gfx_cg2_ck@b00 { - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clocks = <&gfx_l3_fck>; - reg = <0x0b00>; - ti,bit-shift = <2>; - }; - - clock@a00 { - compatible = "ti,clksel"; - reg = <0xa00>; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - d2d_26m_fck: clock-d2d-26m-fck@3 { - reg = <3>; - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "d2d_26m_fck"; - clocks = <&sys_ck>; - }; - - fshostusb_fck: clock-fshostusb-fck@5 { - reg = <5>; - #clock-cells = <0>; - compatible = "ti,wait-gate-clock"; - clock-output-names = "fshostusb_fck"; - clocks = <&core_48m_fck>; - }; - - ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1@0 { - reg = <0>; - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; - clock-output-names = "ssi_ssr_gate_fck_3430es1"; - clocks = <&corex2_fck>; - }; - }; - - clock@a40 { - compatible = "ti,clksel"; - reg = <0xa40>; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - ssi_ssr_div_fck_3430es1: clock-ssi-ssr-div-fck-3430es1@8 { - reg = <8>; - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "ssi_ssr_div_fck_3430es1"; - clocks = <&corex2_fck>; - ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; - }; - - usb_l4_div_ick: clock-usb-l4-div-ick@4 { - reg = <4>; - #clock-cells = <0>; - compatible = "ti,composite-divider-clock"; - clock-output-names = "usb_l4_div_ick"; - clocks = <&l4_ick>; - ti,max-div = <1>; - ti,index-starts-at-one; - }; - }; - - ssi_ssr_fck: ssi_ssr_fck_3430es1 { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>; - }; - - ssi_sst_fck: ssi_sst_fck_3430es1 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&ssi_ssr_fck>; - clock-mult = <1>; - clock-div = <2>; - }; - - clock@a10 { - compatible = "ti,clksel"; - reg = <0xa10>; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - hsotgusb_ick_3430es1: clock-hsotgusb-ick-3430es1@4 { - reg = <4>; - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clock-output-names = "hsotgusb_ick_3430es1"; - clocks = <&core_l3_ick>; - }; - - fac_ick: clock-fac-ick@8 { - reg = <8>; - #clock-cells = <0>; - compatible = "ti,omap3-interface-clock"; - clock-output-names = "fac_ick"; - clocks = <&core_l4_ick>; - }; - - ssi_ick: clock-ssi-ick-3430es1@0 { - reg = <0>; - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clock-output-names = "ssi_ick_3430es1"; - clocks = <&ssi_l4_ick>; - }; - - usb_l4_gate_ick: clock-usb-l4-gate-ick@5 { - reg = <5>; - #clock-cells = <0>; - compatible = "ti,composite-interface-clock"; - clock-output-names = "usb_l4_gate_ick"; - clocks = <&l4_ick>; - }; - }; - - ssi_l4_ick: ssi_l4_ick { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&l4_ick>; - clock-mult = <1>; - clock-div = <1>; - }; - - usb_l4_ick: usb_l4_ick { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; - }; - - clock@e00 { - compatible = "ti,clksel"; - reg = <0xe00>; - #clock-cells = <2>; - #address-cells = <1>; - #size-cells = <0>; - - dss1_alwon_fck: clock-dss1-alwon-fck-3430es1@0 { - reg = <0>; - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clock-output-names = "dss1_alwon_fck_3430es1"; - clocks = <&dpll4_m4x2_ck>; - ti,set-rate-parent; - }; - }; - - dss_ick: dss_ick_3430es1@e10 { - #clock-cells = <0>; - compatible = "ti,omap3-no-wait-interface-clock"; - clocks = <&l4_ick>; - reg = <0x0e10>; - ti,bit-shift = <0>; - }; -}; - -&cm_clockdomains { - core_l3_clkdm: core_l3_clkdm { - compatible = "ti,clockdomain"; - clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>; - }; - - gfx_3430es1_clkdm: gfx_3430es1_clkdm { - compatible = "ti,clockdomain"; - clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>; - }; - - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>, - <&dss1_alwon_fck>, <&dss_ick>; - }; - - d2d_clkdm: d2d_clkdm { - compatible = "ti,clockdomain"; - clocks = <&d2d_26m_fck>; - }; - - core_l4_clkdm: core_l4_clkdm { - compatible = "ti,clockdomain"; - clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, - <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, - <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, - <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, - <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, - <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, - <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, - <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, - <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, - <&fshostusb_fck>, <&fac_ick>, <&ssi_ick>; - }; -}; From 1e79c330713efba3f4200c80e4aa68d7393edfac Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Wed, 24 Dec 2025 10:34:57 +0100 Subject: [PATCH 348/757] ARM: dts: ti/omap: omap*: fix watchdog node names Watchdog nodes should be named watchdog@ and not wdg@. Fix that. Signed-off-by: Andreas Kemnade Link: https://patch.msgid.link/20251224093457.558477-1-andreas@kemnade.info Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/omap2430.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap3.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap4-l4.dtsi | 2 +- arch/arm/boot/dts/ti/omap/omap5-l4.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/omap2430.dtsi b/arch/arm/boot/dts/ti/omap/omap2430.dtsi index b9a9e6e45266..222613d2a4d1 100644 --- a/arch/arm/boot/dts/ti/omap/omap2430.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap2430.dtsi @@ -332,7 +332,7 @@ interrupts = <93>; }; - wd_timer2: wdt@49016000 { + wd_timer2: watchdog@49016000 { compatible = "ti,omap2-wdt"; ti,hwmods = "wd_timer2"; reg = <0x49016000 0x80>; diff --git a/arch/arm/boot/dts/ti/omap/omap3.dtsi b/arch/arm/boot/dts/ti/omap/omap3.dtsi index 817474ee2d13..959069e24730 100644 --- a/arch/arm/boot/dts/ti/omap/omap3.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap3.dtsi @@ -553,7 +553,7 @@ status = "disabled"; }; - wdt2: wdt@48314000 { + wdt2: watchdog@48314000 { compatible = "ti,omap3-wdt"; reg = <0x48314000 0x80>; ti,hwmods = "wd_timer2"; diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi index 59f546a278f8..78ac3d4eceb5 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4-abe.dtsi @@ -279,7 +279,7 @@ ranges = <0x0 0x30000 0x1000>, <0x49030000 0x49030000 0x1000>; - wdt3: wdt@0 { + wdt3: watchdog@0 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = ; diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi index 4ee53dfb71b4..4881dd674393 100644 --- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi @@ -1133,7 +1133,7 @@ #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; - wdt2: wdt@0 { + wdt2: watchdog@0 { compatible = "ti,omap4-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = ; diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi index 9f6100c7c34d..487259132ebf 100644 --- a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi @@ -2393,7 +2393,7 @@ #size-cells = <1>; ranges = <0x0 0x4000 0x1000>; - wdt2: wdt@0 { + wdt2: watchdog@0 { compatible = "ti,omap5-wdt", "ti,omap3-wdt"; reg = <0x0 0x80>; interrupts = ; From 76f88d2edd9f21acad7be8422069403118708455 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 31 Dec 2025 01:40:40 +0200 Subject: [PATCH 349/757] ARM: dts: omap: dra7: Remove bogus #syscon-cells property There is no such dt binding property as '#syscon-cells', remove it. Signed-off-by: Vladimir Zapolskiy Link: https://patch.msgid.link/20251230234040.2083889-1-vz@mleia.com Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi index c9282f57ffa5..db6c53bbaf51 100644 --- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi @@ -109,7 +109,6 @@ scm_conf1: scm_conf@1c04 { compatible = "syscon"; reg = <0x1c04 0x0020>; - #syscon-cells = <2>; }; scm_conf_pcie: scm_conf@1c24 { From d88771fda13f2e97a056d471b7b7c11bd17da148 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:28 +0900 Subject: [PATCH 350/757] dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6) Document the Milos-based The Fairphone (Gen. 6) smartphone. Acked-by: Rob Herring (Arm) Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-4-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index cade15d098bc..d48c625d3fc4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - enum: + - fairphone,fp6 + - const: qcom,milos + - items: - enum: - microsoft,dempsey From 446f4802aa6eb972718b8708188df533b38dbabe Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:29 +0900 Subject: [PATCH 351/757] arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default Keep the different PMIC definitions in pm8550vs.dtsi disabled by default, and only enable them in boards explicitly. This allows to support boards better which only have pm8550vs_c, like the Milos/SM7635-based Fairphone (Gen. 6). Note: I assume that at least some of these devices with PM8550VS also don't have _c, _d, _e and _g, but this patch is keeping the resulting devicetree the same as before this change, disabling them on boards that don't actually have those is out of scope for this patch. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-5-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 16 ++++++++++++++++ .../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 16 ++++++++++++++++ 10 files changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi index 6426b431616b..7b5898c263ad 100644 --- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -98,6 +98,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8550vs_c_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -122,6 +124,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8550vs_d_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -146,6 +150,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8550vs_e_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; @@ -170,6 +176,8 @@ #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + pm8550vs_g_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index e6ac529e6b72..e6ebb643203b 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -366,6 +366,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 599850c48494..ee13e6136a82 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1107,6 +1107,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index f430038bd402..94ed1c221856 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -789,6 +789,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 3d35a9c6fdb0..c35d4737a412 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -1002,6 +1002,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index b4ef40ae2cd9..81c02ee27fe9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -533,6 +533,22 @@ }; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index d90dc7b37c4a..0e6ed6fce614 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -661,6 +661,22 @@ }; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pm8550vs_g_gpios { cam_pwr_a_cs: cam-pwr-a-cs-state { pins = "gpio4"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 5bf1af3308ce..eabc828c05b4 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1046,6 +1046,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index c67bbace2743..bb688a5d21c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -692,6 +692,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index f990e68c7a87..087828c60692 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1045,6 +1045,22 @@ vdd3-supply = <&vreg_l5b_3p1>; }; +&pm8550vs_c { + status = "okay"; +}; + +&pm8550vs_d { + status = "okay"; +}; + +&pm8550vs_e { + status = "okay"; +}; + +&pm8550vs_g { + status = "okay"; +}; + &qup_i2c3_data_clk { /* Use internal I2C pull-up */ bias-pull-up = <2200>; From 57e89dfdfa28810f8c1a44bdd301fca287ff83d1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:30 +0900 Subject: [PATCH 352/757] arm64: dts: qcom: Add PM7550 PMIC Add a dts for the PMIC used e.g. with Milos SoC-based devices. Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-6-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7550.dtsi | 67 ++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm7550.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm7550.dtsi b/arch/arm64/boot/dts/qcom/pm7550.dtsi new file mode 100644 index 000000000000..b886c2397fe7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7550.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include + +/ { + thermal-zones { + pm7550_thermal: pm7550-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pm7550_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + /* + * Current Linux driver currently only supports up to + * 125°C, should be updated to 145°C once available. + */ + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pm7550: pmic@1 { + compatible = "qcom,pm7550", "qcom,spmi-pmic"; + reg = <0x1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7550_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7550_gpios: gpio@8800 { + compatible = "qcom,pm7550-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7550_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm7550_flash: led-controller@ee00 { + compatible = "qcom,pm7550-flash-led", "qcom,spmi-flash-led"; + reg = <0xee00>; + status = "disabled"; + }; + }; +}; From 8f42f255dfb80e57af98191e7a4e18f7d1cdcb7e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:31 +0900 Subject: [PATCH 353/757] arm64: dts: qcom: Add PMIV0104 PMIC Add a dts for the PMIC used e.g. on devices with the Milos SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-7-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmiv0104.dtsi | 73 ++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmiv0104.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmiv0104.dtsi b/arch/arm64/boot/dts/qcom/pmiv0104.dtsi new file mode 100644 index 000000000000..85ee8911d93e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmiv0104.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include + +/ { + thermal-zones { + pmiv0104-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&pmiv0104_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + /* + * Current Linux driver currently only supports up to + * 125°C, should be updated to 145°C once available. + */ + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmic@PMIV0104_SID { + compatible = "qcom,pmiv0104", "qcom,spmi-pmic"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + pmiv0104_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = ; + #thermal-sensor-cells = <0>; + }; + + pmiv0104_gpios: gpio@8800 { + compatible = "qcom,pmiv0104-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmiv0104_gpios 0 0 10>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pmiv0104_eusb2_repeater: phy@fd00 { + compatible = "qcom,pmiv0104-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; From d9d59d105f98665187d90a49d9099675491990f6 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:32 +0900 Subject: [PATCH 354/757] arm64: dts: qcom: Add initial Milos dtsi Add a devicetree description for the Milos SoC, which is for example Snapdragon 7s Gen 3 (SM7635). Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-8-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/milos.dtsi | 2633 +++++++++++++++++++++++++++ 1 file changed, 2633 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/milos.dtsi diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi new file mode 100644 index 000000000000..e1a51d43943f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -0,0 +1,2633 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <76800000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x0>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd0>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x100>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd1>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x200>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd2>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0x0 0x300>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&cpu_pd3>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_2>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x400>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd4>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_4>; + capacity-dmips-mhz = <1670>; + dynamic-power-coefficient = <264>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + #cooling-cells = <2>; + + l2_4: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x500>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd5>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_5>; + capacity-dmips-mhz = <1670>; + dynamic-power-coefficient = <264>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + #cooling-cells = <2>; + + l2_5: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x600>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&cpu_pd6>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_6>; + capacity-dmips-mhz = <1670>; + dynamic-power-coefficient = <264>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + #cooling-cells = <2>; + + l2_6: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0x0 0x700>; + + clocks = <&cpufreq_hw 2>; + + power-domains = <&cpu_pd7>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&l2_7>; + capacity-dmips-mhz = <1670>; + dynamic-power-coefficient = <287>; + + qcom,freq-domain = <&cpufreq_hw 2>; + + #cooling-cells = <2>; + + l2_7: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + silver_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "pc"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <250>; + exit-latency-us = <700>; + min-residency-us = <5200>; + local-timer-stop; + }; + + silver_cpu_sleep_1: cpu-sleep-0-1 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + local-timer-stop; + }; + + gold_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <5511>; + local-timer-stop; + }; + + gold_cpu_sleep_1: cpu-sleep-1-1 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1300>; + min-residency-us = <8136>; + local-timer-stop; + }; + + gold_plus_cpu_sleep_0: cpu-sleep-2-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-plus-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1500>; + min-residency-us = <8551>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41003344>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-milos", "qcom,scm"; + qcom,dload-mode = <&tcsr 0x19000>; + }; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,milos-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,milos-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + memory@0 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0 0 0>; + }; + + pmu-a520 { + compatible = "arm,cortex-a520-pmu"; + interrupts = ; + }; + + pmu-a720 { + compatible = "arm,cortex-a720-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + domain-idle-states = <&gold_plus_cpu_sleep_0>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp-region@80000000 { + reg = <0x0 0x80000000 0x0 0xe00000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@81800000 { + reg = <0x0 0x81800000 0x0 0x40000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@81840000 { + reg = <0x0 0x81840000 0x0 0x1c0000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@81a00000 { + reg = <0x0 0x81a00000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@81a40000 { + reg = <0x0 0x81a40000 0x0 0x1c0000>; + no-map; + }; + + aop_image_mem: aop-image-region@81c00000 { + reg = <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config-region@81c80000 { + reg = <0x0 0x81c80000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@81ca0000 { + reg = <0x0 0x81ca0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log-region@81ce0000 { + reg = <0x0 0x81ce0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log-region@81ce4000 { + reg = <0x0 0x81ce4000 0x0 0x10000>; + no-map; + }; + + chipinfo_mem: chipinfo-region@81cf4000 { + reg = <0x0 0x81cf4000 0x0 0x1000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@81cff000 { + reg = <0x0 0x81cff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem-region@81d00000 { + compatible = "qcom,smem"; + reg = <0x0 0x81d00000 0x0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg = <0x0 0x81f00000 0x0 0x20000>; + no-map; + }; + + pvm_fw_mem: pvm-fw-region@824a0000 { + reg = <0x0 0x824a0000 0x0 0x100000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@825a0000 { + reg = <0x0 0x825a0000 0x0 0x60000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg = <0x0 0x82600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg = <0x0 0x82700000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@82800000 { + reg = <0x0 0x82800000 0x0 0x2000000>; + reusable; + }; + + mpss_mem: mpss-region@8ac00000 { + reg = <0x0 0x8ac00000 0x0 0xe600000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 { + reg = <0x0 0x99200000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 { + reg = <0x0 0x99280000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@99300000 { + reg = <0x0 0x99300000 0x0 0x2800000>; + no-map; + }; + + wpss_mem: wpss-region@9bb00000 { + reg = <0x0 0x9bb00000 0x0 0x1900000>; + no-map; + }; + + video_mem: video-region@9d400000 { + reg = <0x0 0x9d400000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9db00000 { + reg = <0x0 0x9db00000 0x0 0xf00000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 { + reg = <0x0 0x9ea00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9ea80000 { + reg = <0x0 0x9ea80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9ea90000 { + reg = <0x0 0x9ea90000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@9ea9a000 { + reg = <0x0 0x9ea9a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera-region@9eb00000 { + reg = <0x0 0x9eb00000 0x0 0x800000>; + no-map; + }; + + wlan_msa_mem: wlan-msa-region@a6400000 { + reg = <0x0 0xa6400000 0x0 0xc00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@e0600000 { + reg = <0x0 0xe0600000 0x0 0x400000>; + no-map; + }; + + rmtfs_mem: rmtfs@e1f00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xe1f00000 0x0 0x600000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = ; + }; + + qtee_mem: qtee-region@e8900000 { + reg = <0x0 0xe8900000 0x0 0x500000>; + no-map; + }; + + tags_mem: tags-region@e8e00000 { + reg = <0x0 0xe8e00000 0x0 0x700000>; + no-map; + }; + + trusted_apps_mem: trusted-apps-region@e9500000 { + reg = <0x0 0xe9500000 0x0 0x1200000>; + no-map; + }; + }; + + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-wpss { + compatible = "qcom,smp2p"; + qcom,smem = <617>, <616>; + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <13>; + + smp2p_wpss_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wpss_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + smp2p_wlan_out: wlan-ap-to-wpss { + qcom,entry-name = "wlan"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_wlan_in: wlan-wpss-to-ap { + qcom,entry-name = "wlan"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x10 0>; + ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,milos-gcc"; + reg = <0x0 0x00100000 0x0 0x1f4200>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* pcie_0_pipe_clk */ + <0>, /* pcie_1_pipe_clk */ + <0>, /* ufs_phy_rx_symbol_0_clk */ + <0>, /* ufs_phy_rx_symbol_1_clk */ + <0>, /* ufs_phy_tx_symbol_0_clk */ + <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + ipcc: mailbox@405000 { + compatible = "qcom,milos-ipcc", "qcom,ipcc"; + reg = <0x0 0x00405000 0x0 0x1000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + gpi_dma1: dma-controller@800000 { + compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00800000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x36 0x0>; + dma-coherent; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core"; + + iommus = <&apps_smmu 0x23 0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c7: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart11: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00890000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + gpi_dma0: dma-controller@a00000 { + compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x0 0x00a00000 0x0 0x60000>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels = <12>; + dma-channel-mask = <0x3e>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x576 0x0>; + dma-coherent; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x00ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core"; + + iommus = <&apps_smmu 0x563 0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart5: serial@a94000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x00a94000 0x0 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart5_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible = "qcom,milos-trng", "qcom,trng"; + reg = <0x0 0x010c3000 0x0 0x1000>; + }; + + mmss_noc: interconnect@1400000 { + compatible = "qcom,milos-mmss-noc"; + reg = <0x0 0x01400000 0x0 0xdb800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,milos-cnoc-main"; + reg = <0x0 0x01500000 0x0 0x14400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cnoc_cfg: interconnect@1600000 { + compatible = "qcom,milos-cnoc-cfg"; + reg = <0x0 0x01600000 0x0 0x6e00>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,milos-system-noc"; + reg = <0x0 0x01680000 0x0 0x40000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible = "qcom,milos-pcie-anoc"; + reg = <0x0 0x016c0000 0x0 0x12400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,milos-aggre1-noc"; + reg = <0x0 0x016e0000 0x0 0x16400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,milos-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1f400>; + #interconnect-cells = <2>; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,milos-tcsr", "syscon"; + reg = <0x0 0x01fc0000 0x0 0xa0000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible = "qcom,milos-adsp-pas"; + reg = <0x0 0x03000000 0x0 0x10000>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + interconnects = <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,milos-lpass-ag-noc"; + reg = <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,milos-gpucc"; + reg = <0x0 0x03d90000 0x0 0x9800>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible = "qcom,milos-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = "hlos", + "bus", + "iface", + "ahb"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,milos-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names = "cx", + "mss"; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&mpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "mpss"; + qcom,remote-pid = <1>; + }; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,milos-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x0 0x08804000 0x0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + iommus = <&apps_smmu 0x540 0>; + + bus-width = <4>; + + qcom,dll-config = <0x0007442c>; + qcom,ddr-config = <0x80040868>; + + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,milos-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0x0 0x088e3000 0x0 0x154>; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status = "disabled"; + }; + + remoteproc_wpss: remoteproc@8a00000 { + compatible = "qcom,milos-wpss-pas"; + reg = <0x0 0x08a00000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + memory-region = <&wpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_wpss_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "wpss"; + qcom,remote-pid = <13>; + }; + }; + + usb_1: usb@a600000 { + compatible = "qcom,milos-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc000>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + iommus = <&apps_smmu 0x40 0x0>; + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + + phys = <&usb_1_hsphy>; + phy-names = "usb2-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,parkmode-disable-ss-quirk; + tx-fifo-resize; + dma-coherent; + usb-role-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,milos-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + camcc: clock-controller@adb0000 { + compatible = "qcom,milos-camcc"; + reg = <0x0 0x0adb0000 0x0 0x40000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,milos-dispcc"; + reg = <0x0 0x0af00000 0x0 0x20000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, /* dsi0_phy_pll_out_byteclk */ + <0>, /* dsi0_phy_pll_out_dsiclk */ + <0>, /* dp0_phy_pll_link_clk */ + <0>; /* dp0_phy_pll_vco_div_clk */ + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,milos-pdc", "qcom,pdc"; + reg = <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x174000f0 0x0 0x64>; + interrupt-parent = <&intc>; + + qcom,pdc-ranges = <0 480 40>, <40 140 11>, <51 527 47>, + <98 609 31>, <129 63 1>, <130 716 12>, + <142 251 5>; + + #interrupt-cells = <2>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c228000 { + compatible = "qcom,milos-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c228000 0x0 0x1000>, + <0x0 0x0c222000 0x0 0x1000>; + + interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <15>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible = "qcom,milos-tsens", "qcom,tsens-v2"; + reg = <0x0 0x0c229000 0x0 0x1000>, + <0x0 0x0c223000 0x0 0x1000>; + + interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <14>; + + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,milos-aoss-qmp", "qcom,aoss-qmp"; + reg = <0x0 0x0c300000 0x0 0x400>; + + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0x0 0x0c3f0000 0x0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,milos-tlmm"; + reg = <0x0 0x0f100000 0x0 0x300000>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 168>; + + wakeup-parent = <&pdc>; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio15", "gpio16"; + function = "qup0_se3"; + drive-strength = <2>; + bias-pull-up = <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio3"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins = "gpio25", "gpio26"; + function = "qup0_se5"; + drive-strength = <2>; + bias-disable; + }; + + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins = "gpio50", "gpio51"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_uart11_cts_rts: qup-uart11-cts-rts-state { + /* CTS, RTS */ + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-down; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "gpio62"; + function = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "gpio61"; + function = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "gpio58", "gpio57", "gpio35", "gpio34"; + function = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "gpio61"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "gpio58", "gpio57", "gpio35", "gpio34"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17100000 0x0 0x10000>, + <0x0 0x17180000 0x0 0x200000>; + + interrupts = ; + + #interrupt-cells = <4>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0 0x40000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x17140000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + + interrupts = , + ; + + frame-number = <0>; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + + interrupts = ; + + frame-number = <1>; + + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + + interrupts = ; + + frame-number = <2>; + + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + + interrupts = ; + + frame-number = <3>; + + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + + interrupts = ; + + frame-number = <4>; + + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + + interrupts = ; + + frame-number = <5>; + + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + + interrupts = ; + + frame-number = <6>; + + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + + interrupts = , + , + ; + + power-domains = <&cluster_pd>; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,milos-rpmh-clk"; + + clocks = <&xo_board>; + clock-names = "xo"; + + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,milos-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPLL0>; + clock-names = "xo", + "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,milos-gem-noc"; + reg = <0x0 0x24100000 0x0 0xff080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,milos-nsp-noc"; + reg = <0x0 0x320c0000 0x0 0xe080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,milos-cdsp-pas"; + reg = <0x0 0x32300000 0x0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + thermal-sensors = <&tsens0 0>; + + trips { + aoss0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors = <&tsens0 1>; + + trips { + cpuss0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors = <&tsens0 2>; + + trips { + cpuss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu4-left-thermal { + thermal-sensors = <&tsens0 3>; + + trips { + cpu4-left-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-right-thermal { + thermal-sensors = <&tsens0 4>; + + trips { + cpu4-right-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-left-thermal { + thermal-sensors = <&tsens0 5>; + + trips { + cpu5-left-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-right-thermal { + thermal-sensors = <&tsens0 6>; + + trips { + cpu5-right-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-left-thermal { + thermal-sensors = <&tsens0 7>; + + trips { + cpu6-left-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-right-thermal { + thermal-sensors = <&tsens0 8>; + + trips { + cpu6-right-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-left-thermal { + thermal-sensors = <&tsens0 9>; + + trips { + cpu7-left-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-right-thermal { + thermal-sensors = <&tsens0 10>; + + trips { + cpu7-right-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors = <&tsens0 11>; + + trips { + cpu0-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + thermal-sensors = <&tsens0 12>; + + trips { + cpu1-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + thermal-sensors = <&tsens0 13>; + + trips { + cpu2-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + thermal-sensors = <&tsens0 14>; + + trips { + cpu3-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors = <&tsens1 0>; + + trips { + aoss1-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + aoss1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 1>; + + trips { + nsphvx0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphvx0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 2>; + + trips { + nsphmx1-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphmx1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 3>; + + trips { + nsphmx0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + nsphmx0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 4>; + + trips { + gpu0_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + gpuss0-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 5>; + + trips { + gpu1_alert0: trip-point0 { + temperature = <85000>; + hysteresis = <1000>; + type = "passive"; + }; + + trip-point1 { + temperature = <90000>; + hysteresis = <1000>; + type = "hot"; + }; + + gpuss1-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors = <&tsens1 7>; + + trips { + video-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + video-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <10>; + + thermal-sensors = <&tsens1 8>; + + trips { + ddr-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + ddr-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors = <&tsens1 9>; + + trips { + camera0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + camera0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&tsens1 10>; + + trips { + modem0-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem0-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&tsens1 11>; + + trips { + modem1-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem1-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&tsens1 12>; + + trips { + modem2-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem2-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <100>; + + thermal-sensors = <&tsens1 13>; + + trips { + modem3-hot { + temperature = <110000>; + hysteresis = <1000>; + type = "hot"; + }; + + modem3-critical { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = , + , + , + ; + }; +}; From e25834d7691f0661fa9700c167c48d18752f62bf Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 10 Dec 2025 10:43:33 +0900 Subject: [PATCH 355/757] arm64: dts: qcom: Add The Fairphone (Gen. 6) Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based on the Milos/SM7635 SoC. Supported functionality as of this initial submission: * Debug UART * Regulators (PM7550, PM8550VS, PMR735B, PM8008) * Remoteprocs (ADSP, CDSP, MPSS, WPSS) * Power Button, Volume Keys, Switch * PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching) * Camera flash/torch LED * SD card * USB Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251210-sm7635-fp6-initial-v4-9-b05fddd8b45c@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/milos-fairphone-fp6.dts | 790 ++++++++++++++++++ 2 files changed, 791 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ce29b26473b3..0ccd6ec16dfb 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -39,6 +39,7 @@ lemans-evk-camera-dtbs := lemans-evk.dtb lemans-evk-camera.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb +dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts new file mode 100644 index 000000000000..52895dd9e4fa --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -0,0 +1,790 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +/dts-v1/; + +#define PMIV0104_SID 7 + +#include +#include +#include +#include "milos.dtsi" +#include "pm7550.dtsi" +#include "pm8550vs.dtsi" +#include "pmiv0104.dtsi" /* PMIV0108 */ +#include "pmk8550.dtsi" /* PMK7635 */ +#include "pmr735b.dtsi" + +/ { + model = "The Fairphone (Gen. 6)"; + compatible = "fairphone,fp6", "qcom,milos"; + chassis-type = "handset"; + + aliases { + serial0 = &uart5; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_default>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm7550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + switch { + label = "Switch"; + gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + linux,code = ; + }; + }; + + pmic-glink { + compatible = "qcom,milos-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 131 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + }; + }; + }; + + vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 { + compatible = "regulator-fixed"; + regulator-name = "ff_afvdd_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <100>; + + gpio = <&tlmm 93 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 { + compatible = "regulator-fixed"; + regulator-name = "uw_afvdd_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + startup-delay-us = <100>; + + gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_uw_dvdd: regulator-uw-dvdd { + compatible = "regulator-fixed"; + regulator-name = "uw_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <100>; + + gpio = <&tlmm 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_s1b>; + }; + + vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 { + compatible = "regulator-fixed"; + regulator-name = "ois_avdd0_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <100>; + + gpio = <&tlmm 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_bob>; + }; + + vreg_ois_vdd: regulator-ois-vdd { + compatible = "regulator-fixed"; + regulator-name = "ois_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100>; + + gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 { + compatible = "regulator-fixed"; + regulator-name = "oled_dvdd_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 54 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_s2b>; + + regulator-boot-on; + }; + + vreg_s1j: regulator-pm3001a-s1j { + compatible = "regulator-fixed"; + regulator-name = "pm3001a_s1j"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + startup-delay-us = <1000>; + + gpio = <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + + pinctrl-0 = <&s1j_enable_default>; + pinctrl-names = "default"; + }; + + vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 { + compatible = "regulator-fixed"; + regulator-name = "vtof_ldo_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100>; + + gpio = <&tlmm 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + thermal-zones { + pm8008-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&pm8008>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1b>; + vdd-l2-l3-supply = <&vreg_s3b>; + vdd-l4-l5-supply = <&vreg_s2b>; + vdd-l6-supply = <&vreg_s2b>; + vdd-l7-supply = <&vreg_s1b>; + vdd-l8-supply = <&vreg_s1b>; + vdd-l9-l10-supply = <&vreg_s1b>; + vdd-l11-supply = <&vreg_s1b>; + vdd-l12-l14-supply = <&vreg_bob>; + vdd-l13-l16-supply = <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply = <&vreg_bob>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "b"; + + vreg_s1b: smps1 { + regulator-name = "vreg_s1b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2080000>; + regulator-initial-mode = ; + }; + + vreg_s2b: smps2 { + regulator-name = "vreg_s2b"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1408000>; + regulator-initial-mode = ; + }; + + vreg_s3b: smps3 { + regulator-name = "vreg_s3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <1040000>; + regulator-initial-mode = ; + }; + + vreg_l2b: ldo2 { + regulator-name = "vreg_l2b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3b: ldo3 { + regulator-name = "vreg_l3b"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l4b: ldo4 { + regulator-name = "vreg_l4b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l5b: ldo5 { + regulator-name = "vreg_l5b"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b: ldo7 { + regulator-name = "vreg_l7b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8b: ldo8 { + regulator-name = "vreg_l8b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9b: ldo9 { + regulator-name = "vreg_l9b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l10b: ldo10 { + regulator-name = "vreg_l10b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11b: ldo11 { + regulator-name = "vreg_l11b"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l12b: ldo12 { + regulator-name = "vreg_l12b"; + /* + * Skip voltage voting for UFS VCC. + */ + regulator-initial-mode = ; + }; + + vreg_l13b: ldo13 { + regulator-name = "vreg_l13b"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vreg_l14b: ldo14 { + regulator-name = "vreg_l14b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l15b: ldo15 { + regulator-name = "vreg_l15b"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l16b: ldo16 { + regulator-name = "vreg_l16b"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l17b: ldo17 { + regulator-name = "vreg_l17b"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l18b: ldo18 { + regulator-name = "vreg_l18b"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = ; + }; + + vreg_l19b: ldo19 { + regulator-name = "vreg_l19b"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l20b: ldo20 { + regulator-name = "vreg_l20b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l21b: ldo21 { + regulator-name = "vreg_l21b"; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l22b: ldo22 { + regulator-name = "vreg_l22b"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = ; + }; + + vreg_l23b: ldo23 { + regulator-name = "vreg_l23b"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3b>; + vdd-l3-supply = <&vreg_s3b>; + + qcom,pmic-id = "c"; + + vreg_l2c: ldo2 { + regulator-name = "vreg_l2c"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + }; + + regulators-2 { + compatible = "qcom,pmr735b-rpmh-regulators"; + + vdd-l1-l2-supply= <&vreg_s3b>; + vdd-l3-supply= <&vreg_s3b>; + vdd-l4-supply= <&vreg_s1b>; + vdd-l5-supply= <&vreg_s2b>; + vdd-l6-supply= <&vreg_s2b>; + vdd-l7-l8-supply= <&vreg_s2b>; + vdd-l9-supply= <&vreg_s3b>; + vdd-l10-supply= <&vreg_s1b>; + vdd-l11-supply= <&vreg_s3b>; + vdd-l12-supply= <&vreg_s3b>; + + qcom,pmic-id = "f"; + + vreg_l1f: ldo1 { + regulator-name = "vreg_l1f"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + }; + + vreg_l2f: ldo2 { + regulator-name = "vreg_l2f"; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + regulator-initial-mode = ; + }; + + vreg_l3f: ldo3 { + regulator-name = "vreg_l3f"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vreg_l4f: ldo4 { + regulator-name = "vreg_l4f"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + }; + + vreg_l5f: ldo5 { + regulator-name = "vreg_l5f"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + vreg_l6f: ldo6 { + regulator-name = "vreg_l6f"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7f: ldo7 { + regulator-name = "vreg_l7f"; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + }; + + vreg_l8f: ldo8 { + regulator-name = "vreg_l8f"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1320000>; + regulator-initial-mode = ; + }; + + vreg_l9f: ldo9 { + regulator-name = "vreg_l9f"; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + regulator-initial-mode = ; + }; + + vreg_l10f: ldo10 { + regulator-name = "vreg_l10f"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l11f: ldo11 { + regulator-name = "vreg_l11f"; + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <864000>; + regulator-initial-mode = ; + }; + }; +}; + +&gcc { + protected-clocks = , , + , , + , , + , , + , , + , ; +}; + +&i2c1 { + /* Samsung NFC @ 0x27 */ + + status = "okay"; +}; + +&i2c3 { + /* AW88261FCR amplifier (top) @ 0x34 */ + /* AW88261FCR amplifier (bottom) @ 0x35 */ + + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&vreg_s2b>; + vdd-l3-l4-supply = <&vreg_bob>; + vdd-l5-supply = <&vreg_bob>; + vdd-l6-supply = <&vreg_s1b>; + vdd-l7-supply = <&vreg_bob>; + + pinctrl-0 = <&pm8008_int_default>, <&pm8008_reset_n_default>; + pinctrl-names = "default"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1144000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3000000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1896000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; + + /* VL53L3 ToF @ 0x29 */ + /* AW86938FCR vibrator @ 0x5a */ +}; + +&pm8550vs_c { + status = "okay"; +}; + +&pmiv0104_eusb2_repeater { + vdd18-supply = <&vreg_l7b>; + vdd3-supply = <&vreg_l17b>; + + qcom,tune-res-fsdif = /bits/ 8 <0x5>; + qcom,tune-usb2-amplitude = /bits/ 8 <0x8>; + qcom,tune-usb2-disc-thres = /bits/ 8 <0x7>; + qcom,tune-usb2-preem = /bits/ 8 <0x6>; +}; + +&pmr735b_gpios { + s1j_enable_default: s1j-enable-default-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <0>; + bias-disable; + output-low; + }; + + pm8008_reset_n_default: pm8008-reset-n-default-state { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-down; + }; +}; + +&pm7550_gpios { + volume_up_default: volume-up-default-state { + pins = "gpio6"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <1>; + bias-pull-up; + }; +}; + +&pm7550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = ; + led-sources = <1>, <4>; + led-max-microamp = <350000>; + flash-max-microamp = <1500000>; + flash-max-timeout-us = <400000>; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/milos/fairphone/fp6/adsp.mbn", + "qcom/milos/fairphone/fp6/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/milos/fairphone/fp6/cdsp.mbn", + "qcom/milos/fairphone/fp6/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/milos/fairphone/fp6/modem.mbn"; + + status = "okay"; +}; + +&remoteproc_wpss { + firmware-name = "qcom/milos/fairphone/fp6/wpss.mbn"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&tlmm 65 GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vreg_l13b>; + vqmmc-supply = <&vreg_l23b>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&spi0 { + /* Eswin EPH8621 touchscreen @ 0 */ +}; + +&tlmm { + gpio-reserved-ranges = <8 4>, /* Fingerprint SPI */ + <13 1>, /* NC */ + <63 2>; /* WLAN UART */ + + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + pm8008_int_default: pm8008-int-default-state { + pins = "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart5 { + status = "okay"; +}; + +&usb_1 { + dr_mode = "otg"; + + /* USB 2.0 only, HW does not support USB 3.x */ + qcom,select-utmi-as-pipe-clk; + + status = "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l2b>; + vdda12-supply = <&vreg_l4b>; + + phys = <&pmiv0104_eusb2_repeater>; + + status = "okay"; +}; From e06a177d819570014ca627a062b38a032a816165 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 11:59:13 -0600 Subject: [PATCH 356/757] arm64: dts: xilinx: Drop "label" property on dlg,slg7xl45106 The "label" property is not documented for the dlg,slg7xl45106. Nor is it common to use for GPIO controllers. So drop it. Signed-off-by: Rob Herring (Arm) Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20251216175914.2791200-1-robh@kernel.org --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso | 1 - arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 1 - arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso index 02be5e1e8686..d0230da47068 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -75,7 +75,6 @@ slg7xl45106: gpio@11 { /* u13 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "", diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso index b92dcb86e87e..5d1f031bbd89 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -103,7 +103,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso index 99ad220d13d6..1d5c95bd6073 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -104,7 +104,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", From 4310a370a323901b42f0ddd119a53af723f3359b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 15 Dec 2025 09:02:05 +0100 Subject: [PATCH 357/757] arm64: zynqmp: Remove ina260 IIO description Kernel has only hwmon driver that's why there is no reason to wire iio to hwmon converter which was describing out of tree ina260 IIO. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7e57f76deca9e73be3fcb914aed119f567c9bf8a.1765785722.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso | 6 ------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 6 ------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 6 ------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 6 ------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 6 ------ 5 files changed, 30 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso index d0230da47068..23f6695d86b4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -26,11 +26,6 @@ ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u3 { - compatible = "iio-hwmon"; - io-channels = <&u3 0>, <&u3 1>, <&u3 2>; - }; - clk_26: clock2 { /* u17 - USB */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -67,7 +62,6 @@ u3: ina260@40 { /* u3 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso index 5d1f031bbd89..b82a056be2f9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -25,11 +25,6 @@ ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - clk_27: clock0 { /* u86 - DP */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -95,7 +90,6 @@ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso index 1d5c95bd6073..4dcf92a2158f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -25,11 +25,6 @@ ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - clk_125: clock0 { /* u87 - GEM0/1 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -96,7 +91,6 @@ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index d7351a17d3e8..923a70d750bf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -32,11 +32,6 @@ ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -96,7 +91,6 @@ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a4ae37ebaccf..563e750b0e08 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -27,11 +27,6 @@ ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -92,7 +87,6 @@ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; From c0d11ff904753a99e0f6efd29e614268bc6e98db Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 6 Jan 2026 10:07:39 +0100 Subject: [PATCH 358/757] arm64: dts: qcom: sm8750: Add Iris VPU v3.5 Add Iris video codec to SM8750 SoC, which comes with significantly different powering up sequence than previous SM8650, thus different clocks and resets. For consistency keep existing clock and clock-names naming, so the list shares common part. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20260106-b4-sm8750-iris-dts-v4-1-97db1d1df3dd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 121 +++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 0a6f2a449c20..a76bf5193a70 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -2811,6 +2812,126 @@ }; }; + iris: video-codec@aa00000 { + compatible = "qcom,sm8750-iris"; + reg = <0x0 0x0aa00000 0x0 0xf0000>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun"; + + dma-coherent; + iommus = <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = ; + + memory-region = <&video_mem>; + + operating-points-v2 = <&iris_opp_table>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core"; + + /* + * IRIS firmware is signed by vendors, only + * enable in boards where the proper signed firmware + * is available. + */ + status = "disabled"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-570000000 { + opp-hz = /bits/ 64 <570000000>; + required-opps = <&rpmhpd_opp_nom_l1>, + <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8750-videocc"; + reg = <0x0 0x0aaf0000 0x0 0x10000>; + clocks = <&bi_tcxo_div2>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; From 10d764c8cb1bdaff15020115aa49ee7a0489655b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 6 Jan 2026 10:07:40 +0100 Subject: [PATCH 359/757] arm64: dts: qcom: sm8750-mtp: Enable Iris codec Enable on SM8750 MTP the Iris video codec for accelerated video encoding/decoding. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20260106-b4-sm8750-iris-dts-v4-2-97db1d1df3dd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index e77fe0ce91ca..cb718331496e 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -925,6 +925,10 @@ }; }; +&iris { + status = "okay"; +}; + &lpass_vamacro { pinctrl-0 = <&dmic01_default>, <&dmic23_default>; pinctrl-names = "default"; From ad0721bba4156d4d06c5f79b0a32e9d876f5ad0f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 6 Jan 2026 10:07:41 +0100 Subject: [PATCH 360/757] arm64: dts: qcom: sm8750-qrd: Enable Iris codec Enable on SM8750 QRD the Iris video codec for accelerated video encoding/decoding. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20260106-b4-sm8750-iris-dts-v4-3-97db1d1df3dd@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750-qrd.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts index 439ffb202599..801c46d55602 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-qrd.dts @@ -858,6 +858,10 @@ }; }; +&iris { + status = "okay"; +}; + &pm8550_flash { status = "okay"; From b7ad04269d6825b1c88de17e698a356bac5f3197 Mon Sep 17 00:00:00 2001 From: Xiangxu Yin Date: Tue, 4 Nov 2025 09:33:25 +0800 Subject: [PATCH 361/757] arm64: dts: qcom: talos: Add DisplayPort and QMP USB3-DP PHY Introduce DisplayPort controller node and associated QMP USB3-DP PHY for SM6150 SoC. Add data-lanes property to the DP endpoint and update clock assignments for proper DP integration. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Xiangxu Yin Link: https://lore.kernel.org/r/20251104-add-displayport-support-to-qcs615-devicetree-v7-3-e51669170a6f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 115 +++++++++++++++++++++++++++- 1 file changed, 113 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index d1dbfa3bd81c..208344a1a832 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -3855,6 +3856,7 @@ reg = <0>; dpu_intf0_out: endpoint { + remote-endpoint = <&mdss_dp0_in>; }; }; @@ -3887,6 +3889,89 @@ }; }; + mdss_dp0: displayport-controller@ae90000 { + compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; + + reg = <0x0 0x0ae90000 0x0 0x200>, + <0x0 0x0ae90200 0x0 0x200>, + <0x0 0x0ae90400 0x0 0x600>, + <0x0 0x0ae90a00 0x0 0x600>, + <0x0 0x0ae91000 0x0 0x600>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel", + "stream_1_pixel"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; + assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; + + phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd RPMHPD_CX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dp0_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dp0_out: endpoint { + data-lanes = <3 2 0 1>; + }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + mdss_dsi0: dsi@ae94000 { compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; reg = <0x0 0x0ae94000 0x0 0x400>; @@ -3982,8 +4067,8 @@ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, - <0>, - <0>; + <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; #clock-cells = <1>; #reset-cells = <1>; @@ -4362,6 +4447,32 @@ status = "disabled"; }; + usb_qmpphy_2: phy@88e8000 { + compatible = "qcom,qcs615-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x2000>; + + clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR >, + <&gcc GCC_USB3_DP_PHY_SEC_BCR>; + reset-names = "phy_phy", + "dp_phy"; + + #clock-cells = <1>; + #phy-cells = <1>; + + qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>; + + status = "disabled"; + }; + usb_1: usb@a6f8800 { compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; reg = <0x0 0x0a6f8800 0x0 0x400>; From b5a3112bfd5742a5d831c0bdfac2cf6e6796ac9d Mon Sep 17 00:00:00 2001 From: Xiangxu Yin Date: Tue, 4 Nov 2025 09:33:26 +0800 Subject: [PATCH 362/757] arm64: dts: qcom: qcs615-ride: Enable DisplayPort Add DP connector node and configure MDSS DisplayPort controller for QCS615 Ride platform. Include PHY supply settings to support DP output. Reviewed-by: Konrad Dybcio Signed-off-by: Xiangxu Yin Link: https://lore.kernel.org/r/20251104-add-displayport-support-to-qcs615-devicetree-v7-4-e51669170a6f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index be67eb173046..5a24c19c415e 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -39,6 +39,20 @@ }; }; + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "mini"; + + hpd-gpios = <&io_expander 8 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + dp-dsi0-connector { compatible = "dp-connector"; label = "DSI0"; @@ -423,6 +437,15 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint = <&dp0_connector_in>; +}; + &mdss_dsi0 { vdda-supply = <&vreg_l11a>; status = "okay"; @@ -624,6 +647,13 @@ status = "okay"; }; +&usb_qmpphy_2 { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + &usb_1 { status = "okay"; }; From 0b2761eb1287bd9f62367cccf6626eb3107cef6f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 Dec 2025 18:36:14 +0800 Subject: [PATCH 363/757] ARM: dts: allwinner: sun5i-a13-utoo-p66: delete "power-gpios" property The P66's device tree includes the reference design dtsi files, which defines a node and properties for the touchpanel in the common design. The P66 dts file then overrides all the properties to match its own design, but as the touchpanel model is different, a different schema is matched. This other schema uses a different name for the GPIO. The original submission added the correct GPIO property, but did not delete the one inherited from the reference design, causing validation errors. Explicitly delete the incorrect GPIO property. Fixes: 2a53aff27236 ("ARM: dts: sun5i: Enable touchscreen on Utoo P66") Reviewed-by: Jernej Skrabec Link: https://patch.msgid.link/20251225103616.3203473-4-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts index be486d28d04f..428cab5a0e90 100644 --- a/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts +++ b/arch/arm/boot/dts/allwinner/sun5i-a13-utoo-p66.dts @@ -102,6 +102,7 @@ /* The P66 uses a different EINT then the reference design */ interrupts = <6 9 IRQ_TYPE_EDGE_FALLING>; /* EINT9 (PG9) */ /* The icn8318 binding expects wake-gpios instead of power-gpios */ + /delete-property/ power-gpios; wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ touchscreen-size-x = <800>; touchscreen-size-y = <480>; From 2b8cd99c8cf489d539e1347adb5fd39548c53f19 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 25 Dec 2025 19:43:19 -0800 Subject: [PATCH 364/757] arm64: dts: rockchip: Add magnetometer sensor to Pinephone Pro Pinephone Pro uses AF8133J according to the schematic. The mount-matrix was added by Leonardo on top of Ondrej's work of adding the magnetometer. It was verified with Leonardo's compass app: https://gitlab.com/lgtrombetta/compass Co-developed-by: Leonardo G. Trombetta Signed-off-by: Leonardo G. Trombetta Signed-off-by: Ondrej Jirman Reviewed-by: Pavel Machek Signed-off-by: Rudraksha Gupta Link: https://patch.msgid.link/20251225-ppp_light_accel_mag_vol-down-v6-1-8c79a4e87001@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3399-pinephone-pro.dts | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 5e9867e934d2..a100fb96c8a5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -543,6 +543,23 @@ }; }; +&i2c4 { + af8133j: compass@1c { + compatible = "voltafield,af8133j"; + reg = <0x1c>; + avdd-supply = <&vcc_3v0>; + dvdd-supply = <&vcc_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&compass_rst_l>; + reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; + + mount-matrix = + "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + }; +}; + &io_domains { bt656-supply = <&vcc1v8_dvp>; audio-supply = <&vcca1v8_codec>; @@ -655,6 +672,12 @@ }; }; + compass { + compass_rst_l: compass-rst-l { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { red_led_pin: red-led-pin { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; From a3e4bb6c9a2262c87a842d9fa42bdd65a1671edf Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Thu, 25 Dec 2025 19:43:20 -0800 Subject: [PATCH 365/757] arm64: dts: rockchip: Add light/proximity sensor to Pinephone Pro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pinephone Pro uses STK3311 according to the schematics. Tests: ~ $ monitor-sensor --light // When the sensor is exposed, it get's fluctating values such as Light changed: 1.800000 (lux) Light changed: 1.700000 (lux) Light changed: 1.800000 (lux) Light changed: 1.700000 (lux) Light changed: 1.600000 (lux) Light changed: 1.100000 (lux) // When covering the sensor, it prints a low value and stops printing Light changed: 0.200000 (lux) ~ $ monitor-sensor --proximity // When it goes away from an object Proximity value changed: 0 // When it comes near an object Proximity value changed: 1 Co-developed-by: Martijn Braam Signed-off-by: Martijn Braam Co-developed-by: Kamil Trzciński Signed-off-by: Kamil Trzciński Signed-off-by: Ondrej Jirman Signed-off-by: Rudraksha Gupta Link: https://patch.msgid.link/20251225-ppp_light_accel_mag_vol-down-v6-2-8c79a4e87001@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-pinephone-pro.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index a100fb96c8a5..141ab9850290 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -520,6 +520,16 @@ touchscreen-size-x = <720>; touchscreen-size-y = <1440>; }; + + light-sensor@48 { + compatible = "sensortek,stk3311"; + reg = <0x48>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&light_int_l>; + proximity-near-level = <300>; + }; }; &i2c4 { @@ -718,6 +728,12 @@ }; }; + stk3311 { + light_int_l: light-int-l { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_input_pull_up>; + }; + }; + wifi { wifi_host_wake_l: wifi-host-wake-l { rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; From cd50298ffc5f98872ddf0ac05c51a014003a34b7 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Tue, 30 Dec 2025 17:23:34 +0400 Subject: [PATCH 366/757] arm64: dts: rockchip: enable UFS controller on FriendlyElec NanoPi M5 The NanoPi M5 board supports pluggable UFS modules using the UFSHC inside its Rockchip RK3576 SoC. Enable the respective devicetree node and add its supply regulators. Link: https://wiki.friendlyelec.com/wiki/images/9/97/NanoPi_M5_LP5_2411_SCH.pdf Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251230-nanopi-m5-ufs-v3-1-ed188ae34fdb@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-nanopi-m5.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts index cce34c541f7c..af4b7c004c38 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -110,6 +110,22 @@ regulator-name = "vcc12v_dcin"; }; + vcc1v2_ufs_vccq: regulator-vcc1v2-ufs-vccq { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc1v2_ufs_vccq"; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc1v8_ufs_vccq2: regulator-vcc1v8-ufs-vccq2 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_ufs_vccq2"; + vin-supply = <&vcc_1v8_s3>; + }; + vcc3v3_m2_keym: regulator-vcc3v3-m2-keym { compatible = "regulator-fixed"; enable-active-high; @@ -906,6 +922,14 @@ status = "okay"; }; +&ufshc { + vcc-supply = <&vcc_3v3_s3>; + vccq-supply = <&vcc1v2_ufs_vccq>; + vccq2-supply = <&vcc1v8_ufs_vccq2>; + vdd-hba-supply = <&vdda_1v2_s0>; + status = "okay"; +}; + &usbdp_phy { status = "okay"; }; From 7127b6d899c74a2ba7af09f1755a22cf9c72dba9 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 1 Jan 2026 07:43:09 +0100 Subject: [PATCH 367/757] arm64: dts: rockchip: Enable the NPU on NanoPC T6/T6-LTS Enable the NPU on FriendlyElec NanoPC T6/T6-LTS boards. The regulator vdd_npu_s0 was already in place; since the NPU power domain supply is now described, remove the regulator's always-on. Signed-off-by: Ricardo Pardini Link: https://patch.msgid.link/20260101-arm64-dts-rockchip-rk3588-npu-enablements-v2-1-013cf5d5c39d@pardini.net Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 36 ++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi index fafeabe9adf9..90e7fe254491 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi @@ -458,7 +458,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -629,6 +628,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { gpio-leds { sys_led_pin: sys-led-pin { @@ -706,6 +709,37 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; From 628aea397d81cbec3f2ff9067c5223c927f220a2 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 1 Jan 2026 07:43:10 +0100 Subject: [PATCH 368/757] arm64: dts: rockchip: Enable the NPU on FriendlyElec CM3588 Enable the NPU on FriendlyElec CM3588. The regulator vdd_npu_s0 was already in place; since the NPU power domain supply is now described, remove the regulator's always-on. Signed-off-by: Ricardo Pardini Link: https://patch.msgid.link/20260101-arm64-dts-rockchip-rk3588-npu-enablements-v2-2-013cf5d5c39d@pardini.net Signed-off-by: Heiko Stuebner --- .../rockchip/rk3588-friendlyelec-cm3588.dtsi | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi index af431fdcbea7..49cf4b85c4e9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -182,7 +182,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -264,6 +263,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { @@ -294,6 +297,36 @@ }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; From 5360ad495b7bf1e3ea95f0e47961d5447a829f8e Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 1 Jan 2026 07:43:11 +0100 Subject: [PATCH 369/757] arm64: dts: rockchip: Enable the NPU on Turing RK1 Enable the NPU on Turing RK1. The regulator vdd_npu_s0 was already in place; since the NPU power domain supply is now described, remove the regulator's always-on. Signed-off-by: Ricardo Pardini Link: https://patch.msgid.link/20260101-arm64-dts-rockchip-rk3588-npu-enablements-v2-3-013cf5d5c39d@pardini.net Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3588-turing-rk1.dtsi | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi index 6daea8961fdd..b11d24dcc180 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi @@ -171,7 +171,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -293,6 +292,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { fan { fan_int: fan-int { @@ -333,6 +336,36 @@ status = "okay"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &sdhci { bus-width = <8>; no-sdio; From f01f0e0700740dc7a2e5ed1af89d9770c1127d2e Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 6 Jan 2026 18:00:00 +0800 Subject: [PATCH 370/757] arm64: dts: rockchip: Enable PCIe for ArmSoM Sige1 Enable the RTL8125 network controller and corresponding PHY connected via PCIe on the ArmSoM Sige1. Signed-off-by: Chukun Pan Reviewed-by: Jonas Karlman Link: https://patch.msgid.link/20260106100000.225445-1-amadeus@jmu.edu.cn Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3528-armsom-sige1.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts index 6e21579365a5..c41af8fc0c8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3528-armsom-sige1.dts @@ -232,6 +232,10 @@ }; }; +&combphy { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_arm>; }; @@ -293,6 +297,14 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_perstn>; + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + &pinctrl { bluetooth { bt_reg_on_h: bt-reg-on-h { @@ -324,6 +336,12 @@ }; }; + pcie { + pcie20_perstn: pcie20-perstn { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + rtc { rtc_int_l: rtc-int-l { rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; From 77712fe6847b2471a558ec88868311a4784afdce Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:32:44 -0600 Subject: [PATCH 371/757] arm64: dts: rockchip: Add missing everest,es8388 supplies to rk3399-roc-pc-plus The regulator supplies for everest,es8388 audio codec are missing and are required. Add them based on the schematics found here: https://personalbsd.org/download/Documents/SCH/ROC-RK3399-PC-PLUS-V20-20210809.pdf With this, "regulator-always-on" should no longer be necessary for LDO5. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260105193245.3167500-1-robh@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts | 4 ++++ arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts index 8e3858cf988c..4f2831097624 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts @@ -116,6 +116,10 @@ reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; #sound-dai-cells = <0>; + AVDD-supply = <&vcca3v0_codec>; + DVDD-supply = <&vcca1v8_codec>; + HPVDD-supply = <&vcca3v0_codec>; + PVDD-supply = <&vcca1v8_codec>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index fc9279627ef6..ac62e8f5d9f5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -408,7 +408,6 @@ vcca3v0_codec: LDO_REG5 { regulator-name = "vcca3v0_codec"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; From a1823b88d35f1bf04ec4e4f86b9206f699b362d0 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 29 Dec 2025 04:58:37 +0000 Subject: [PATCH 372/757] dt-bindings: arm: rockchip: fix description for Radxa CM3I "Radxa CM3I" is the correct name[1], so fix the description. [1] https://dl.radxa.com/cm3i/docs/hw/radxa_cm3i_product_brief.pdf Signed-off-by: FUKAUMI Naoki Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251229045838.2917-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 79e99694577e..410a9715a0fc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -914,7 +914,7 @@ properties: - const: radxa,cm5 - const: rockchip,rk3588s - - description: Radxa CM3 Industrial + - description: Radxa CM3I items: - enum: - radxa,e25 From fc808f80cf298caaa403755ca808cf650844f2f5 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Mon, 29 Dec 2025 04:58:38 +0000 Subject: [PATCH 373/757] dt-bindings: arm: rockchip: fix description for Radxa CM5 "Radxa CM5" is the correct name[1], so fix the description. While at it, move the CM5 entry after the CM3I. [1] https://dl.radxa.com/cm5/radxa_cm5_product_brief.pdf Signed-off-by: FUKAUMI Naoki Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251229045838.2917-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../devicetree/bindings/arm/rockchip.yaml | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 410a9715a0fc..59a7aed538b4 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -907,13 +907,6 @@ properties: - const: radxa,cm3 - const: rockchip,rk3566 - - description: Radxa Compute Module 5 (CM5) - items: - - enum: - - radxa,cm5-io - - const: radxa,cm5 - - const: rockchip,rk3588s - - description: Radxa CM3I items: - enum: @@ -921,6 +914,13 @@ properties: - const: radxa,cm3i - const: rockchip,rk3568 + - description: Radxa CM5 + items: + - enum: + - radxa,cm5-io + - const: radxa,cm5 + - const: rockchip,rk3588s + - description: Radxa E20C items: - const: radxa,e20c From 8fd18d9b7b74bbd5ee5c562c2b94fdb7a356867e Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 12 Aug 2025 10:52:12 +0200 Subject: [PATCH 374/757] arm64: dts: rockchip: enable NPU on rk3588-tiger Enable the NPU cores and their mmus and wire up the supply-regulator. The regulator itself was already defined, but it does not need to be always on - the npu can control it. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Tested-by: Quentin Schulz Link: https://patch.msgid.link/20250812085213.1071106-1-heiko@sntech.de Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi index 365c1d958f2d..27269b7b08aa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -197,7 +197,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -340,6 +339,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -372,6 +375,36 @@ pinctrl-names = "default"; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; From 843b912c7241ed0259f6234243da05e10ce67c0f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 12 Aug 2025 10:52:13 +0200 Subject: [PATCH 375/757] arm64: dts: rockchip: enable NPU on rk3588-jaguar Enable the NPU cores and their mmus and wire up the supply-regulator. The regulator itself was already defined, but it does not need to be always on - the npu can control it. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Tested-by: Quentin Schulz Link: https://patch.msgid.link/20250812085213.1071106-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 176925d0a1a8..952affaf455c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -393,7 +393,6 @@ reg = <0x42>; fcs,suspend-voltage-selector = <1>; regulator-name = "vdd_npu_s0"; - regulator-always-on; regulator-boot-on; regulator-min-microvolt = <550000>; regulator-max-microvolt = <950000>; @@ -564,6 +563,10 @@ domain-supply = <&vdd_gpu_s0>; }; +&pd_npu { + domain-supply = <&vdd_npu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -618,6 +621,36 @@ }; }; +&rknn_core_0 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_1 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_core_2 { + npu-supply = <&vdd_npu_s0>; + sram-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknn_mmu_0 { + status = "okay"; +}; + +&rknn_mmu_1 { + status = "okay"; +}; + +&rknn_mmu_2 { + status = "okay"; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; From 309598fca339abd4e8eef0efe0d630714ca79ac9 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:00 +0400 Subject: [PATCH 376/757] arm64: dts: rockchip: Use a readable audio card name on NanoPi M5 'simple-audio-card,name' ends up in user visible places such as ALSA mixer names, so use a more human-readable name instead of realtek,rt5616-codec Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-3-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts index af4b7c004c38..9cb5acb555d8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -220,7 +220,7 @@ simple-audio-card,format = "i2s"; simple-audio-card,hp-det-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,name = "Onboard Analog RT5616"; simple-audio-card,routing = "Headphones", "HPOL", From bde555926b61740c6256a38a9cf5a4833be345cc Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:01 +0400 Subject: [PATCH 377/757] arm64: dts: rockchip: Enable HDMI sound on FriendlyElec NanoPi M5 All RK3576 boards get their HDMI sound from SAI6, which is internally connected to the HDMI codec. Enable this for FriendlyElec NanoPi M5. Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-4-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts index 9cb5acb555d8..959ea96b313f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts @@ -340,6 +340,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -864,6 +868,10 @@ status = "okay"; }; +&sai6 { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8_s0>; status = "okay"; From 87af7643234a2b4cb49a97dfe7fb455633b3185d Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:02 +0400 Subject: [PATCH 378/757] arm64: dts: rockchip: Enable HDMI sound on Luckfox Core3576 All RK3576 boards get their HDMI sound from SAI6, which is internally connected to the HDMI codec. Enable this for Luckfox Core3576 Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-5-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi index 9187012d6fa4..749f0a54b478 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-luckfox-core3576.dtsi @@ -246,6 +246,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -691,6 +695,10 @@ status = "okay"; }; +&sai6 { + status = "okay"; +}; + &saradc { vref-supply = <&vcca_1v8_s0>; status = "okay"; From f5c9549964adbac931e163693bd17db872976679 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:03 +0400 Subject: [PATCH 379/757] arm64: dts: rockchip: Enable HDMI sound on RK3576 EVB1 All RK3576 boards get their HDMI sound from SAI6, which is internally connected to the HDMI codec. Enable this for Rockchip RK3576 EVB1 Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-6-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index db8fef7a4f1b..deab20ff4d97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -315,6 +315,10 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + &hdptxphy { status = "okay"; }; @@ -835,6 +839,10 @@ }; }; +&sai6 { + status = "okay"; +}; + &sdhci { bus-width = <8>; full-pwr-cycle-in-suspend; From d8872b9dd9208c493f1f3811d42997fb968de064 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Mon, 29 Dec 2025 14:12:04 +0400 Subject: [PATCH 380/757] arm64: dts: rockchip: Enable analog sound on RK3576 EVB1 Rockchip RK3576 EVB1 board uses the typical configuration with an ES8388 analog codec driven from built-in SAI I2S. Add device tree nodes for it. Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20251229-rk3576-sound-v1-7-2f59ef0d19b1@gmail.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-evb1-v10.dts | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index deab20ff4d97..0789733c2073 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -246,6 +246,63 @@ regulator-max-microvolt = <1800000>; vin-supply = <&vcc_1v8_s3>; }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + simple-audio-card,name = "On-board Analog ES8388"; + simple-audio-card,aux-devs = <&hp_power>, <&spk_power>; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&masterdai>; + simple-audio-card,hp-det-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,routing = + "Headphone Power INL", "LOUT1", + "Headphone Power INR", "ROUT1", + "Speaker Power INL", "LOUT2", + "Speaker Power INR", "ROUT2", + "Headphones", "Headphone Power OUTL", + "Headphones", "Headphone Power OUTR", + "Speaker", "Speaker Power OUTL", + "Speaker", "Speaker Power OUTR", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + simple-audio-card,widgets = + "Microphone", "Main Mic", + "Microphone", "Headset Mic", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&es8388>; + system-clock-frequency = <12288000>; + }; + }; + + hp_power: headphone-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_ctl>; + sound-name-prefix = "Headphone Power"; + }; + + spk_power: speaker-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spk_ctl>; + sound-name-prefix = "Speaker Power"; + VCC-supply = <&vcc5v0_device>; + }; }; &cpu_l0 { @@ -712,6 +769,25 @@ }; }; +&i2c3 { + status = "okay"; + + es8388: audio-codec@10 { + compatible = "everest,es8388", "everest,es8328"; + reg = <0x10>; + AVDD-supply = <&vcca_3v3_s0>; + DVDD-supply = <&vcc_1v8_s0>; + HPVDD-supply = <&vcca_3v3_s0>; + PVDD-supply = <&vcc_1v8_s0>; + assigned-clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + assigned-clock-rates = <12288000>; + clocks = <&cru CLK_SAI1_MCLKOUT_TO_IO>; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_mclk>; + #sound-dai-cells = <0>; + }; +}; + &mdio0 { rgmii_phy0: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; @@ -778,6 +854,20 @@ }; &pinctrl { + audio { + hp_det: hp-det { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + hp_ctl: hp-ctl { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + spk_ctl: spk-ctl { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + bluetooth { bt_reg_on: bt-reg-on { rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; @@ -839,6 +929,15 @@ }; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; + status = "okay"; +}; + &sai6 { status = "okay"; }; From eaada4f56ab366f4c198291aa9d04b8a3348e291 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:25:24 +0100 Subject: [PATCH 381/757] arm64: dts: airoha: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/airoha/en7581-evb.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts index dae9968a4ff6..886e2e4b5f64 100644 --- a/arch/arm64/boot/dts/airoha/en7581-evb.dts +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts @@ -47,17 +47,17 @@ reg = <0x00600000 0x03200000>; }; - tclinux_slave@3800000 { + tclinux-slave@3800000 { label = "tclinux_alt"; reg = <0x03800000 0x03200000>; }; - rootfs_data@6a00000 { + rootfs-data@6a00000 { label = "rootfs_data"; reg = <0x06a00000 0x01400000>; }; - reserved_bmt@7e00000 { + reserved-bmt@7e00000 { label = "reserved_bmt"; reg = <0x07e00000 0x00200000>; read-only; From 0516c548883bbe58a48d604e81e33b390986cdb6 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 19 Nov 2025 18:51:22 +0100 Subject: [PATCH 382/757] arm64: dts: mediatek: mt7986: add dtbs with applied overlays for bpi-r3 Build devicetree binaries for testing overlays and providing users full dtb without using overlays. Suggested-by: Rob Herring Signed-off-by: Frank Wunderlich Acked-by: Rob Herring (Arm) Acked-by: AngeloGioacchino Del Regno Fixes: a58c36806741 ("arm64: dts: mediatek: mt7988a-bpi-r4pro: Add mmc overlays") Fixes: dec929e61a42 ("arm64: dts: mediatek: mt7988a-bpi-r4-pro: Add PCIe overlays") Fixes: 714a80ced07a ("arm64: dts: mediatek: mt7988a-bpi-r4: Add dt overlays for sd + emmc") Fixes: 312189ebb802 ("arm64: dts: mt7986: add overlay for SATA power socket on BPI-R3") Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c5fd6191a925..77d76730d61b 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -19,6 +19,27 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo +mt7986a-bananapi-bpi-r3-emmc-nand-dtbs := \ + mt7986a-bananapi-bpi-r3.dtb \ + mt7986a-bananapi-bpi-r3-emmc.dtbo \ + mt7986a-bananapi-bpi-r3-nand.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc-nand.dtb +mt7986a-bananapi-bpi-r3-emmc-nor-dtbs := \ + mt7986a-bananapi-bpi-r3.dtb \ + mt7986a-bananapi-bpi-r3-emmc.dtbo \ + mt7986a-bananapi-bpi-r3-nor.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc-nor.dtb +mt7986a-bananapi-bpi-r3-sd-nand-dtbs := \ + mt7986a-bananapi-bpi-r3.dtb \ + mt7986a-bananapi-bpi-r3-sd.dtbo \ + mt7986a-bananapi-bpi-r3-nand.dtbo \ + mt7986a-bananapi-bpi-r3-sata.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd-nand.dtb +mt7986a-bananapi-bpi-r3-sd-nor-dtbs := \ + mt7986a-bananapi-bpi-r3.dtb \ + mt7986a-bananapi-bpi-r3-sd.dtbo \ + mt7986a-bananapi-bpi-r3-nor.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd-nor.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4.dtb From d977b61d38030f50bae9f634049110af0a364d0d Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 19 Nov 2025 18:51:23 +0100 Subject: [PATCH 383/757] arm64: dts: mediatek: mt7988: add dtbs with applied overlays for bpi-r4 (pro) Build devicetree binaries for testing overlays and providing users full dtb without using overlays for Bananapi R4 (pro) variants. Signed-off-by: Frank Wunderlich Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 77d76730d61b..cac8f4c6d76f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -52,6 +52,38 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-cn18.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-sd.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtbo +mt7988a-bananapi-bpi-r4-emmc-dtbs := \ + mt7988a-bananapi-bpi-r4.dtb \ + mt7988a-bananapi-bpi-r4-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-emmc.dtb +mt7988a-bananapi-bpi-r4-sd-dtbs := \ + mt7988a-bananapi-bpi-r4.dtb \ + mt7988a-bananapi-bpi-r4-sd.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-sd.dtb +mt7988a-bananapi-bpi-r4-2g5-emmc-dtbs := \ + mt7988a-bananapi-bpi-r4-2g5.dtb \ + mt7988a-bananapi-bpi-r4-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-emmc.dtb +mt7988a-bananapi-bpi-r4-2g5-sd-dtbs := \ + mt7988a-bananapi-bpi-r4-2g5.dtb \ + mt7988a-bananapi-bpi-r4-sd.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-2g5-sd.dtb +mt7988a-bananapi-bpi-r4-pro-8x-emmc-dtbs := \ + mt7988a-bananapi-bpi-r4-pro-8x.dtb \ + mt7988a-bananapi-bpi-r4-pro-emmc.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-emmc.dtb +mt7988a-bananapi-bpi-r4-pro-8x-sd-dtbs := \ + mt7988a-bananapi-bpi-r4-pro-8x.dtb \ + mt7988a-bananapi-bpi-r4-pro-sd.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb +mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15-dtbs := \ + mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn15.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn15.dtb +mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18-dtbs := \ + mt7988a-bananapi-bpi-r4-pro-8x-sd.dtb \ + mt7988a-bananapi-bpi-r4-pro-cn18.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7988a-bananapi-bpi-r4-pro-8x-sd-cn18.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb From 34e7595912cfffdbca8c34d7c321d9937e0201ee Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 5 Dec 2025 22:59:38 +0100 Subject: [PATCH 384/757] arm64: dts: mediatek: Apply mt8395-radxa DT overlay at build time It's a requirement that DT overlays be applied at build time in order to validate them as overlays are not validated on their own. Add missing target for mt8395-radxa hd panel overlay. Fixes: 4c8ff61199a7 ("arm64: dts: mediatek: mt8395-radxa-nio-12l: Add Radxa 8 HD panel") Signed-off-by: Rob Herring (Arm) Signed-off-by: Frank Wunderlich Acked-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index cac8f4c6d76f..3f76d9ce9879 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -166,6 +166,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo +mt8395-radxa-nio-12l-8-hd-panel-dtbs := mt8395-radxa-nio-12l.dtb mt8395-radxa-nio-12l-8-hd-panel.dtbo +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb # Device tree overlays support From 5ea75722eaec226c60472dc578a302aae1d1fa3e Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 8 Nov 2025 22:15:03 +0100 Subject: [PATCH 385/757] ARM: dts: meson: drop iio-hwmon in favour of generic-adc-thermal Commit 85b21fdec906e ("thermal/drivers/generic-adc: Register thermal zones as hwmon sensors") made "generic-adc-thermal" also register hwmon attributes. That means we now have the temperature sensor shown twice: - once from iio-hwmon - and another time from generic-adc-thermal We need the latter for SoC temperature control, so simply drop the former so userspace doesn't see duplicate sensors. Also generic-adc-thermal provides a better name to userspace ("soc_thermal-virtual-0") than iio_hwmon. Signed-off-by: Martin Blumenstingl Link: https://patch.msgid.link/20251108211503.1578711-1-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong --- arch/arm/boot/dts/amlogic/meson.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi index 28ec2c821cdc..6792377b2841 100644 --- a/arch/arm/boot/dts/amlogic/meson.dtsi +++ b/arch/arm/boot/dts/amlogic/meson.dtsi @@ -12,11 +12,6 @@ #size-cells = <1>; interrupt-parent = <&gic>; - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&saradc 8>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; From 125c3ceadfe02cd4917c5e0bb6707b37870449f2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:25:11 +0100 Subject: [PATCH 386/757] arm64: dts: amlogic: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20251223152510.155463-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index 13b7ac03f9b2..c9d9f3ddf73c 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -780,7 +780,7 @@ #address-cells = <1>; #size-cells = <0>; - internal_ephy: ethernet_phy@8 { + internal_ephy: ethernet-phy@8 { compatible = "ethernet-phy-id0180.3301", "ethernet-phy-ieee802.3-c22"; interrupts = ; From 7bcbedd64ecf5624583140faebfdb0e2e2f6b43e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:25:12 +0100 Subject: [PATCH 387/757] arm64: dts: amlogic: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20251223152510.155463-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 4 ++-- arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index c9d9f3ddf73c..11e5323f95b7 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -108,7 +108,7 @@ firmware { scmi: scmi { compatible = "arm,scmi-smc"; - arm,smc-id = <0x820000C1>; + arm,smc-id = <0x820000c1>; shmem = <&scmi_shmem>; #address-cells = <1>; #size-cells = <0>; @@ -989,7 +989,7 @@ nand: nand-controller@8d000 { compatible = "amlogic,meson-axg-nfc"; reg = <0x0 0x8d000 0x0 0x200>, - <0x0 0x8C000 0x0 0x4>; + <0x0 0x8c000 0x0 0x4>; reg-names = "nfc", "emmc"; interrupts = ; clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>, diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts index c05edebb90b5..cab2ee9ea0d3 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts @@ -20,7 +20,7 @@ memory@0 { device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0xE0000000 + reg = <0x00000000 0x00000000 0x00000000 0xe0000000 0x00000001 0x00000000 0x00000000 0x20000000>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts index f5b3424c0f61..dddbbe6dca7c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-mecool-kiii-pro.dts @@ -17,7 +17,7 @@ memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x0 0xC0000000>; + reg = <0x0 0x0 0x0 0xc0000000>; }; adc-keys { From 8b7f2aa05c02c13aa017a70401b5f8a3ce0c0f57 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 27 Jun 2025 21:37:55 +0200 Subject: [PATCH 388/757] arm64: dts: qcom: qcs615: Drop IPA interconnects In the same spirit as e.g. Commit 6314184be391 ("arm64: dts: qcom: sc8180x: Drop ipa-virt interconnect") drop the resources that should be taken care of through the clk-rpmh driver. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250627-topic-qcs615_icc_ipa-v1-1-dc47596cde69@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 208344a1a832..96bacae93c70 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -480,12 +480,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - ipa_virt: interconnect-1 { - compatible = "qcom,qcs615-ipa-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - mc_virt: interconnect-2 { compatible = "qcom,qcs615-mc-virt"; #interconnect-cells = <2>; From e8061ea925314c57248fafc1d0c30b8dc39e23b6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:46:34 -0600 Subject: [PATCH 389/757] arm64: dts: marvell: Add missing "#phy-cells" to "usb-nop-xceiv" The "usb-nop-xceiv" binding requires "#phy-cells" property with a value of 0 though it is not really used. Add it where missing from Marvell platforms. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 1 + arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 1 + arch/arm64/boot/dts/marvell/armada-8040-db.dts | 2 ++ arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 2 ++ arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 ++ arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 1 + arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 2 ++ 7 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index bd4e61d5448e..06d4a3a93f84 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -41,6 +41,7 @@ usb3_phy: usb3-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&exp_usb3_vbus>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 97a180c8dcd9..e82284888b9a 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -37,6 +37,7 @@ usb3_phy: usb3-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <®_usb3_vbus>; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index 21ecb9c12505..c7102f74d4d5 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -51,6 +51,7 @@ cp0_usb3_0_phy: cp0-usb3-0-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_0_vbus>; }; @@ -65,6 +66,7 @@ cp1_usb3_0_phy: cp1-usb3-0-phy { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp1_reg_usb3_0_vbus>; }; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 5e7d6de3cdde..5689a8bdfd03 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -47,10 +47,12 @@ cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus1>; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 3cc320f569ad..7156739aa31a 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -50,6 +50,7 @@ cp0_usb3_0_phy0: usb-phy-1 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus0>; }; @@ -64,6 +65,7 @@ cp0_usb3_0_phy1: usb-phy-2 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp0_reg_usb3_vbus1>; }; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index 626042fce7e2..26dc91c88677 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -31,6 +31,7 @@ cp1_usb3_0_phy0: usb-phy-3 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp1_reg_usb3_vbus0>; }; diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi index f91fc69905b8..f82d45e62753 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi @@ -28,6 +28,7 @@ cp2_usb3_0_phy0: usb-phy-4 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp2_reg_usb3_vbus0>; }; @@ -42,6 +43,7 @@ cp2_usb3_0_phy1: usb-phy-5 { compatible = "usb-nop-xceiv"; + #phy-cells = <0>; vcc-supply = <&cp2_reg_usb3_vbus1>; }; From 5336444472700244147b04601235ca8b7fd1ec16 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:46:41 -0600 Subject: [PATCH 390/757] arm64: dts: marvell: Fix stray and typo "pinctrl-names" properties There's several cases of "pinctrl-names" used without any "pinctrl-0" properties. Drop them. Fix the typo "pintrl-names" as well. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 1 - arch/arm64/boot/dts/marvell/cn9130-cf-base.dts | 2 +- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 1 - arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 -- arch/arm64/boot/dts/marvell/cn9132-db.dtsi | 1 - 5 files changed, 1 insertion(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index e82284888b9a..0ab33aa928e7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -42,7 +42,6 @@ }; gpio-leds { - pinctrl-names = "default"; compatible = "gpio-leds"; /* No assigned functions to the LEDs by default */ led1 { diff --git a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts index 788a5c302b17..212865f6cf6a 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts +++ b/arch/arm64/boot/dts/marvell/cn9130-cf-base.dts @@ -137,7 +137,7 @@ &cp0_pinctrl { pinctrl-0 = <&sim_select_pins>; - pintrl-names = "default"; + pinctrl-names = "default"; rear_button_pins: cp0-rear-button-pins { marvell,pins = "mpp31"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index 5689a8bdfd03..c9050e707a60 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -93,7 +93,6 @@ /* on-board eMMC U6 */ &ap_sdhci0 { - pinctrl-names = "default"; bus-width = <8>; status = "okay"; mmc-ddr-1_8v; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index 7156739aa31a..8e413286e019 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -111,7 +111,6 @@ /* on-board eMMC - U9 */ &ap_sdhci0 { - pinctrl-names = "default"; bus-width = <8>; vqmmc-supply = <&ap0_reg_sd_vccq>; status = "okay"; @@ -166,7 +165,6 @@ /* U36 */ expander0: pca953x@21 { compatible = "nxp,pca9555"; - pinctrl-names = "default"; gpio-controller; #gpio-cells = <2>; reg = <0x21>; diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi index f82d45e62753..98eee9e4e10b 100644 --- a/arch/arm64/boot/dts/marvell/cn9132-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9132-db.dtsi @@ -142,7 +142,6 @@ /* U12 */ cp2_module_expander1: pca9555@21 { compatible = "nxp,pca9555"; - pinctrl-names = "default"; gpio-controller; #gpio-cells = <2>; reg = <0x21>; From e509bd563114c3730bf4be48436a4741c0ab4dc9 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:46:46 -0600 Subject: [PATCH 391/757] arm64: dts: marvell: cn9131-cf-solidwan: Add missing GPIO properties on "nxp,pca9536" The PCA9536 is always a GPIO provider, so add the missing properties. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts index 338853d3b179..b6aeba7d0a61 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts +++ b/arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts @@ -202,6 +202,8 @@ expander0: gpio@41 { compatible = "nxp,pca9536"; reg = <0x41>; + gpio-controller; + #gpio-cells = <2>; usb-a-vbus0-ilimit-hog { gpio-hog; From dd1aadd29de3645c08a160c3b3cfc0d7a5c9bf35 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:46:52 -0600 Subject: [PATCH 392/757] arm64: dts: marvell: change regulator-gpio to regulator-fixed A "regulator-gpio" must have a GPIO control, hence the name. There's no GPIO on a couple of Marvell platforms at least as far as the DT is defined, so change the regulator type from GPIO to fixed. Signed-off-by: Rob Herring (Arm) Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts | 9 ++------- arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi | 3 ++- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index 9f4bafeddd82..a881a3326dba 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -26,16 +26,11 @@ }; vcc_sd_reg1: regulator { - compatible = "regulator-gpio"; + compatible = "regulator-fixed"; regulator-name = "vcc_sd1"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; - - gpios-states = <0>; - states = <1800000 0x1 - 3300000 0x0>; - enable-active-high; }; keys { diff --git a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi index 6f3914bcfd01..71c225221617 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db-comexpress.dtsi @@ -15,8 +15,9 @@ }; &ap0_reg_sd_vccq { + compatible = "regulator-fixed"; regulator-max-microvolt = <1800000>; - states = <1800000 0x1 1800000 0x0>; + /delete-property/ states; /delete-property/ gpios; }; From 1b3cadbd185a6e8681c3b3b6578d7cf3ea4ca47d Mon Sep 17 00:00:00 2001 From: Peter Shen Date: Fri, 19 Dec 2025 17:16:31 +0800 Subject: [PATCH 393/757] dt-bindings: arm: aspeed: Add compatible for Facebook Anacapa BMC This patch adds the compatible string for the Facebook Anacapa BMC which uses an Aspeed AST2600 SoC. This is required before adding the board's device tree source file. Signed-off-by: Peter Shen Acked-by: Krzysztof Kozlowski [arj: Insert provided Acked-by tag from Krzysztof, drop misspelled one] Link: https://lore.kernel.org/linux-aspeed/259e917f-0570-40d6-983f-bfe9d77444a7@kernel.org/ Link: https://patch.msgid.link/20251219091632.1598603-2-sjg168@gmail.com Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 8a190819e066..ba59bfd699da 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -80,6 +80,7 @@ properties: - aspeed,ast2600-evb - aspeed,ast2600-evb-a1 - asus,x4tf-bmc + - facebook,anacapa-bmc - facebook,bletchley-bmc - facebook,catalina-bmc - facebook,clemente-bmc From bc83b7353d2bfefba73193335bacc3542d8a7ae2 Mon Sep 17 00:00:00 2001 From: Peter Shen Date: Fri, 19 Dec 2025 17:16:32 +0800 Subject: [PATCH 394/757] ARM: dts: aspeed: Add Facebook Anacapa platform The Meta Anacapa BMC is the DC-SCM (Data Center Secure Control Module) controller for the Meta OCP Open Rack Wide (ORW) compute tray. This platform is a key component of the AMD Helios AI rack reference design system, designed for next-generation AI workloads. The BMC utilizes the Aspeed AST2600 SoC to manage the compute tray, which contains up to 4 AMD Instinct MI450 Series GPUs (connected via a Broadcom OCP NIC) and host CPUs. Its primary role is to provide essential system control, power sequencing, and telemetry reporting for the compute complex via the OpenBMC software stack. For more detail on the AMD Helios reference design: https://www.amd.com/en/blogs/2025/amd-helios-ai-rack-built-on-metas-2025-ocp-design.html Signed-off-by: Peter Shen Link: https://patch.msgid.link/20251219091632.1598603-3-sjg168@gmail.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../aspeed/aspeed-bmc-facebook-anacapa.dts | 1045 +++++++++++++++++ 2 files changed, 1046 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index ed25fec25fc4..b3e2f76027f5 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-asus-x4tf.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-delta-ahe50dc.dtb \ + aspeed-bmc-facebook-anacapa.dtb \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-catalina.dtb \ aspeed-bmc-facebook-clemente.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts new file mode 100644 index 000000000000..221af858cb6b --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -0,0 +1,1045 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Facebook Anacapa BMC"; + compatible = "facebook,anacapa-bmc", "aspeed,ast2600"; + + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + i2c16 = &i2c0mux0ch0; + i2c17 = &i2c0mux0ch1; + i2c18 = &i2c0mux0ch2; + i2c19 = &i2c0mux0ch3; + i2c20 = &i2c1mux0ch0; + i2c21 = &i2c1mux0ch1; + i2c22 = &i2c1mux0ch2; + i2c23 = &i2c1mux0ch3; + i2c24 = &i2c4mux0ch0; + i2c25 = &i2c4mux0ch1; + i2c26 = &i2c4mux0ch2; + i2c27 = &i2c4mux0ch3; + i2c28 = &i2c4mux0ch4; + i2c29 = &i2c4mux0ch5; + i2c30 = &i2c4mux0ch6; + i2c31 = &i2c4mux0ch7; + i2c32 = &i2c8mux0ch0; + i2c33 = &i2c8mux0ch1; + i2c34 = &i2c8mux0ch2; + i2c35 = &i2c8mux0ch3; + i2c36 = &i2c10mux0ch0; + i2c37 = &i2c10mux0ch1; + i2c38 = &i2c10mux0ch2; + i2c39 = &i2c10mux0ch3; + i2c40 = &i2c10mux0ch4; + i2c41 = &i2c10mux0ch5; + i2c42 = &i2c10mux0ch6; + i2c43 = &i2c10mux0ch7; + i2c44 = &i2c11mux0ch0; + i2c45 = &i2c11mux0ch1; + i2c46 = &i2c11mux0ch2; + i2c47 = &i2c11mux0ch3; + i2c48 = &i2c11mux0ch4; + i2c49 = &i2c11mux0ch5; + i2c50 = &i2c11mux0ch6; + i2c51 = &i2c11mux0ch7; + i2c52 = &i2c13mux0ch0; + i2c53 = &i2c13mux0ch1; + i2c54 = &i2c13mux0ch2; + i2c55 = &i2c13mux0ch3; + i2c56 = &i2c13mux0ch4; + i2c57 = &i2c13mux0ch5; + i2c58 = &i2c13mux0ch6; + i2c59 = &i2c13mux0ch7; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + label = "bmc_heartbeat_amber"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "fp_id_amber"; + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: video { + size = <0x02c00000>; + alignment = <0x00100000>; + compatible = "shared-dma-pool"; + reusable; + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + p3v3_bmc_aux: regulator-p3v3-bmc-aux { + compatible = "regulator-fixed"; + regulator-name = "p3v3_bmc_aux"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + spi_gpio: spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + spi-max-frequency = <33000000>; + reg = <0>; + }; + }; +}; + +&adc0 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + status = "okay"; +}; + +&adc1 { + aspeed,int-vref-microvolt = <2500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc10_default>; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&gpio0 { + gpio-line-names = + + /*A0-A7*/ + "","","","","","","","", + + /*B0-B7*/ + "BATTERY_DETECT", "", "", "BMC_READY", + "", "FM_ID_LED", "", "", + + /*C0-C7*/ + "","","","","","","","", + + /*D0-D7*/ + "","","","","","","","", + + /*E0-E7*/ + "","","","","","","","", + + /*F0-F7*/ + "","","","","","","","", + + /*G0-G7*/ + "FM_MUX1_SEL", "", "", "", + "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", + + /*H0-H7*/ + "","","","","","","","", + + /*I0-I7*/ + "", "", "", "", + "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", + + /*J0-J7*/ + "","","","","","","","", + + /*K0-K7*/ + "","","","","","","","", + + /*L0-L7*/ + "","","","","","","","", + + /*M0-M7*/ + "", "BMC_FRU_WP", "", "", + "", "", "", "", + + /*N0-N7*/ + "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", + "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", + + /*O0-O7*/ + "","","","","","","","", + + /*P0-P7*/ + "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", + "PWR_LED", "", "", "BMC_HEARTBEAT_N", + + /*Q0-Q7*/ + "","","","","","","","", + + /*R0-R7*/ + "","","","","","","","", + + /*S0-S7*/ + "", "", "SYS_BMC_PWRBTN_N", "", + "", "", "", "RUN_POWER_FAULT", + + /*T0-T7*/ + "","","","","","","","", + + /*U0-U7*/ + "","","","","","","","", + + /*V0-V7*/ + "","","","","","","","", + + /*W0-W7*/ + "","","","","","","","", + + /*X0-X7*/ + "","","","","","","","", + + /*Y0-Y7*/ + "","","","","","","","", + + /*Z0-Z7*/ + "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", + "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ + "","","","","","","","", + + /*18B0-18B7*/ + "","","","", + "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2", "", + + /*18C0-18C7*/ + "","","","","","","","", + + /*18D0-18D7*/ + "","","","","","","","", + + /*18E0-18E3*/ + "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; +}; + +// L Bridge Board +&i2c0 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c0mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c0mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c0mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c0mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// R Bridge Board +&i2c1 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c1mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c1mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// MB - E1.S +&i2c4 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c4mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c4mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// AMC +&i2c5 { + status = "okay"; +}; + +// MB +&i2c6 { + status = "okay"; + + // HPM FRU + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +// SCM +&i2c7 { + status = "okay"; + + +}; + +// MB - PDB +&i2c8 { + status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <1>; + }; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "", + "", "", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", + "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", + "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", + "", "RPDB_FAN1_PRSNT_N_R", + "", "RPDB_FAN2_PRSNT_N_R", + "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", + "", ""; + }; + + // R-PDB FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N","", + "","", + "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + }; + + gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", + "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", + "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", + "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", + "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", + "","", + "","", + "",""; + }; + + // L-PDB FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c8mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// SCM +&i2c9 { + status = "okay"; + + // SCM FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + // BSM FRU + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +// R Bridge Board +&i2c10 { + status = "okay"; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c10mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","", + "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", + "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", + "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", + "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", + "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", + "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", + "",""; + }; + + // R Bridge Board FRU + eeprom@52 { + compatible = "atmel,24c256"; + reg = <0x52>; + }; + }; + i2c10mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c10mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// L Bridge Board +&i2c11 { + status = "okay"; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","", + "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", + "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", + "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", + "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", + "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", + "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", + "",""; + }; + + // L Bridge Board FRU + eeprom@52 { + compatible = "atmel,24c256"; + reg = <0x52>; + }; + }; + i2c11mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c11mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// Debug Card +&i2c12 { + status = "okay"; +}; + +// MB +&i2c13 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c13mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <1>; + }; + }; + i2c13mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + // HPM BRD ID FRU + eeprom@51 { + compatible = "atmel,24c256"; + reg = <0x51>; + }; + }; + i2c13mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + i2c13mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// SCM +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8>; + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ncsi3_default>; + use-ncsi; +}; + +&sgpiom0 { + ngpios = <128>; + bus-frequency = <2000000>; + gpio-line-names = + /*in - out - in - out */ + /* A0-A7 line 0-15 */ + "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", + "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", + "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", + "", "", "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "", + "Channel5_leakage_EAM1", "", + "Channel6_leakage_CPU_DIMM", "", + "Channel7_leakage_EAM2", "", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "", "", "", + "", "", "", "", + "LEAK_DETECT_RMC_N", "", "", "", + "", "", "", "", + + /* D0-D7 line 48-63 */ + "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", + "AMC_BRD_PRSNT_CPLD_L", "", "", "", + "", "", "", "", + + /* E0-E7 line 64-79 */ + "AMC_PDB_EAMHSC0_CPLD_EN_R", "", + "AMC_PDB_EAMHSC1_CPLD_EN_R", "", + "AMC_PDB_EAMHSC2_CPLD_EN_R", "", + "AMC_PDB_EAMHSC3_CPLD_EN_R", "", + "", "", "", "", + "", "", "", "", + + /* F0-F7 line 80-95 */ + "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", + "PWRGD_PVDDCR_CPU0_P0", "", + "", "", "", "", + "", "", "", "", + + /* G0-G7 line 96-111 */ + "PWRGD_PVDDCR_SOC_P0", "", + "PWRGD_PVDDIO_P0", "", + "PWRGD_PVDDIO_MEM_S3_P0", "", + "PWRGD_CHMP_CPU0_FPGA", "", + "PWRGD_CHIL_CPU0_FPGA", "", + "PWRGD_CHEH_CPU0_FPGA", "", + "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", + "", "", + + /* H0-H7 line 112-127 */ + "PWRGD_P3V3", "", + "P12V_DDR_IP_PWRGD_R", "", + "P12V_DDR_AH_PWRGD_R", "", + "PWRGD_P12V_VRM1_CPLD_PG_R", "", + "PWRGD_P12V_VRM0_CPLD_PG_R", "", + "PWRGD_PDB_HSC4_CPLD_PG_R", "", + "PWRGD_PVDD18_S5_P0_PG", "", + "PWRGD_PVDD33_S5_P0_PG", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "EAM0_CPU_MOD_PWR_GD_R", "", + "EAM1_CPU_MOD_PWR_GD_R", "", + "EAM2_CPU_MOD_PWR_GD_R", "", + "EAM3_CPU_MOD_PWR_GD_R", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BIRDGE_R", "", + "PRSNT_R_BIRDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "", "", "", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "CPU0_SP7R1", "", "CPU0_SP7R2", "", + "CPU0_SP7R3", "", "CPU0_SP7R4", "", + "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", + "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "", "", "", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "HPM_AMC_THERMTRIP_R_L", "Port80_b3", + "FM_CPU0_THERMTRIP_N", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "", + "FM_PWRGD_CPU0_PWROK", "", + "wS5_PWR_Ready", "", + "wS0_ON_N", "PWRGD_P1V0_AUX"; + status = "okay"; +}; + +// BIOS Flash +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default>; + status = "okay"; + reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + label = "pnor"; + spi-max-frequency = <12000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + status = "okay"; + }; +}; + +// HOST BIOS Debug +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +// BMC Debug Console +&uart5 { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&vhub { + status = "okay"; + pinctrl-names = "default"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&wdt1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; + status = "okay"; +}; From 7c2516fc94b80ca38bb32dc57d1ab67224cacc90 Mon Sep 17 00:00:00 2001 From: Cosmo Chou Date: Fri, 19 Dec 2025 14:29:48 +0800 Subject: [PATCH 395/757] ARM: dts: aspeed: bletchley: Remove try-power-role from connectors Remove the "try-power-role = sink" property from all USB-C connectors. The try mechanism is unnecessary and wastes time during connection. Since power-role = "dual" is already configured, standard USB PD negotiation is sufficient and more efficient. Signed-off-by: Cosmo Chou Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts index 7c27bf6bb51d..d1a04b63df9e 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-bletchley.dts @@ -414,7 +414,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = ; sink-pdos = ; @@ -501,7 +500,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = ; sink-pdos = ; @@ -588,7 +586,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = ; sink-pdos = ; @@ -675,7 +672,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = ; sink-pdos = ; @@ -762,7 +758,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = ; sink-pdos = ; @@ -849,7 +844,6 @@ label = "USB-C"; pd-revision = /bits/ 8 <0x2 0x0 0x1 0x20>; power-role = "dual"; - try-power-role = "sink"; data-role = "dual"; source-pdos = ; sink-pdos = ; From c4f6b5d254ef060ba92f060e2354fc03cc0b2ba6 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Thu, 18 Dec 2025 09:18:13 -0700 Subject: [PATCH 396/757] dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board Document ASRock Rack ALTRAD8 (ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q) compatibles. Signed-off-by: Rebecca Cran Acked-by: Conor Dooley Reviewed-by: Tan Siewert Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20251218161816.38155-2-rebecca@bsdio.com [arj: Drop erroneous Tested-by tag from Tan] Signed-off-by: Andrew Jeffery --- Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index ba59bfd699da..f9925a14680e 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -34,6 +34,7 @@ properties: - amd,ethanolx-bmc - ampere,mtjade-bmc - aspeed,ast2500-evb + - asrock,altrad8-bmc - asrock,e3c246d4i-bmc - asrock,e3c256d4i-bmc - asrock,romed8hm3-bmc From c6d3513c90bd1382d11f82b65c6baac9285b1bf0 Mon Sep 17 00:00:00 2001 From: Rebecca Cran Date: Thu, 18 Dec 2025 09:18:14 -0700 Subject: [PATCH 397/757] ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC The ALTRAD8 BMC is an Aspeed AST2500-based BMC for the ASRock Rack ALTRAD8UD-1L2T and ALTRAD8UD2-1L2Q boards. Signed-off-by: Rebecca Cran Tested-by: Tan Siewert Reviewed-by: Tan Siewert Link: https://patch.msgid.link/20251218161816.38155-3-rebecca@bsdio.com Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-asrock-altrad8.dts | 637 ++++++++++++++++++ 2 files changed, 638 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index b3e2f76027f5..20e5b64280a5 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-ampere-mtjefferson.dtb \ aspeed-bmc-ampere-mtmitchell.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ + aspeed-bmc-asrock-altrad8.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ aspeed-bmc-asrock-e3c256d4i.dtb \ aspeed-bmc-asrock-romed8hm3.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts new file mode 100644 index 000000000000..d4028312bdf2 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-altrad8.dts @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include +#include + +/ { + model = "ASRock ALTRAD8 BMC"; + compatible = "asrock,altrad8-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + i2c50 = &nvme1; + i2c51 = &pcie4; + i2c52 = &pcie5; + i2c53 = &pcie6; + i2c54 = &pcie7; + i2c55 = &nvme3; + i2c56 = &nvme2; + i2c57 = &nvme0; + i2c58 = &nvme4; + i2c59 = &nvme5; + i2c60 = &nvme6; + i2c61 = &nvme7; + i2c62 = &nvme8; + i2c63 = &nvme9; + i2c64 = &nvme10; + i2c65 = &nvme11; + }; + + chosen { + stdout-path = "uart5:115200n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4> ,<&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; + + leds { + compatible = "gpio-leds"; + + led-system-fault { + gpios = <&gpio ASPEED_GPIO(G,3) GPIO_ACTIVE_LOW>; + label = "platform:red:fault"; + color = ; + function = LED_FUNCTION_FAULT; + }; + + led-heartbeat { + gpios = <&gpio ASPEED_GPIO(G,0) GPIO_ACTIVE_LOW>; + label = "platform:green:heartbeat"; + color = ; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "timer"; + }; + + led-fan1-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 0 GPIO_ACTIVE_LOW>; + label = "fan1:red:fault"; + color = ; + function = LED_FUNCTION_FAULT; + }; + + led-fan2-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 1 GPIO_ACTIVE_LOW>; + label = "fan2:red:fault"; + color = ; + function = LED_FUNCTION_FAULT; + }; + + led-fan3-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 2 GPIO_ACTIVE_LOW>; + label = "fan3:red:fault"; + color = ; + function = LED_FUNCTION_FAULT; + }; + + led-fan4-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 3 GPIO_ACTIVE_LOW>; + label = "fan4:red:fault"; + color = ; + function = LED_FUNCTION_FAULT; + }; + + led-fan5-fault { + retain-state-shutdown; + default-state = "off"; + gpios = <&io_expander0 4 GPIO_ACTIVE_LOW>; + label = "fan5:red:fault"; + color = ; + function = LED_FUNCTION_FAULT; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gfx_memory: framebuffer { + compatible = "shared-dma-pool"; + size = <0x01000000>; + alignment = <0x01000000>; + reusable; + }; + + vga_memory: framebuffer@9f000000 { + no-map; + reg = <0x9f000000 0x01000000>; /* 16M */ + }; + + video_engine_memory: jpegbuffer { + compatible = "shared-dma-pool"; + size = <0x02000000>; /* 32M */ + alignment = <0x01000000>; + reusable; + }; + }; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + status = "okay"; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&gfx { + memory-region = <&gfx_memory>; + status = "okay"; +}; + +&gpio { + gpio-line-names = + /*A0-A7*/ "","","","bmc-ready","","","","", + /*B0-B7*/ "i2c-backup-sel","","","","","","","host0-shd-ack-n", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "button-power-n","control-power-n","button-reset-n", + "host0-sysreset-n","","","power-chassis-good","", + /*E0-E7*/ "","s0-vrd1-vddq0123-fault-n", + "s0-vrd1-vddq4567-fault-n","s0-vrd0-vddc-fault-n", + "s0-vrd3-p0v75-fault-n","","","", + /*F0-F7*/ "","","ps-atx-on-n","","","","","", + /*G0-G7*/ "led-bmc-heartbeat-n","button-identify-n","", + "led-system-fault-n","uboot-ready","bmc-salt2-n","","", + /*H0-H7*/ "ps-pwr-ok","","","","","","","", + /*I0-I7*/ "","","","","","","","", + /*J0-J7*/ "s0-hightemp-n","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "cpld-disable-bmc-n","","","","","s0-spi-auth-fail-n","","", + /*N0-N7*/ "","","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","led-identify-n", + "chassis-intrusion-n", + /*R0-R7*/ "","","ext-hightemp-n","spi0-program-sel","", + "output-hwm-bat-en","","", + /*S0-S7*/ "s0-vr-hot-n","","input-salt2-n","bmc-sysreset-n","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","","","s0-rtc-lock","","","","", + /*AA0-AA7*/ "s0-rtc-int-n","","","","","pmbus-sel-n","","", + /*AB0-AB7*/ "host0-reboot-ack-n","s0-sys-auth-failure-n", + "","","","","","", + /*AC0-AC7*/ "s0-fault-alert","host0-ready","s0-overtemp-n", + "","bmc-ok","host0-special-boot","presence-cpu0", + "host0-shd-req-n"; + + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; + +}; + +&i2c1 { + status = "okay"; + + i2c-mux1@73 { + compatible = "nxp,pca9548"; + reg = <0x73>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + nvme1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + pcie4: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + pcie5: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + pcie6: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + pcie7: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + nvme3: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + nvme2: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + nvme0: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + + i2c-mux2@75 { + compatible = "nxp,pca9548"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + nvme4: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + nvme5: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + nvme6: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + nvme7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + nvme8: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + nvme9: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + nvme10: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + nvme11: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c2 { + status = "okay"; + + smpro@4f { + compatible = "ampere,smpro"; + reg = <0x4f>; + }; +}; + +&i2c3 { + status = "okay"; + + // PSU FRU + eeprom@38 { + compatible = "atmel,24c02"; + reg = <0x38>; + }; +}; + +&i2c4 { + status = "okay"; + + temperature-sensor@29 { + compatible = "nuvoton,nct7802"; + reg = <0x29>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { /* LTD */ + reg = <0>; + status = "okay"; + }; + + channel@1 { /* RTD1 */ + reg = <1>; + sensor-type = "temperature"; + temperature-mode = "thermistor"; + }; + + channel@2 { /* RTD2 */ + reg = <2>; + sensor-type = "temperature"; + temperature-mode = "thermal-diode"; + }; + }; + + temperature-sensor@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c7 { + status = "okay"; + + // BMC FRU + eeprom@57 { + compatible = "atmel,24c128"; + reg = <0x57>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eth1_macaddress: macaddress@3f80 { + reg = <0x3f80 6>; + }; + + // The offset for eth0 really is at 0x3f88. + // eth0 and eth1 are swapped from what might be + // expected. + eth0_macaddress: macaddress@3f88 { + reg = <0x3f88 6>; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + + io_expander0: gpio@1c { + compatible = "nxp,pca9557"; + reg = <0x1c>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +// Bus for accessing the SCP EEPROM +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; + + ssif-bmc@10 { + compatible = "ssif-bmc"; + reg = <0x10>; + }; +}; + +// Connected to host Intel X550 (ALTRAD8UD-1L2T) or +// Broadcom BCM57414 (ALTRAD8UD2-1L2Q) interface. +// Unconnected on ALTRAD8UD-1L +&mac0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; + + status = "okay"; +}; + +// Connected to Realtek RTL8211E +&mac1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; + + nvmem-cells = <ð1_macaddress>; + nvmem-cell-names = "mac-address"; + + status = "okay"; +}; + +&pwm_tacho { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + status = "okay"; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00 0x08>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01 0x09>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02 0x0a>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0c>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0d>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0e>; + }; + + fan@7 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x07 0x0f>; + }; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + status = "okay"; + + // Host BIOS/UEFI EEPROM + flash@0 { + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + tfa@400000 { + reg = <0x400000 0x200000>; + label = "pnor-tfa"; + }; + + uefi@600000 { + reg = <0x600000 0x1A00000>; + label = "pnor-uefi"; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_nrts1_default>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; + + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; + + status = "okay"; +}; + +// The BMC's uart +&uart5 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + memory-region = <&video_engine_memory>; + + status = "okay"; +}; From c6a40c867467c23d531446c2b11d310b0a6641e7 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 13:32:31 -0600 Subject: [PATCH 398/757] arm64: dts: nuvoton: Add missing "device_type" property on memory node "device_type" is required for memory nodes, but is missing on Nuvoton npcm845-evb. Signed-off-by: Rob Herring (Arm) Signed-off-by: Andrew Jeffery --- arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts index 2638ee1c3846..5edf5d13342d 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts @@ -17,6 +17,7 @@ }; memory@0 { + device_type = "memory"; reg = <0x0 0x0 0x0 0x40000000>; }; From c76e026616b65e21e115351b1623cae732008c0d Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 2 Jan 2026 18:01:32 +0100 Subject: [PATCH 399/757] ARM: dts: microchip: sama7d65: add dma properties to usart6 Add the dma property and associated dma activation for usart6 as part of flx6 node. Is useful for usual default console on this product. Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20260102170135.70717-4-nicolas.ferre@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index cd2cf9a6f40b..4db7c2f7518b 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -617,6 +617,11 @@ interrupts = ; clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "usart"; + dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; atmel,usart-mode = ; atmel,fifo-size = <32>; status = "disabled"; From a395da9920b246d8d84dec09c7d6a7b52580ab27 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 2 Jan 2026 18:01:33 +0100 Subject: [PATCH 400/757] ARM: dts: microchip: sama7d65: add fifo-size to usart When missing, add the atmel,fifo-size = <32> property for usart nodes in flexcom. Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20260102170135.70717-5-nicolas.ferre@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index 4db7c2f7518b..ad1464c7b8c6 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -414,6 +414,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size = <32>; atmel,usart-mode = ; status = "disabled"; }; @@ -492,6 +493,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size = <32>; atmel,usart-mode = ; status = "disabled"; }; @@ -517,6 +519,7 @@ dma-names = "tx", "rx"; atmel,use-dma-rx; atmel,use-dma-tx; + atmel,fifo-size = <32>; atmel,usart-mode = ; status = "disabled"; }; From d08fc1f551b51816c8d9c4c4a1b8d1cc1e6c0806 Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Fri, 2 Jan 2026 18:01:34 +0100 Subject: [PATCH 401/757] ARM: dts: microchip: sama7d65: add missing flexcom nodes Add nodes for usart, spi and i2c when missing to the flexcom nodes. Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/20260102170135.70717-6-nicolas.ferre@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 271 ++++++++++++++++++++++ 1 file changed, 271 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index ad1464c7b8c6..385d47657220 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -419,6 +419,21 @@ status = "disabled"; }; + spi0: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, + <&dma1 AT91_XDMAC_DT_PERID(5)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c0: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -443,6 +458,22 @@ #size-cells = <1>; status = "disabled"; + uart1: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, + <&dma0 AT91_XDMAC_DT_PERID(7)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + spi1: spi@400 { compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; reg = <0x400 0x200>; @@ -497,6 +528,35 @@ atmel,usart-mode = ; status = "disabled"; }; + + spi2: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, + <&dma1 AT91_XDMAC_DT_PERID(9)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, + <&dma1 AT91_XDMAC_DT_PERID(9)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx3: flexcom@e182c000 { @@ -524,6 +584,21 @@ status = "disabled"; }; + spi3: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, + <&dma0 AT91_XDMAC_DT_PERID(11)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c3: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -579,6 +654,20 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + i2c4: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, + <&dma1 AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx5: flexcom@e201c000 { @@ -590,6 +679,37 @@ #size-cells = <1>; status = "disabled"; + uart5: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, + <&dma0 AT91_XDMAC_DT_PERID(15)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, + <&dma0 AT91_XDMAC_DT_PERID(15)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c5: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -629,6 +749,35 @@ atmel,fifo-size = <32>; status = "disabled"; }; + + spi6: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, + <&dma1 AT91_XDMAC_DT_PERID(17)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx7: flexcom@e2024000 { @@ -655,6 +804,35 @@ atmel,usart-mode = ; status = "disabled"; }; + + spi7: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + i2c7: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, + <&dma1 AT91_XDMAC_DT_PERID(19)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; }; flx8: flexcom@e281c000 { @@ -666,6 +844,37 @@ #size-cells = <1>; status = "disabled"; + uart8: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi8: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, + <&dma0 AT91_XDMAC_DT_PERID(21)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c8: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -690,6 +899,37 @@ #size-cells = <1>; status = "disabled"; + uart9: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi9: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, + <&dma0 AT91_XDMAC_DT_PERID(23)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c9: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; @@ -714,6 +954,37 @@ #size-cells = <1>; status = "disabled"; + uart10: serial@200 { + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + clock-names = "usart"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; + dma-names = "tx", "rx"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <32>; + atmel,usart-mode = ; + status = "disabled"; + }; + + spi10: spi@400 { + compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, + <&dma0 AT91_XDMAC_DT_PERID(25)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + i2c10: i2c@600 { compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; reg = <0x600 0x200>; From 481b64376c3fb72557725acf2f4fbc4f73bc3188 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 24 Dec 2025 16:50:46 +0000 Subject: [PATCH 402/757] dt-bindings: clock: renesas,r9a09g077/87: Add PCLKCAN ID Add PCLKCAN ID for CANFD to both R9A09G077 and R9A09G087 SoCs. This definition is required for describing CANFD device in DT. Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251224165049.3384870-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 + include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index 9eaedca6a616..c4863e444458 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -33,5 +33,6 @@ #define R9A09G077_ETCLKE 21 #define R9A09G077_XSPI_CLK0 22 #define R9A09G077_XSPI_CLK1 23 +#define R9A09G077_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 606468ac49a4..0d53f1e65077 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -33,5 +33,6 @@ #define R9A09G087_ETCLKE 21 #define R9A09G087_XSPI_CLK0 22 #define R9A09G087_XSPI_CLK1 23 +#define R9A09G087_PCLKCAN 24 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ From 0c3644ac3f8df9a79a59ff980538473d3b57d96c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 6 Jan 2026 18:14:01 +0100 Subject: [PATCH 403/757] riscv: dts: renesas: r9a07g043f: Move interrupt-parent to top node Move the "interrupt-parent = <&plic>" property from the soc node to the top node, for consistency with arch/arm64/boot/dts/renesas/r9a07g043u.dtsi. Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar Link: https://patch.msgid.link/97d3d70e42832f4ffa3888bec792b692a7ab700f.1767719409.git.geert+renesas@glider.be --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index a8bcb26f4270..571de3cafa82 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -12,6 +12,8 @@ #include / { + interrupt-parent = <&plic>; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -52,7 +54,6 @@ &soc { dma-noncoherent; - interrupt-parent = <&plic>; irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043f-irqc"; From e600933b6e518397b3f256dddd233e5d8e6cff93 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 15:31:51 -0600 Subject: [PATCH 404/757] ARM: dts: aspeed: ibm: Use non-deprecated AT25 properties The at25,* properties have been deprecated since 2012. These platforms weren't upstream until 2020 and 2023, so it should be safe to switch over to the "new" properties and just drop the deprecated ones. Signed-off-by: Rob Herring (Arm) Signed-off-by: Andrew Jeffery --- .../dts/aspeed/aspeed-bmc-ibm-everest.dts | 128 +++++++++--------- .../arm/boot/dts/aspeed/ibm-power10-dual.dtsi | 64 ++++----- .../arm/boot/dts/aspeed/ibm-power10-quad.dtsi | 64 ++++----- 3 files changed, 128 insertions(+), 128 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts index 5a0975d52492..561633d31039 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts @@ -2806,13 +2806,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -2823,13 +2823,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -2840,13 +2840,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -2857,13 +2857,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -3181,13 +3181,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3198,13 +3198,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3215,13 +3215,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3232,13 +3232,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -3556,13 +3556,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3573,13 +3573,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3590,13 +3590,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3607,13 +3607,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -3931,13 +3931,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3948,13 +3948,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3965,13 +3965,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -3982,13 +3982,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; diff --git a/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi b/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi index 06fac236773f..79eaf442c5bf 100644 --- a/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi +++ b/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi @@ -88,13 +88,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -105,13 +105,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -122,13 +122,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -139,13 +139,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -257,13 +257,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -274,13 +274,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -291,13 +291,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -308,13 +308,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; diff --git a/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi b/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi index 9501f66d0030..a54be7d0af0b 100644 --- a/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi +++ b/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi @@ -739,13 +739,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -756,13 +756,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -773,13 +773,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -790,13 +790,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; @@ -1114,13 +1114,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -1131,13 +1131,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -1148,13 +1148,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; @@ -1165,13 +1165,13 @@ #size-cells = <0>; eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <1000000>; + + address-width = <24>; + pagesize = <256>; + size = <0x80000>; }; }; }; From be0b304eeb8c5f77e4f98f64e58729d879195f2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Otto=20Pfl=C3=BCger?= Date: Tue, 6 Jan 2026 11:11:12 +0100 Subject: [PATCH 405/757] arm64: dts: mediatek: mt8183: Add missing endpoint IDs to display graph MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The endpoint IDs in the display graph are expected to match the associated display path number, i.e. all endpoints connected to mmsys_ep_main must have reg = <0> and all endpoints connected to mmsys_ep_ext must have reg = <1>. Add the missing ID to all endpoints in the display graph, based on mt8365.dtsi as an existing example that does this correctly. Fixes: e72d63fa0563 ("arm64: dts: mediatek: mt8183: Migrate to display controller OF graph") Reported-by: Evans Jahja Closes: https://lore.kernel.org/linux-mediatek/CAAq5pW9o3itC0G16LnJO7KMAQ_XoqXUpB=cuJ_7e3-H11zKd5Q@mail.gmail.com/ Tested-by: Chen-Yu Tsai Signed-off-by: Otto Pflüger [Angelo: Fixed dtbs_check issues] Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 37 ++++++++++++++++++++---- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4e20a8f2eb25..95cc06799533 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1812,15 +1812,23 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - ovl_2l1_in: endpoint { + + ovl_2l1_in: endpoint@1 { + reg = <1>; remote-endpoint = <&mmsys_ep_ext>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - ovl_2l1_out: endpoint { + + ovl_2l1_out: endpoint@1 { + reg = <1>; remote-endpoint = <&rdma1_in>; }; }; @@ -1872,15 +1880,23 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - rdma1_in: endpoint { + + rdma1_in: endpoint@1 { + reg = <1>; remote-endpoint = <&ovl_2l1_out>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - rdma1_out: endpoint { + + rdma1_out: endpoint@1 { + reg = <1>; remote-endpoint = <&dpi_in>; }; }; @@ -2076,15 +2092,24 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - dpi_in: endpoint { + + dpi_in: endpoint@1 { + reg = <1>; remote-endpoint = <&rdma1_out>; }; }; port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; - dpi_out: endpoint { }; + + dpi_out: endpoint@1 { + reg = <1>; + }; }; }; }; From 262cb81069c65373d4d6b773413552a65b478f7e Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:52 +0100 Subject: [PATCH 406/757] arm64: dts: mediatek: mt7981b: Add PCIe and USB support Add device tree nodes for PCIe controller and USB3 XHCI host controller on MT7981B SoC. Both controllers share the USB3 PHY which can be configured for either USB3 or PCIe operation. The USB3 XHCI controller supports USB 2.0 and USB 3.0 SuperSpeed operation. The PCIe controller is compatible with PCIe Gen2 specifications. Also add the topmisc syscon node required for USB/PCIe PHY multiplexing. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 80 +++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 416096b80770..d3f37413413e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include / { @@ -223,6 +224,55 @@ status = "disabled"; }; + xhci: usb@11200000 { + compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + status = "disabled"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7981-pcie", + "mediatek,mt8192-pcie"; + reg = <0 0x11280000 0 0x4000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0 0x20000000 + 0x0 0x20000000 0 0x10000000>; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + device_type = "pci"; + phys = <&u3port0 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + interrupts = ; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + status = "disabled"; + + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, @@ -252,6 +302,36 @@ }; }; + topmisc: topmisc@11d10000 { + compatible = "mediatek,mt7981-topmisc", "syscon"; + reg = <0 0x11d10000 0 0x10000>; + #clock-cells = <1>; + }; + + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7981-tphy", + "mediatek,generic-tphy-v2"; + ranges = <0 0 0x11e10000 0x1700>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,syscon-type = <&topmisc 0x218 0>; + }; + }; + efuse@11f20000 { compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; reg = <0 0x11f20000 0 0x1000>; From 8f350dbb2e4a7eaa5de97c6502d004caa26eba1a Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:53 +0100 Subject: [PATCH 407/757] arm64: dts: mediatek: mt7981b-openwrt-one: Enable PCIe and USB Enable the PCIe controller and USB3 XHCI host on the OpenWrt One board. The USB controller is configured for USB 2.0 only mode, as the shared USB3/PCIe PHY is dedicated to PCIe functionality on this board. Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 2e39e7287730..7382599cfea2 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -67,9 +67,40 @@ linux,default-trigger = "netdev"; }; }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; }; &pio { + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_pereset"; + }; + }; + pwm_pins: pwm-pins { mux { function = "pwm"; @@ -163,3 +194,15 @@ &uart0 { status = "okay"; }; + +&usb_phy { + status = "okay"; +}; + +&xhci { + phys = <&u2port0 PHY_TYPE_USB2>; + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; From 9846a8c6031855ed9be45b4cc538c2b80965f816 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:54 +0100 Subject: [PATCH 408/757] arm64: dts: mediatek: mt7981b: Add Ethernet and WiFi offload support Add device tree nodes for the Ethernet subsystem on MT7981B SoC, including: - Ethernet MAC controller with dual GMAC support - Wireless Ethernet Dispatch (WED) - SGMII PHY controllers for high-speed Ethernet interfaces - Reserved memory regions for WiFi offload processor Signed-off-by: Sjoerd Simons [Angelo: Removed useless address/size cells from main eth node] Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 131 +++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index d3f37413413e..e277adcaf893 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -47,11 +48,36 @@ #size-cells = <2>; ranges; + wo_boot: wo-boot@15194000 { + reg = <0 0x15194000 0 0x1000>; + no-map; + }; + + wo_ilm0: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_dlm0: wo-dlm@151e8000 { + reg = <0 0x151e8000 0 0x2000>; + no-map; + }; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ secmon_reserved: secmon@43000000 { reg = <0 0x43000000 0 0x30000>; no-map; }; + + wo_emi0: wo-emi@47d80000 { + reg = <0 0x47d80000 0 0x40000>; + no-map; + }; + + wo_data: wo-data@47dc0000 { + reg = <0 0x47dc0000 0 0x240000>; + no-map; + }; }; soc { @@ -107,6 +133,18 @@ #pwm-cells = <2>; }; + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7981-sgmiisys_0", "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7981-sgmiisys_1", "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x100>; @@ -345,15 +383,106 @@ thermal_calibration: thermal-calib@274 { reg = <0x274 0xc>; }; + + phy_calibration: phy-calib@8dc { + reg = <0x8dc 0x10>; + }; }; - clock-controller@15000000 { + ethsys: clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; + wed: wed@15010000 { + compatible = "mediatek,mt7981-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif0>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7981-eth"; + reg = <0 0x15100000 0 0x40000>; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, + <&topckgen CLK_TOP_CB_SGM_325M>; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&topckgen CLK_TOP_SGM_REG>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&sgmiisys0 CLK_SGM0_CK0_EN>, + <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, + <&sgmiisys1 CLK_SGM1_TX_EN>, + <&sgmiisys1 CLK_SGM1_RX_EN>, + <&sgmiisys1 CLK_SGM1_CK1_EN>, + <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu0", + "sgmii_ck", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", + "pdma1", "pdma2", "pdma3"; + sram = <ð_sram>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,infracfg = <&topmisc>; + mediatek,wed = <&wed>; + status = "disabled"; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + int_gbe_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-mode = "gmii"; + phy-is-integrated; + nvmem-cells = <&phy_calibration>; + nvmem-cell-names = "phy-cal-data"; + }; + }; + }; + + eth_sram: sram@15140000 { + compatible = "mmio-sram"; + reg = <0 0x15140000 0 0x40000>; + ranges = <0 0x15140000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = ; + }; + wifi@18000000 { compatible = "mediatek,mt7981-wmac"; reg = <0 0x18000000 0 0x1000000>, From ecc68d72b50d17241ec9d44dca11633589bd0049 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:55 +0100 Subject: [PATCH 409/757] arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet Enable the Ethernet subsystem on OpenWrt One board with dual-MAC configuration: - GMAC0: Connected to external Airoha EN8811H 2.5GbE PHY via SGMII (2500base-x mode) for WAN connectivity with LED indicators - GMAC1: Connected to internal MT7981 1GbE PHY (GMII mode) for LAN Ethernet aliases are defined to provide consistent network interface naming (ethernet0 = LAN, ethernet1 = WAN). Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 7382599cfea2..2aea89900645 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -12,6 +12,8 @@ model = "OpenWrt One"; aliases { + ethernet0 = &gmac1; + ethernet1 = &gmac0; serial0 = &uart0; }; @@ -87,6 +89,58 @@ }; }; +ð { + status = "okay"; + + /* WAN interface */ + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + nvmem-cells = <&wan_factory_mac 0>; + nvmem-cell-names = "mac-address"; + phy-mode = "2500base-x"; + phy-handle = <&phy15>; + }; + + /* LAN interface */ + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "gmii"; + phy-handle = <&int_gbe_phy>; + }; +}; + +&mdio_bus { + phy15: ethernet-phy@f { + compatible = "ethernet-phy-id03a2.a411"; + reg = <0xf>; + interrupt-parent = <&pio>; + interrupts = <38 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + function = LED_FUNCTION_WAN; + color = ; + }; + + led@1 { + reg = <1>; + function = LED_FUNCTION_WAN; + color = ; + }; + }; + }; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -191,6 +245,10 @@ }; }; +&sgmiisys0 { + mediatek,pnswap; +}; + &uart0 { status = "okay"; }; From 46757ad083ce9a88ea157fe8b2b8f57d4db1801d Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:56 +0100 Subject: [PATCH 410/757] arm64: dts: mediatek: mt7981b: Disable wifi by default Disable the wifi block by default as it won't function properly without at least pin muxing. This doesn't enable wifi on any of the existing mt7981b devices as a required memory-region property is missing, causing the driver to fail probing anyway. Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index e277adcaf893..700f9c330bbb 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -497,6 +497,7 @@ clock-names = "mcu", "ap2conn"; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; + status = "disabled"; }; }; From c0379b6fa1645401c46a22845bb34d5498a3d1b5 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:57 +0100 Subject: [PATCH 411/757] arm64: dts: mediatek: mt7981b: Add wifi memory region Add required memory region for the builtin wifi block. Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 700f9c330bbb..324ae1395b3b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -69,6 +69,11 @@ no-map; }; + wmcpu_emi: wmcpu-reserved@47c80000 { + reg = <0 0x47c80000 0 0x100000>; + no-map; + }; + wo_emi0: wo-emi@47d80000 { reg = <0 0x47d80000 0 0x40000>; no-map; @@ -495,6 +500,7 @@ clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; clock-names = "mcu", "ap2conn"; + memory-region = <&wmcpu_emi>; resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; status = "disabled"; From 6fd69ff487c6a4cb3f45e53684937975cb1b67c1 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Tue, 23 Dec 2025 13:37:58 +0100 Subject: [PATCH 412/757] arm64: dts: mediatek: mt7981b-openwrt-one: Enable wifi Enable Dual-band WiFI 6 functionality on the Openwrt One Signed-off-by: Sjoerd Simons Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt7981b-openwrt-one.dts | 24 +++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 2 +- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 2aea89900645..3de368c73bc8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -180,6 +180,22 @@ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; }; }; + + wifi_dbdc_pins: wifi-dbdc-pins { + mux { + function = "eth"; + groups = "wf0_mode1"; + }; + + conf { + pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", + "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", + "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", + "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", + "WF_CBA_RESETB", "WF_DIG_RESETB"; + drive-strength = <4>; + }; + }; }; &pwm { @@ -257,6 +273,14 @@ status = "okay"; }; +&wifi { + nvmem-cells = <&wifi_factory_calibration>; + nvmem-cell-names = "eeprom"; + pinctrl-names = "dbdc"; + pinctrl-0 = <&wifi_dbdc_pins>; + status = "okay"; +}; + &xhci { phys = <&u2port0 PHY_TYPE_USB2>; vusb33-supply = <®_3p3v>; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 324ae1395b3b..4084f4dfa3e5 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -488,7 +488,7 @@ interrupts = ; }; - wifi@18000000 { + wifi: wifi@18000000 { compatible = "mediatek,mt7981-wmac"; reg = <0 0x18000000 0 0x1000000>, <0 0x10003000 0 0x1000>, From 6c90d33aedd355732062cc96d03fe4adb7609e8b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:03 +0100 Subject: [PATCH 413/757] arm64: dts: mediatek: mt8195: Add DPI1, HDMI, HDMI PHY/DDC nodes Add all of the nodes that are required to enable HDMI output, including ones describing the HDMI PHY, Controller and DDC, and the Digital Parallel Interface instance that is internally connected to the HDMI Controller. All of the added nodes are disabled by default as usage is board dependent. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 85 ++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index c7adafaa8328..c72e34c57629 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -26,8 +26,10 @@ aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + dpi1 = &dpi1; gce0 = &gce0; gce1 = &gce1; + hdmi0 = &hdmi; ethdr0 = ðdr0; mutex0 = &mutex; mutex1 = &mutex1; @@ -1857,6 +1859,23 @@ #clock-cells = <1>; }; + hdmi_phy: hdmi-phy@11d5f000 { + compatible = "mediatek,mt8195-hdmi-phy"; + reg = <0 0x11d5f000 0 0x100>; + clocks = <&topckgen CLK_TOP_HDMI_XTAL>, + <&infracfg_ao CLK_INFRA_AO_HDMI_26M>, + <&apmixedsys CLK_APMIXED_HDMIPLL1>, + <&apmixedsys CLK_APMIXED_HDMIPLL2>; + clock-names = "pll_ref", "26m", "pll1", "pll2"; + clock-output-names = "hdmi_txpll"; + + #clock-cells = <0>; + #phy-cells = <0>; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "disabled"; + }; + i2c0: i2c@11e00000 { compatible = "mediatek,mt8195-i2c", "mediatek,mt8192-i2c"; @@ -3670,6 +3689,34 @@ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; }; + dpi1: dpi@1c112000 { + compatible = "mediatek,mt8195-dpi"; + reg = <0 0x1c112000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DPI1>, + <&vdosys1 CLK_VDO1_DPI1_MM>, + <&vdosys1 CLK_VDO1_DPI1_HDMI>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_DPI1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi1_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dpi1_out: endpoint { }; + }; + }; + }; + dp_intf1: dp-intf@1c113000 { compatible = "mediatek,mt8195-dp-intf"; reg = <0 0x1c113000 0 0x1000>; @@ -3730,6 +3777,44 @@ "gfx_fe1_async", "vdo_be_async"; }; + hdmi: hdmi-tx@1c300000 { + compatible = "mediatek,mt8195-hdmi-tx"; + #sound-dai-cells = <1>; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + assigned-clocks = <&topckgen CLK_TOP_HDCP>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + status = "disabled"; + + hdmitx_ddc: i2c { + compatible = "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { }; + }; + }; + }; + edp_tx: edp-tx@1c500000 { compatible = "mediatek,mt8195-edp-tx"; reg = <0 0x1c500000 0 0x8000>; From 5875428ac6c7d687f9a51aef7c8665310f06be64 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:04 +0100 Subject: [PATCH 414/757] arm64: dts: mediatek: mt8188: Add DPI1, HDMI, HDMI PHY/DDC nodes Add all of the nodes that are required to enable HDMI output, including ones describing the HDMI PHY, Controller and DDC, and the Digital Parallel Interface instance that is internally connected to the HDMI Controller. All of the added nodes are disabled by default as usage is board dependent. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 82 ++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 90c388f1890f..e2a17359e407 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -26,6 +26,7 @@ aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + dpi1 = &dpi1; dsc0 = &dsc0; ethdr0 = ðdr0; gce0 = &gce0; @@ -2038,6 +2039,19 @@ }; }; + hdmi_phy: hdmi-phy@11d5f000 { + compatible = "mediatek,mt8188-hdmi-phy", "mediatek,mt8195-hdmi-phy"; + reg = <0 0x11d5f000 0 0x100>; + clocks = <&infracfg_ao CLK_INFRA_AO_HDMI_26M>; + clock-names = "pll_ref"; + clock-output-names = "hdmi_txpll"; + #clock-cells = <0>; + #phy-cells = <0>; + mediatek,ibias = <0xa>; + mediatek,ibias_up = <0x1c>; + status = "disabled"; + }; + mipi_tx_config0: dsi-phy@11c80000 { compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; reg = <0 0x11c80000 0 0x1000>; @@ -3406,6 +3420,34 @@ mediatek,merge-fifo-en; }; + dpi1: dpi@1c112000 { + compatible = "mediatek,mt8188-dpi", "mediatek,mt8195-dpi"; + reg = <0 0x1c112000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DPI1>, + <&vdosys1 CLK_VDO1_DPI1_MM>, + <&vdosys1 CLK_VDO1_DPI1_HDMI>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_DPI1_MM_CK>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi1_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dpi1_out: endpoint { }; + }; + }; + }; + dp_intf1: dp-intf@1c113000 { compatible = "mediatek,mt8188-dp-intf"; reg = <0 0x1c113000 0 0x1000>; @@ -3530,6 +3572,46 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; }; + hdmi: hdmi@1c300000 { + compatible = "mediatek,mt8188-hdmi-tx"; + #sound-dai-cells = <1>; + reg = <0 0x1c300000 0 0x1000>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP>, + <&topckgen CLK_TOP_HDCP_24M>, + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; + assigned-clocks = <&topckgen CLK_TOP_HDCP>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4_D8>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_HDMI_TX>; + phys = <&hdmi_phy>; + phy-names = "hdmi"; + status = "disabled"; + + hdmi_ddc: i2c { + compatible = "mediatek,mt8188-hdmi-ddc", + "mediatek,mt8195-hdmi-ddc"; + clocks = <&clk26m>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hdmi0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + hdmi0_out: endpoint { }; + }; + }; + }; + + edp_tx: edp-tx@1c500000 { compatible = "mediatek,mt8188-edp-tx"; reg = <0 0x1c500000 0 0x8000>; From ae9198b7a5d64e01632cd450d4408f162f88c3be Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:05 +0100 Subject: [PATCH 415/757] arm64: dts: mediatek: mt8390-genio-common: Enable HDMI output Add a node for the HDMI-A connector found on this board, then configure the display pipeline and enable the required DPI1 interface, HDMI controller, its integrated DDC and the HDMI PHY to enable support for the HDMI output provided by these EVKs. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8390-genio-common.dtsi | 141 ++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index a2cdecd2b903..5fa1f5fbad18 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -55,6 +55,20 @@ wakeup-delay-ms = <30>; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmi_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -328,6 +342,18 @@ remote-endpoint = <&dsi0_in>; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + &gamma0_out { remote-endpoint = <&postmask0_in>; }; @@ -337,6 +363,55 @@ status = "okay"; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -475,6 +550,35 @@ status = "okay"; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6359_vproc2_buck_reg>; }; @@ -727,6 +831,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = ; + bias-pull-down; + }; + + pins-cec { + pinmux = ; + bias-disable; + }; + + pins-ddc { + pinmux = , + ; + drive-strength = <10>; + }; + }; + i2c0_pins: i2c0-pins { pins { pinmux = , @@ -1286,6 +1415,18 @@ }; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { status = "okay"; }; From 0ad0f933fc0dad5a51996533d3cdb11a24c83e00 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:06 +0100 Subject: [PATCH 416/757] arm64: dts: mediatek: mt8390-genio-common: Add HDMI sound output support Add in the sound node a new dai-link for ETDM3_OUT_BE to add the sound output support through the HDMI connector. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi index 5fa1f5fbad18..2062506f6cc5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi @@ -1344,6 +1344,15 @@ sound-dai = <&dmic_codec>; }; }; + + dai-link-2 { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; + }; &spi2 { From 19a385bd460e97b216c82603c01081f7b5c9e4ef Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 17 Dec 2025 11:19:07 +0100 Subject: [PATCH 417/757] arm64: dts: mediatek: mt8395-radxa-nio-12l: Enable HDMI output Add a definition for the on-board HDMI connector, enable and add the relevant configuration for the HDMI PHY and controller, and define the pins used by those. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8395-radxa-nio-12l.dts | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index d32f973f5e05..b0e18876bd5d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -37,6 +37,20 @@ stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmitx_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -245,6 +259,18 @@ }; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>; @@ -265,11 +291,61 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &gpu { mali-supply = <&mt6315_7_vbuck1>; status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + + status = "okay"; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-0 = <&i2c2_pins>; @@ -448,6 +524,35 @@ }; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; @@ -647,6 +752,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = ; + bias-pull-down; + }; + + pins-ddc { + pinmux = , + ; + drive-strength = <10>; + }; + + pins-cec { + pinmux = ; + bias-disable; + }; + }; + i2c2_pins: i2c2-pins { pins-bus { pinmux = , @@ -1058,6 +1188,18 @@ status = "okay"; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { vbus-supply = <&otg_vbus_regulator>; status = "okay"; From 0ddfd2f29ae229fb67b710677e7d7004e685d733 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:08 +0100 Subject: [PATCH 418/757] arm64: dts: mediatek: mt8395-radxa-nio-12l: Add HDMI sound output support Add in the sound node a new dai-link for ETDM3_OUT_BE to add the sound output support through the HDMI TX connector. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index b0e18876bd5d..1cd4b84e9861 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -1072,6 +1072,14 @@ sound-dai = <&pmic 0>; }; }; + + hdmi-dai-link { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; }; &spi1 { From e1480453aed83e2b0d2e52a0e439c56bd4c3a4c4 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:09 +0100 Subject: [PATCH 419/757] arm64: dts: mediatek: mt8395-genio-common: Enable HDMI output Add a definition for the on-board HDMI connector, enable and add the relevant configuration for the HDMI PHY and controller, and define the pins used by those. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt8395-genio-common.dtsi | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 2b7167804e71..345fc5ac9e03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -26,6 +26,20 @@ stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + ddc-i2c-bus = <&hdmitx_ddc>; + hdmi-pwr-supply = <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi0_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -247,6 +261,18 @@ wakeup-delay-ms = <200>; }; +&dpi1 { + status = "okay"; +}; + +&dpi1_in { + remote-endpoint = <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint = <&hdmi0_in>; +}; + &dsi0 { #address-cells = <1>; #size-cells = <0>; @@ -313,6 +339,35 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &gamma0_out { remote-endpoint = <&dither0_in>; }; @@ -329,6 +384,27 @@ status = "okay"; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + status = "okay"; +}; + +&hdmi0_in { + remote-endpoint = <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint = <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_vreg_pins>; + + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-0 = <&i2c1_pins>; @@ -533,6 +609,35 @@ }; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dpi1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; @@ -762,6 +867,31 @@ }; }; + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = ; + bias-pull-down; + }; + + pins-ddc { + pinmux = , + ; + drive-strength = <10>; + }; + + pins-cec { + pinmux = ; + bias-disable; + }; + }; + i2c0_pins: i2c0-pins { pins { pinmux = , @@ -1212,6 +1342,18 @@ }; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { status = "okay"; }; From 7fe8a313e4646ae4c5cb6a6e46b78bf5c9166066 Mon Sep 17 00:00:00 2001 From: Louis-Alexis Eyraud Date: Wed, 17 Dec 2025 11:19:10 +0100 Subject: [PATCH 420/757] arm64: dts: mediatek: mt8395-genio-common: Add HDMI sound output support Add in the sound node a new dai-link for ETDM3_OUT_BE to add the sound output support through the HDMI TX connector. Signed-off-by: Louis-Alexis Eyraud Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi index 345fc5ac9e03..d849af4d3613 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi @@ -1189,6 +1189,14 @@ sound-dai = <&pmic 0>; }; }; + + hdmi-dai-link { + link-name = "ETDM3_OUT_BE"; + + codec { + sound-dai = <&hdmi 0>; + }; + }; }; &spi1 { From a7a53f7482f96f88d6ab2064828f6f6bdb93c43e Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:37 +0100 Subject: [PATCH 421/757] dt-bindings: vendor-prefixes: Add Ezurio LLC Ezurio is the new name of Laird Connectivity after it acquired Boundary Devices. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..26e6935e5115 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -555,6 +555,8 @@ patternProperties: description: Exegin Technologies Limited "^ezchip,.*": description: EZchip Semiconductor + "^ezurio,.*": + description: Ezurio LLC "^facebook,.*": description: Facebook "^fairchild,.*": From 07a4700f95745671e8f257d56db6aaf244350111 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:38 +0100 Subject: [PATCH 422/757] dt-bindings: arm: mediatek: Add Ezurio Tungsten entries Add device tree bindings support for the Ezurio Tungsten 510 (MT8370) SMARC [1] / Ezurio Tungsten 700 (MT8390) SMARC [2] + Universal SMARC carrier board [3]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/product/tungsten700-smarc [3] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 718d732174b9..382d0eb4d0af 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -438,12 +438,14 @@ properties: - const: mediatek,mt8365 - items: - enum: + - ezurio,mt8370-tungsten-smarc - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 - items: - enum: + - ezurio,mt8390-tungsten-smarc - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 From 18e1d95faeaca2e1b3887d2c44fe44b8bb2f123c Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:39 +0100 Subject: [PATCH 423/757] arm64: dts: mediatek: mt8188: switch mmc nodes to interrupts-extended No functional change but will allow other dts including this one to override the interrupts, for eint support for instance, without having to delete the 'interrupts' property. Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index e2a17359e407..75133794cec3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -1801,7 +1801,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11230000 0 0x10000>, <0 0x11f50000 0 0x1000>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC50_0>, <&infracfg_ao CLK_INFRA_AO_MSDC0>, <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, @@ -1814,7 +1814,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11240000 0 0x1000>, <0 0x11eb0000 0 0x1000>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC30_1>, <&infracfg_ao CLK_INFRA_AO_MSDC1>, <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; @@ -1828,7 +1828,7 @@ compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11250000 0 0x1000>, <0 0x11e60000 0 0x1000>; - interrupts = ; + interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&topckgen CLK_TOP_MSDC30_2>, <&infracfg_ao CLK_INFRA_AO_MSDC2>, <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; From 9fda4a8a479f030a2a267b1823ffe0687aea8fd4 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:40 +0100 Subject: [PATCH 424/757] arm64: dts: mediatek: add device tree for Tungsten 510 board Add device tree to support Ezurio Tungsten 510 (MT8370) SMARC SOM [1] + Universal SMARC carrier board [2]. It includes support for the MIPI-DSI BD070LIC3 display which uses the Tianma TM070JDHG30 panel + TI SN65DSI84 MIPI-DSI to LVDS bridge [3]. [1] https://www.ezurio.com/product/tungsten510-smarc [2] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier [3] https://www.ezurio.com/product/bd070lic3-7-touchscreen-display Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8370-tungsten-smarc.dts | 14 + .../dts/mediatek/mt8390-tungsten-smarc.dtsi | 1489 +++++++++++++++++ 3 files changed, 1504 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3f76d9ce9879..9e26d828d796 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts b/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts new file mode 100644 index 000000000000..4c3a7c4579c8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8370-tungsten-smarc.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ +/dts-v1/; +#include "mt8370.dtsi" +#include "mt8390-tungsten-smarc.dtsi" + +/ { + model = "Ezurio Tungsten510 SMARC (MT8370)"; + compatible = "ezurio,mt8370-tungsten-smarc", "mediatek,mt8370", + "mediatek,mt8188"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi new file mode 100644 index 000000000000..40b381d4cc35 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dtsi @@ -0,0 +1,1489 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ + +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + aliases { + dsi0 = &disp_dsi0; + ethernet0 = ð + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + mmc0 = &mmc0; + mmc1 = &mmc1; + mmc2 = &mmc2; + rtc0 = &rv3028; + rtc1 = &mt6359rtc; + serial0 = &uart0; + }; + + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <768>; + num-interpolated-steps = <1023>; + enable-gpios = <&pio 30 GPIO_ACTIVE_HIGH>; + pwms = <&disp_pwm0 0 30000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x1 0x00000000>; + }; + + panel-dsi0 { + compatible = "tianma,tm070jdhg30"; + backlight = <&backlight_lcd0>; + power-supply = <®_5v>; + + port { + dsi0_panel_in: endpoint { + remote-endpoint = <&sn65dsi84_bridge_out>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + regulator-efuse { + compatible = "regulator-output"; + vout-supply = <&mt6359_vefuse_ldo_reg>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "reg_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "reg_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "reg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sdcard_en_3v3: regulator-sdcard-en { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "sdcard_en_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 111 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p0_vbus: regulator-usb-p0-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus_p0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator-usb-p1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_hub_pins>; + regulator-name = "vbus_p1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 147 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator-usb-p2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_eth_pins>; + regulator-name = "vbus_p2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pins>; + post-power-on-delay-ms = <200>; + reset-gpios = <&pio 89 GPIO_ACTIVE_LOW>; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&disp_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + +&disp_dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi84_bridge_in>; + }; + }; + }; +}; + +&dither0_in { + remote-endpoint = <&postmask0_out>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio = <&pio 27 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 11000 1000>; + status = "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x7>; + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&gamma0_out { + remote-endpoint = <&postmask0_in>; +}; + +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + i2c-mux@73 { + compatible = "nxp,pca9546"; + reg = <0x73>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_mux_pins>; + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_mux_gp_0: i2c@0 { + reg = <0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_1: i2c@1 { + reg = <1>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_2: i2c@2 { + reg = <2>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_gp_3: i2c@3 { + reg = <3>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; + + i2c-mux@73 { + compatible = "nxp,pca9546"; + reg = <0x73>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c_mux_smarc_lcd_pins>; + reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_mux_lcd_0: i2c@0 { + reg = <0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_1: i2c@1 { + reg = <1>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_2: i2c@2 { + reg = <2>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c_mux_lcd_3: i2c@3 { + reg = <3>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c_mux_gp_0 { + rv3028: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + interrupts-extended = <&pio 42 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rv3028_pins>; + #clock-cells = <0>; + wakeup-source; + }; +}; + +&i2c_mux_gp_1 { + usb-typec@60 { + compatible = "ti,hd3ss3220"; + reg = <0x60>; + interrupts-extended = <&pio 45 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hd3ss3220_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb_role_switch>; + }; + }; + }; + }; +}; + +&i2c_mux_gp_2 { + codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&topckgen CLK_TOP_I2SO1>; + AVDD-supply = <®_1v8>; + CPVDD-supply = <®_1v8>; + DBVDD-supply = <®_3v3>; + DCVDD-supply = <®_1v8>; + MICVDD-supply = <®_3v3>; + PLLVDD-supply = <®_1v8>; + SPKVDD1-supply = <®_5v>; + SPKVDD2-supply = <®_5v>; + gpio-cfg = < + 0x0000 /* n/c */ + 0x0000 /* gpio2: */ + 0x0000 /* gpio3: */ + 0x0000 /* n/c */ + 0x8081 /* gpio5:HP detect */ + 0x8095 /* gpio6:Mic detect */ + >; + }; +}; + +&i2c_mux_lcd_2 { + bridge@2c { + compatible = "ti,sn65dsi84"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_sn65dsi84_pins>; + enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sn65dsi84_bridge_in: endpoint { + remote-endpoint = <&dsi0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + + sn65dsi84_bridge_out: endpoint { + remote-endpoint = <&dsi0_panel_in>; + }; + }; + }; + }; + + touchscren@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_dsi0_goodix_pins>; + interrupts-extended = <&pio 146 IRQ_TYPE_LEVEL_HIGH>; + irq-gpios = <&pio 146 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + bus-width = <8>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + hs400-ds-delay = <0x1481b>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + non-removable; + no-sd; + no-sdio; + supports-cqe; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&mmc1 { + bus-width = <4>; + cap-sd-highspeed; + max-frequency = <200000000>; + sd-uhs-sdr104; + sd-uhs-sdr50; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; + vmmc-supply = <&sdcard_en_3v3>; + status = "okay"; +}; + +&mmc2 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <200000000>; + no-mmc; + non-removable; + no-sd; + sd-uhs-sdr104; + wakeup-source; + pinctrl-names = "default", "state_uhs", "state_eint"; + pinctrl-0 = <&mmc2_default_pins>; + pinctrl-1 = <&mmc2_uhs_pins>; + pinctrl-2 = <&mmc2_eint_pins>; + interrupt-names = "msdc", "sdio_wakeup"; + interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 172 IRQ_TYPE_LEVEL_LOW>; + vmmc-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vqmmc-supply = <&mt6359_vcn18_ldo_reg>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +&mipi_tx_config0 { + status = "okay"; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; + mediatek,mic-type-1 = <3>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name = "vcn18_pmu"; + regulator-always-on; + regulator-boot-on; +}; + +&mt6359_vcn33_1_bt_ldo_reg { + regulator-name = "vcn33_1_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name = "vcn33_2_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name = "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vemc_1_ldo_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name = "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vmodem_buck_reg { + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name = "vpa_pmu"; + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name = "vgpu"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <225000>; +}; + +&mt6359_vs2_buck_reg { + regulator-min-microvolt = <1600000>; + regulator-boot-on; +}; + +&mt6359_vpu_buck_reg { + regulator-name = "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name = "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread = <225000>; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name = "vsim1_pmu"; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name = "vufs18_pmu"; + regulator-always-on; +}; + +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default_pins>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; + + keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = ; + wakeup-source; + }; + }; +}; + +&postmask0_in { + remote-endpoint = <&gamma0_out>; +}; + +&postmask0_out { + remote-endpoint = <&dither0_in>; +}; + +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&spi0 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-name = "vbuck1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck3: vbuck3 { + regulator-name = "vbuck3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck4: vbuck4 { + regulator-name = "vbuck4"; + regulator-min-microvolt = <1193750>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1193750>; + }; + }; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ssusb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + usb-role-switch; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usbotg_pins>; + pinctrl-names = "default"; + status = "okay"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + hs_ep: endpoint { + remote-endpoint = <&usb_hs_ep>; + }; + }; + + port@1 { + reg = <1>; + ss_ep: endpoint { + remote-endpoint = <&hd3ss3220_in_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + + port@1 { + reg = <1>; + usb_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; + }; +}; + +&u2port0 { + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&xhci0 { + vbus-supply = <&usb_p0_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb1 { + dr_mode = "host"; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&u2port1 { + status = "okay"; +}; + +&u3port1 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&xhci1 { + vbus-supply = <&usb_p1_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&ssusb2 { + dr_mode = "host"; + maximum-speed = "high-speed"; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&u2port2 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&xhci2 { + vbus-supply = <&usb_p2_vbus>; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ethernet@1 { + compatible = "usb424,7850"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <1>; + microchip,led-modes = < + LAN78XX_LINK_1000_ACTIVITY + LAN78XX_LINK_10_ACTIVITY + LAN78XX_LINK_10_100_ACTIVITY + LAN78XX_LINK_ACTIVITY + >; + }; + }; + }; +}; + +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + +&watchdog { + pinctrl-names = "default"; + pinctrl-0 = <&watchdog_pins>; +}; + +&pio { + audio_pins: audio-pins { + pins-aud-pmic { + pinmux = ; + }; + + pins-pcm-wifi { + pinmux = ; + }; + + pins-i2s { + pinmux = ; + }; + }; + + disp_pwm0_pins: disp-pwm0-pins { + pins { + pinmux = ; + bias-pull-down; + }; + }; + + dsi0_sn65dsi84_pins: dsi0-sn65dsi84-pins { + pins-irq { + pinmux = ; + bias-pull-down; + input-enable; + }; + + pins-enable { + pinmux = ; + bias-pull-down; + }; + }; + + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + pins-cc { + pinmux = , + , + ; + drive-strength = <8>; + }; + pins-rxd { + pinmux = , + , + , + , + ; + drive-strength = <8>; + bias-pull-up = ; + }; + pins-mdio { + pinmux = , + ; + drive-strength = <8>; + input-enable; + }; + pins-power { + pinmux = ; /* GP_EQOS_RESET */ + output-high; + }; + pins-intr { + pinmux = ; /* GPIRQ_EQOS_PHY */ + bias-pull-up = ; + input-enable; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + pins-cc { + pinmux = , + , + , + ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + + gpio_keys_pins: gpio-keys-pins { + pins-keys { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + hd3ss3220_pins: hd3ss3320-pins { + pins-irq { + pinmux = ; + bias-pull-up = ; + input-enable; + }; + }; + + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux = ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux = ; + bias-pull-down; + }; + + pins-cec { + pinmux = ; + bias-disable; + }; + + pins-ddc { + pinmux = , + ; + drive-strength = <10>; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c0_mux_pins: i2c0-mux-pins { + pins-reset { + pinmux = ; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c_mux_smarc_lcd_pins: i2c-mux-smarc-lcd-pins { + pins-reset { + pinmux = ; + bias-pull-down; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-pwr { + pinmux = ; + bias-pull-down; + }; + + pins-pullup { + pinmux = ; + bias-pull-up; + }; + + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux = ; + drive-strength = <4>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <4>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux = ; + input-enable; + bias-pull-up = ; + }; + }; + + rv3028_pins: rv3028-pins { + pins-irq { + pinmux = ; + bias-pull-up = ; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + pcie_default_pins: pcie-default-pins { + pins { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + ts_dsi0_goodix_pins: ts-dsi0-goodix-pins { + pins-irq { + pinmux = ; + bias-pull-up = ; + input-enable; + }; + + pins-reset { + pinmux = ; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + usbotg_pins: usbotg-pins { + pins-iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux = ; + input-enable; + }; + + pins-vbus { + pinmux = ; + output-high; + }; + }; + + usb1_hub_pins: usb1-hub-pins { + pins { + pinmux = ; + output-low; + }; + }; + + usb1_pins: usb1-pins { + pins { + pinmux = ; + input-enable; + }; + }; + + usb2_eth_pins: usb2-eth-pins { + pins { + pinmux = ; + output-low; + }; + }; + + wifi_pwrseq_pins: wifi-pwrseq-pins { + pins { + pinmux = ; + output-low; + }; + }; + + watchdog_pins: watchdog-pins { + pins { + pinmux = ; + bias-pull-up; + }; + }; +}; From fe96ff075f960abb9dd1c99c4c4e7f79c4e10172 Mon Sep 17 00:00:00 2001 From: Gary Bisson Date: Wed, 3 Dec 2025 22:20:41 +0100 Subject: [PATCH 425/757] arm64: dts: mediatek: add device tree for Tungsten 700 board Add device tree to support Ezurio Tungsten 700 (MT8390) SMARC SOM [1] + Universal SMARC carrier board [2]. It includes support for the MIPI-DSI BD070LIC3 display which uses the Tianma TM070JDHG30 panel + TI SN65DSI84 MIPI-DSI to LVDS bridge [3]. [1] https://www.ezurio.com/product/tungsten700-smarc [2] https://www.ezurio.com/system-on-module/accessories/universal-smarc-carrier [3] https://www.ezurio.com/product/bd070lic3-7-touchscreen-display Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Gary Bisson Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8390-tungsten-smarc.dts | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 9e26d828d796..387faa9c2a09 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -164,6 +164,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk-ufs.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-tungsten-smarc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts new file mode 100644 index 000000000000..7580f9e2f20d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-tungsten-smarc.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Ezurio LLC + * Author: Gary Bisson + */ +/dts-v1/; +#include "mt8188.dtsi" +#include "mt8390-tungsten-smarc.dtsi" + +/ { + model = "Ezurio Tungsten700 SMARC (MT8390)"; + compatible = "ezurio,mt8390-tungsten-smarc", "mediatek,mt8390", + "mediatek,mt8188"; +}; + +&cpu4 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu5 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; From 256d3e55d8ce91eb0b22f7101c02e446cd3dd8f1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 13 Nov 2025 16:13:52 +0100 Subject: [PATCH 426/757] ARM: dts: stm32: reorder nodes for stm32429i-eval Reorder nodes by alphabetical order. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-1-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32429i-eval.dts | 56 ++++++++++++------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts index afa417b34b25..6ce8d7e5565a 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -82,27 +82,6 @@ dma-ranges = <0xc0000000 0x0 0x10000000>; }; - vdda: regulator-vdda { - compatible = "regulator-fixed"; - regulator-name = "vdda"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vref: regulator-vref { - compatible = "regulator-fixed"; - regulator-name = "vref"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - vdd_panel: vdd-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - leds { compatible = "gpio-leds"; led-green { @@ -135,11 +114,11 @@ }; }; - usbotg_hs_phy: usbphy { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; - clock-names = "main_clk"; + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; panel_rgb: panel-rgb { @@ -153,9 +132,30 @@ }; }; - mmc_vcard: mmc_vcard { + vdda: regulator-vdda { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vdda"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vref: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "vref"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usbotg_hs_phy: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + vdd_panel: vdd-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; From 929dc5b3e06c54f1d19b01c93042174d0e741b99 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:40 -0600 Subject: [PATCH 427/757] ARM: dts: broadcom: bcm2711: Fix 'simple-bus' node names Fix 'simple-bus' node names to follow the defined pattern. Nodes with 'reg' or 'ranges' addresses should also have a unit-address. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-1-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/broadcom/bcm2711.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi index c06d9f5e53c8..5e3b4bb39396 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -415,7 +415,7 @@ * The firmware will find whether the emmc2bus alias is defined, and if * so, it'll edit the dma-ranges property below accordingly. */ - emmc2bus: emmc2bus { + emmc2bus: emmc2-bus@fe000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; @@ -542,7 +542,7 @@ }; }; - scb { + scb-bus@fc000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; From 05f790b3d2359a1e2dcfd157268492e63ae41845 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sat, 27 Sep 2025 08:56:31 +0100 Subject: [PATCH 428/757] arm64: dts: broadcom: bcm2712: Enable RNG The RNG is the same IP as in the bcm2711 so add the device tree block to enable the device. Signed-off-by: Peter Robinson Reviewed-by: Stefan Wahren Link: https://lore.kernel.org/r/20250927075643.716179-1-pbrobinson@gmail.com Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 205b87f557d6..7d4f5b00432c 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -283,6 +283,12 @@ reg = <0x7d510700 0x20>; }; + random: rng@7d208000 { + compatible = "brcm,bcm2711-rng200"; + reg = <0x7d208000 0x28>; + status = "okay"; + }; + interrupt-controller@7d517000 { compatible = "brcm,bcm7271-l2-intc"; reg = <0x7d517000 0x10>; From 87a6c3c03d46d78719672332ffad00f520231dbc Mon Sep 17 00:00:00 2001 From: Stanimir Varbanov Date: Fri, 31 Oct 2025 20:33:09 +0200 Subject: [PATCH 429/757] arm64: dts: broadcom: bcm2712: Add watchdog DT node Add watchdog device-tree node for bcm2712 SoC. Signed-off-by: Stanimir Varbanov Link: https://lore.kernel.org/r/20251031183309.1163384-5-svarbanov@suse.de Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi index 7d4f5b00432c..d57a9b1bff70 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -250,6 +250,15 @@ status = "disabled"; }; + pm: watchdog@7d200000 { + compatible = "brcm,bcm2712-pm", "brcm,bcm2835-pm-wdt"; + reg = <0x7d200000 0x604>; + reg-names = "pm"; + #power-domain-cells = <1>; + #reset-cells = <1>; + system-power-controller; + }; + pinctrl: pinctrl@7d504100 { compatible = "brcm,bcm2712c0-pinctrl"; reg = <0x7d504100 0x30>; From 591cf7900da577a9ac7777b74b697bf3d61687d0 Mon Sep 17 00:00:00 2001 From: Nick Chan Date: Wed, 31 Dec 2025 02:30:42 +0800 Subject: [PATCH 430/757] arm64: dts: apple: s8001: Add DWI backlight for J98a, J99a iPad Pro (12.9-inch) uses DWI backlight, while the 9.7-inch model does not. Add DWI backlight node for s8001 and enable it for J98a and J99a. Signed-off-by: Nick Chan Link: https://patch.msgid.link/20251231-b4-j98a-j99a-dwi-bl-v1-1-24793c2b99fc@gmail.com Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi | 4 ++++ arch/arm64/boot/dts/apple/s8001.dtsi | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi b/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi index e66a4c1c138f..67633c56a723 100644 --- a/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi +++ b/arch/arm64/boot/dts/apple/s8001-j98a-j99a.dtsi @@ -9,6 +9,10 @@ * Copyright (c) 2024, Nick Chan */ +&dwi_bl { + status = "okay"; +}; + &ps_dcs4 { apple,always-on; /* LPDDR4 interface */ }; diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/apple/s8001.dtsi index b5b00dca6ffa..209c7dd19b7c 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -209,6 +209,13 @@ power-domains = <&ps_aic>; }; + dwi_bl: backlight@20e200080 { + compatible = "apple,s8000-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200080 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; + }; + pinctrl_ap: pinctrl@20f100000 { compatible = "apple,s8000-pinctrl", "apple,pinctrl"; reg = <0x2 0x0f100000 0x0 0x100000>; From 165287f761aaf7f5c2d4d8b19343569b6a26f8bf Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 8 Jan 2026 18:05:48 +0100 Subject: [PATCH 431/757] arm64: dts: qcom: qcm2290: Add pin configuration for mclks Add pinctrl configuration for the four available camera master clocks. Signed-off-by: Loic Poulain Reviewed-by: Konrad Dybcio Reviewed-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20260108170550.359968-2-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 992a157c571f..7815ece261ea 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -604,6 +604,34 @@ bias-disable; }; + mclk0_default: mclk0-default-state { + pins = "gpio20"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + mclk1_default: mclk1-default-state { + pins = "gpio21"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + mclk2_default: mclk2-default-state { + pins = "gpio27"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + + mclk3_default: mclk3-default-state { + pins = "gpio28"; + function = "cam_mclk"; + drive-strength = <16>; + bias-disable; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; From 141f384413fbeada38f3fa46e2beed9bf8c0f6fe Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 8 Jan 2026 18:05:49 +0100 Subject: [PATCH 432/757] arm64: dts: qcom: qrb2210-rb1: Add PM8008 node The PM8008 device is a dedicated camera PMIC integrating all the necessary camera power management features. Signed-off-by: Loic Poulain Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260108170550.359968-3-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 75 ++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index 1b9ca957a94b..9814ac4896c5 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -267,6 +267,81 @@ firmware-name = "qcom/qcm2290/a702_zap.mbn"; }; +&i2c1 { + clock-frequency = <400000>; + + status = "okay"; + + pm8008: pmic@8 { + compatible = "qcom,pm8008"; + reg = <0x8>; + + interrupts-extended = <&tlmm 25 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply = <&pm4125_s3>; + vdd-l3-l4-supply = <&vph_pwr>; + vdd-l5-supply = <&vph_pwr>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-supply = <&vph_pwr>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells = <2>; + + #thermal-sensor-cells = <0>; + + status = "disabled"; + + regulators { + vreg_l1p: ldo1 { + regulator-name = "vreg_l1p"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name = "vreg_l2p"; + regulator-min-microvolt = <528000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l3p: ldo3 { + regulator-name = "vreg_l3p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l4p: ldo4 { + regulator-name = "vreg_l4p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3404000>; + }; + + vreg_l5p: ldo5 { + regulator-name = "vreg_l5p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l6p: ldo6 { + regulator-name = "vreg_l6p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; + + vreg_l7p: ldo7 { + regulator-name = "vreg_l7p"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <3400000>; + }; + }; + }; +}; + &i2c2_gpio { clock-frequency = <400000>; status = "okay"; From 89daf7b9a8205d58ea934e3a51a4f1f892ab0ed6 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 8 Jan 2026 18:05:50 +0100 Subject: [PATCH 433/757] arm64: dts: qcom: qrb2210-rb1: Add overlay for vision mezzanine This initial version includes support for OV9282 camera sensor. Signed-off-by: Loic Poulain Reviewed-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20260108170550.359968-4-loic.poulain@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 5 ++ .../qcom/qrb2210-rb1-vision-mezzanine.dtso | 66 +++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 0ccd6ec16dfb..a5d6f451f85c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -149,6 +149,11 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-arduino-imola.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb + +qrb2210-rb1-vision-mezzanine-dtbs := qrb2210-rb1.dtb qrb2210-rb1-vision-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1-vision-mezzanine.dtb + dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso new file mode 100644 index 000000000000..c314cd6dd484 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1-vision-mezzanine.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&pm8008 { + status = "okay"; +}; + +&camss { + status = "okay"; + + vdd-csiphy-1p2-supply = <&pm4125_l5>; + vdd-csiphy-1p8-supply = <&pm4125_l13>; + + ports { + port@0 { + csiphy0_ep: endpoint { + data-lanes = <0 1>; + remote-endpoint = <&ov9282_ep>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + /* Vision Mezzanine DIP3-1 must be ON (Selects camera CAM0A&B) */ + camera@60 { + compatible = "ovti,ov9282"; + reg = <0x60>; + + /* Reset is active-low, but driver applies inverted reset logic */ + reset-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&mclk3_default>; + pinctrl-names = "default"; + + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + assigned-clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + + avdd-supply = <&vreg_l3p>; + dvdd-supply = <&vreg_l1p>; + dovdd-supply = <&vreg_l7p>; + + port { + ov9282_ep: endpoint { + link-frequencies = /bits/ 64 <400000000>; + data-lanes = <1 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; From d9802af199ad4e9a498879e4cb73763bddd4ae76 Mon Sep 17 00:00:00 2001 From: Horatiu Vultur Date: Mon, 8 Dec 2025 09:35:44 +0100 Subject: [PATCH 434/757] dt-bindings: arm: at91: add lan966 pcb8385 board Add documentation for Microchip LAN9668 PCB8385 Acked-by: Rob Herring (Arm) Reviewed-by: Claudiu Beznea Signed-off-by: Horatiu Vultur Link: https://lore.kernel.org/r/20251208083545.3642168-2-horatiu.vultur@microchip.com Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 3a34b7a2e8d4..68d306d17c2a 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -235,9 +235,11 @@ properties: - const: microchip,lan9662 - const: microchip,lan966 - - description: Microchip LAN9668 PCB8290 Evaluation Board. + - description: Microchip LAN9668 Evaluation Board. items: - - const: microchip,lan9668-pcb8290 + - enum: + - microchip,lan9668-pcb8290 + - microchip,lan9668-pcb8385 - const: microchip,lan9668 - const: microchip,lan966 From a8e30c9d856ddebad75abaec55c019a7a85b16da Mon Sep 17 00:00:00 2001 From: Horatiu Vultur Date: Mon, 8 Dec 2025 09:35:45 +0100 Subject: [PATCH 435/757] ARM: dts: Add support for pcb8385 Add basic support for pcb8385 [1]. It is a modular board which allows to add different daughter cards on which there are different PHYs. This adds support for UART, LEDs and I2C. [1] https://www.microchip.com/en-us/development-tool/ev83e85a Signed-off-by: Horatiu Vultur Link: https://lore.kernel.org/r/20251208083545.3642168-3-horatiu.vultur@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/microchip/Makefile | 3 +- .../boot/dts/microchip/lan966x-pcb8385.dts | 131 ++++++++++++++++++ 2 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/microchip/lan966x-pcb8385.dts diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index 79cd38fdc7da..08986c24a470 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -102,4 +102,5 @@ dtb-$(CONFIG_SOC_LAN966) += \ lan966x-kontron-kswitch-d10-mmt-8g.dtb \ lan966x-pcb8290.dtb \ lan966x-pcb8291.dtb \ - lan966x-pcb8309.dtb + lan966x-pcb8309.dtb \ + lan966x-pcb8385.dtb diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8385.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8385.dts new file mode 100644 index 000000000000..d18969275efe --- /dev/null +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8385.dts @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x-pcb8385.dts - Device Tree file for PCB8385 + */ +/dts-v1/; + +#include "lan966x.dtsi" +#include "dt-bindings/phy/phy-lan966x-serdes.h" + +/ { + model = "Microchip EVB - LAN9668"; + compatible = "microchip,lan9668-pcb8385", "microchip,lan9668", "microchip,lan966"; + + aliases { + serial0 = &usart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 59 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; + + leds { + compatible = "gpio-leds"; + + led-p1-green { + label = "cu0:green"; + gpios = <&sgpio_out 2 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-p1-yellow { + label = "cu0:yellow"; + gpios = <&sgpio_out 2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-p2-green { + label = "cu1:green"; + gpios = <&sgpio_out 3 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-p2-yellow { + label = "cu1:yellow"; + gpios = <&sgpio_out 3 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&aes { + status = "reserved"; /* Reserved by secure OS */ +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&gpio { + fc0_b_pins: fc0-b-pins { + /* SCL, SDA */ + pins = "GPIO_25", "GPIO_26"; + function = "fc0_b"; + }; + + fc3_b_pins: fc3-b-pins { + /* RX, TX */ + pins = "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + sgpio_a_pins: sgpio-a-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35"; + function = "sgpio_a"; + }; +}; + +&i2c0 { + pinctrl-0 = <&fc0_b_pins>; + pinctrl-names = "default"; + dmas = <0>, <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; + + eeprom@54 { + compatible = "atmel,24c01"; + reg = <0x54>; + }; + + eeprom@55 { + compatible = "atmel,24c01"; + reg = <0x55>; + }; +}; + +&sgpio { + pinctrl-0 = <&sgpio_a_pins>; + pinctrl-names = "default"; + microchip,sgpio-port-ranges = <0 3>; + status = "okay"; + + gpio@0 { + ngpios = <64>; + }; + gpio@1 { + ngpios = <64>; + }; +}; + +&usart3 { + pinctrl-0 = <&fc3_b_pins>; + pinctrl-names = "default"; + status = "okay"; +}; From d2bfa3f72d4762f5e531bfe29781d9a62fea5847 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 24 Dec 2025 06:52:05 +0200 Subject: [PATCH 436/757] ARM: dts: lpc32xx: Update spi clock properties PL022 binding require two clocks to be defined but NXP LPC32xx platform doesn't comply with the bindings and define only one clock i.e apb_pclk. Update SPI clocks and clocks-names property by adding appropriate clock reference to make it compliant with the bindings. Noteworthy, strictly speaking the change tackles DT ABI by changing the order in the list of clock-names property values, however this level of impact is considered as acceptable. Cc: Vladimir Zapolskiy Signed-off-by: Kuldeep Singh [vzapolskiy: rebased and minor update to the commit message] Reviewed-by: Frank Li Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index e780451fd335..206c66bdfe41 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -172,8 +172,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x20084000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP0>; - clock-names = "apb_pclk"; + clocks = <&clk LPC32XX_CLK_SSP0>, <&clk LPC32XX_CLK_SSP0>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -196,8 +196,8 @@ compatible = "arm,pl022", "arm,primecell"; reg = <0x2008c000 0x1000>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk LPC32XX_CLK_SSP1>; - clock-names = "apb_pclk"; + clocks = <&clk LPC32XX_CLK_SSP1>, <&clk LPC32XX_CLK_SSP1>; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; From 1594e575924c614bb376b4f0b749cef8e3fa4e29 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 24 Dec 2025 18:58:44 +0200 Subject: [PATCH 437/757] ARM: dts: lpc32xx: change NAND controllers node names The device tree node name of NAND controllers shall be 'nand-controller', while 'flash' name is the name of NAND chip device tree nodes. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 206c66bdfe41..3d5a59b2886c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -62,14 +62,14 @@ /* * Enable either SLC or MLC */ - slc: flash@20020000 { + slc: nand-controller@20020000 { compatible = "nxp,lpc3220-slc"; reg = <0x20020000 0x1000>; clocks = <&clk LPC32XX_CLK_SLC>; status = "disabled"; }; - mlc: flash@200a8000 { + mlc: nand-controller@200a8000 { compatible = "nxp,lpc3220-mlc"; reg = <0x200a8000 0x11000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; From d8bb9ef26e9c223c2113d08d89c2f912b22d518a Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 24 Dec 2025 18:58:45 +0200 Subject: [PATCH 438/757] ARM: dts: lpc32xx: describe FLASH_INT of SLC NAND controller SLC and MLC NAND flash controllers fire the muxed interrupt FLASH_INT to the SoC, add the interrupt property to the SLC device tree node. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 3d5a59b2886c..5ddaea8c481a 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -65,6 +65,7 @@ slc: nand-controller@20020000 { compatible = "nxp,lpc3220-slc"; reg = <0x20020000 0x1000>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SLC>; status = "disabled"; }; From 8754c6e19b902416816057bcf38af8af52a91103 Mon Sep 17 00:00:00 2001 From: Piotr Wojtaszczyk Date: Wed, 31 Dec 2025 23:57:51 +0200 Subject: [PATCH 439/757] ARM: dts: lpc32xx: Use syscon for system control block The clock controller is a part of NXP LPC32xx system control block (SCB), and SCB provides a number of controllers apart of the clock controller. [vzapolskiy]: 1. kept a simple comment, 2. renamed SoC specific compatible to 'nxp,lpc3220-scb' due to the SoC UM, 3. changed size in 'ranges', since it should cover more SCB functions, 4. updated the commit message. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-5-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 5ddaea8c481a..e44917324aed 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -308,17 +308,17 @@ ranges = <0x20000000 0x20000000 0x30000000>; /* System Control Block */ - scb { - compatible = "simple-bus"; - ranges = <0x0 0x40004000 0x00001000>; + syscon@40004000 { + compatible = "nxp,lpc3220-scb", "syscon", "simple-mfd"; + reg = <0x40004000 0x1000>; #address-cells = <1>; #size-cells = <1>; + ranges = <0 0x40004000 0x1000>; clk: clock-controller@0 { compatible = "nxp,lpc3220-clk"; reg = <0x00 0x114>; #clock-cells = <1>; - clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; }; From 6b7e0f1c2a3eb66f561fdc5643752b190692e5cd Mon Sep 17 00:00:00 2001 From: Piotr Wojtaszczyk Date: Wed, 31 Dec 2025 23:57:52 +0200 Subject: [PATCH 440/757] ARM: dts: lpc32xx: Add missing DMA properties Add properties declared in the new DT binding nxp,lpc3220-dmamux.yaml and corresponding phandles. [vzapolskiy]: 1. rebased the change, 2. dmamux unit address shall be 0x78 instead of 0x7c, 3. removed unsupported 'dmas' properties from sd, ssp0, ssp1 and HS UARTs, 4. more non-functional updates by reordering properies, 5. minor updates to the commit message. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-6-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index e44917324aed..58d21f42ea4c 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -67,6 +67,8 @@ reg = <0x20020000 0x1000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SLC>; + dmas = <&dma 1 1>; + dma-names = "rx-tx"; status = "disabled"; }; @@ -75,6 +77,8 @@ reg = <0x200a8000 0x11000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_MLC>; + dmas = <&dma 12 1>; + dma-names = "rx-tx"; status = "disabled"; }; @@ -84,6 +88,12 @@ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_DMA>; clock-names = "apb_pclk"; + dma-channels = <8>; + dma-requests = <16>; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; #dma-cells = <2>; }; @@ -184,6 +194,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI1>; + dmas = <&dmamux 11 1 0>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -208,6 +220,8 @@ compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; clocks = <&clk LPC32XX_CLK_SPI2>; + dmas = <&dmamux 3 1 0>; + dma-names = "rx-tx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -216,6 +230,8 @@ i2s0: i2s@20094000 { compatible = "nxp,lpc3220-i2s"; reg = <0x20094000 0x1000>; + dmas = <&dma 0 1>, <&dma 13 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -232,6 +248,8 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009c000 0x1000>; + dmas = <&dma 2 1>, <&dmamux 10 1 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -322,6 +340,13 @@ clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; }; + + dmamux: dma-router@78 { + compatible = "nxp,lpc3220-dmamux"; + reg = <0x78 0x8>; + dma-masters = <&dma>; + #dma-cells = <3>; + }; }; mic: interrupt-controller@40008000 { From 14c877ddffe9d69da2c92eec390d2d0eadc8c1c6 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Wed, 31 Dec 2025 23:57:53 +0200 Subject: [PATCH 441/757] ARM: dts: lpc32xx: Declare the second AHB master support on PL080 DMA controller Add 'lli-bus-interface-ahb2' and 'mem-bus-interface-ahb2' properties to the PL080 DMA controller device tree node, tested with dmatest utility. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 58d21f42ea4c..b9a0d7dae4ed 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -91,7 +91,9 @@ dma-channels = <8>; dma-requests = <16>; lli-bus-interface-ahb1; + lli-bus-interface-ahb2; mem-bus-interface-ahb1; + mem-bus-interface-ahb2; memcpy-burst-size = <256>; memcpy-bus-width = <32>; #dma-cells = <2>; From c23ac0f9325ee5b3755ff9b7c3143fed7bbaebd8 Mon Sep 17 00:00:00 2001 From: Piotr Wojtaszczyk Date: Wed, 31 Dec 2025 23:57:54 +0200 Subject: [PATCH 442/757] ARM: dts: lpc32xx: Add missing properties to I2S device tree nodes Add NXP LPC32xx I2S controller device tree properties in accordance to nxp,lpc3220-i2s.yaml. Link to the original change: * https://lore.kernel.org/linux-arm-kernel/20240627150046.258795-7-piotr.wojtaszczyk@timesys.com/ Signed-off-by: Piotr Wojtaszczyk [vzapolskiy: changes to the commit message] Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index b9a0d7dae4ed..e89ef62f9fbb 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -232,8 +232,11 @@ i2s0: i2s@20094000 { compatible = "nxp,lpc3220-i2s"; reg = <0x20094000 0x1000>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_I2S0>; dmas = <&dma 0 1>, <&dma 13 1>; dma-names = "rx", "tx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -250,8 +253,11 @@ i2s1: i2s@2009c000 { compatible = "nxp,lpc3220-i2s"; reg = <0x2009c000 0x1000>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LPC32XX_CLK_I2S1>; dmas = <&dma 2 1>, <&dmamux 10 1 1>; dma-names = "rx", "tx"; + #sound-dai-cells = <0>; status = "disabled"; }; From 98aa86525051bbb974818cd27f9a6fbaf255975b Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 26 Nov 2025 15:03:53 +0200 Subject: [PATCH 443/757] arm64: dts: renesas: r9a09g077: Add OPP table Add OPP table for RZ/T2H SoC. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251126130356.2768625-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 2db5f5e94f7c..20c28eed9d0e 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -14,6 +14,17 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +35,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +45,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +55,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +65,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From ffcc240e3680e77d36c99026f5da81553d559246 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 26 Nov 2025 15:03:54 +0200 Subject: [PATCH 444/757] arm64: dts: renesas: r9a09g087: Add OPP table Add OPP table for RZ/N2H SoC. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251126130356.2768625-8-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index f3225694b4cb..a6a558e0ccd9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -14,6 +14,17 @@ #size-cells = <2>; interrupt-parent = <&gic>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -24,6 +35,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C0>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -32,6 +45,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C1>; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@200 { @@ -40,6 +55,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C2>; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@300 { @@ -48,6 +65,8 @@ device_type = "cpu"; next-level-cache = <&L3_CA55>; enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C3>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { From aea73cb10ec5bf8e24ff688eba8aeb9c7d1b4cd0 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 26 Nov 2025 15:03:55 +0200 Subject: [PATCH 445/757] arm64: dts: renesas: r9a09g077: Add TSU and thermal zones support The Renesas RZ/T2H (R9A09G077) SoC includes a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. The TSU loads calibration data via SMC SIP. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251126130356.2768625-9-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 20c28eed9d0e..fa3e667e77e0 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -36,6 +36,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -46,6 +47,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -56,6 +58,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -66,6 +69,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -316,6 +320,17 @@ status = "disabled"; }; + tsu: thermal@80086000 { + compatible = "renesas,r9a09g077-tsu"; + reg = <0 0x80086000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 307>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; @@ -1194,6 +1209,37 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 1>, <&cpu1 0 1>, + <&cpu2 0 1>, <&cpu3 0 1>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From 5c4c34ea8dc02350fad11bc5423ca065595bbd54 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Wed, 26 Nov 2025 15:03:56 +0200 Subject: [PATCH 446/757] arm64: dts: renesas: r9a09g087: Add TSU and thermal zones support The Renesas RZ/N2H (R9A09G087) SoC includes a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. The TSU loads calibration data via SMC SIP. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251126130356.2768625-10-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index a6a558e0ccd9..804970bf745f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -36,6 +36,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C0>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -46,6 +47,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C1>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -56,6 +58,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C2>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -66,6 +69,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C3>; + #cooling-cells = <2>; operating-points-v2 = <&cluster0_opp>; }; @@ -316,6 +320,17 @@ status = "disabled"; }; + tsu: thermal@80086000 { + compatible = "renesas,r9a09g087-tsu", "renesas,r9a09g077-tsu"; + reg = <0 0x80086000 0 0x1000>; + interrupts = , + ; + interrupt-names = "adi", "adcmpi"; + clocks = <&cpg CPG_MOD 307>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + }; + i2c0: i2c@80088000 { compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; reg = <0 0x80088000 0 0x400>; @@ -1197,6 +1212,37 @@ snps,blen = <16 8 4 0 0 0 0>; }; + thermal-zones { + cpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsu>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 1>, <&cpu1 0 1>, + <&cpu2 0 1>, <&cpu3 0 1>; + contribution = <1024>; + }; + }; + + trips { + target: trip-point { + temperature = <95000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor_crit: sensor-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , From a0c0b921b63902b3993bf60bd0ab8c3041a23481 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 5 Dec 2025 17:02:31 +0200 Subject: [PATCH 447/757] arm64: dts: renesas: r9a09g077: Add GPIO IRQ support The Renesas RZ/T2H (R9A09G077) SoC includes pins which can be routed via the ICU to generate interrupts. Add support for using the pin controller as an interrupt chip. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251205150234.2958140-6-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index fa3e667e77e0..27a260ccda04 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -1035,6 +1035,9 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 288>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; }; From 7c9cf4eb9d600a51e4770e6ab876e123dd6b5165 Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 5 Dec 2025 17:02:32 +0200 Subject: [PATCH 448/757] arm64: dts: renesas: r9a09g087: Add GPIO IRQ support The Renesas RZ/N2H (R9A09G087) SoC includes pins which can be routed via the ICU to generate interrupts. Add support for using the pin controller as an interrupt chip. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251205150234.2958140-7-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index 804970bf745f..bb46a936eb4d 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -1038,6 +1038,9 @@ gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pinctrl 0 0 280>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&icu>; power-domains = <&cpg>; }; From fcec728e1599f45f7956c1f7694706cf77cdf29e Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 5 Dec 2025 17:02:33 +0200 Subject: [PATCH 449/757] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keys The Renesas RZ/T2H Evaluation Kit has three user buttons connected to GPIOs that can be used as input keys. Add support for them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251205150234.2958140-8-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index d1474f1bd523..c8e983b43675 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include + #include "r9a09g077m44.dtsi" /* @@ -60,6 +62,37 @@ model = "Renesas RZ/T2H EVK Board based on r9a09g077m44"; compatible = "renesas,rzt2h-evk", "renesas,r9a09g077m44", "renesas,r9a09g077"; + keys { + compatible = "gpio-keys"; + +#if (!SD1_MICRO_SD) + /* SW2-3: OFF */ + key-1 { + interrupts-extended = <&pinctrl RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW9"; + wakeup-source; + debounce-interval = <20>; + }; +#endif + + key-2 { + interrupts-extended = <&pinctrl RZT2H_GPIO(0, 3) IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW10"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts-extended = <&pinctrl RZT2H_GPIO(8, 7) IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW11"; + wakeup-source; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; From 2c089ad703527f5ae08c7c362a9dfe5a660ab16d Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Fri, 5 Dec 2025 17:02:34 +0200 Subject: [PATCH 450/757] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add GPIO keys The Renesas RZ/N2H Evaluation Kit has three user buttons connected to GPIOs that can be used as input keys. Add support for them. Signed-off-by: Cosmin Tanislav Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251205150234.2958140-9-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index eaf73868783b..252f1c21ff90 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include + #include "r9a09g087m44.dtsi" /* @@ -77,6 +79,34 @@ model = "Renesas RZ/N2H EVK Board based on r9a09g087m44"; compatible = "renesas,rzn2h-evk", "renesas,r9a09g087m44", "renesas,r9a09g087"; + keys { + compatible = "gpio-keys"; + + key-1 { + interrupts-extended = <&pinctrl RZT2H_GPIO(18, 2) IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + interrupts-extended = <&pinctrl RZT2H_GPIO(0, 4) IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts-extended = <&pinctrl RZT2H_GPIO(18, 7) IRQ_TYPE_EDGE_FALLING>; + linux,code = ; + label = "SW4"; + wakeup-source; + debounce-interval = <20>; + }; + }; + leds { compatible = "gpio-leds"; From cda350fbd275acae7cf2edb04b4691c2b9af4fb2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 22 Dec 2025 16:42:37 +0000 Subject: [PATCH 451/757] arm64: dts: renesas: r9a09g056: Add RSCI nodes Add RSCI nodes to RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251222164238.156985-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 220 +++++++++++++++++++++ 1 file changed, 220 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index d942ac1f7865..fa425d9273a8 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -757,6 +757,226 @@ status = "disabled"; }; + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g056-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From 03301175a6febb2faf7984e7a2396c345d8774a0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 22 Dec 2025 16:42:38 +0000 Subject: [PATCH 452/757] arm64: dts: renesas: r9a09g057: Add RSCI nodes Add RSCI nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251222164238.156985-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 220 +++++++++++++++++++++ 1 file changed, 220 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index a36961804494..77f986a957ba 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -753,6 +753,226 @@ status = "disabled"; }; + rsci0: serial@12800c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12800c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, + <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, + <&cpg CPG_MOD 0x5f>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x81>, <&cpg 0x82>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci1: serial@12801000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, + <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, + <&cpg CPG_MOD 0x64>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x83>, <&cpg 0x84>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci2: serial@12801400 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, + <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, + <&cpg CPG_MOD 0x69>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x85>, <&cpg 0x86>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci3: serial@12801800 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, + <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, + <&cpg CPG_MOD 0x6e>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x87>, <&cpg 0x88>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci4: serial@12801c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12801c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, + <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, + <&cpg CPG_MOD 0x73>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x89>, <&cpg 0x8a>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci5: serial@12802000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, + <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, + <&cpg CPG_MOD 0x78>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8b>, <&cpg 0x8c>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci6: serial@12802400 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, + <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, + <&cpg CPG_MOD 0x7d>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8d>, <&cpg 0x8e>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci7: serial@12802800 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, + <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, + <&cpg CPG_MOD 0x82>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x8f>, <&cpg 0x90>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci8: serial@12802c00 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12802c00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, + <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, + <&cpg CPG_MOD 0x87>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x91>, <&cpg 0x92>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + + rsci9: serial@12803000 { + compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; + reg = <0 0x12803000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei", + "aed", "bfd"; + clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, + <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, + <&cpg CPG_MOD 0x8c>; + clock-names = "pclk", "tclk", "tclk_div4", + "tclk_div16", "tclk_div64"; + power-domains = <&cpg>; + resets = <&cpg 0x93>, <&cpg 0x94>; + reset-names = "presetn", "tresetn"; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; From ff108a26c91631bef465702d04bcd8d910af7f0e Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 24 Dec 2025 17:51:59 +0000 Subject: [PATCH 453/757] arm64: dts: renesas: r9a09g077: Add CANFD node Add support for the CANFD controller on the Renesas RZ/T2H Soc. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251224175204.3400062-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi index 27a260ccda04..14d7fb6f8952 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi @@ -260,6 +260,37 @@ status = "disabled"; }; + canfd: can@80040000 { + compatible = "renesas,r9a09g077-canfd"; + reg = <0 0x80040000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R9A09G077_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G077_PCLKCAN>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A09G077_PCLKCAN>; + assigned-clock-rates = <80000000>; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, From 3fcf1e255e0d97b42e7d003596ae987fb193bcf0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 24 Dec 2025 17:52:00 +0000 Subject: [PATCH 454/757] arm64: dts: renesas: r9a09g087: Add CANFD node Add support for the CANFD controller on the Renesas RZ/N2H Soc. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251224175204.3400062-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi index bb46a936eb4d..4a1339561332 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi @@ -260,6 +260,37 @@ status = "disabled"; }; + canfd: can@80040000 { + compatible = "renesas,r9a09g087-canfd", "renesas,r9a09g077-canfd"; + reg = <0 0x80040000 0 0x20000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, + <&cpg CPG_CORE R9A09G087_PCLKCAN>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A09G087_PCLKCAN>; + assigned-clock-rates = <80000000>; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + }; + wdt0: watchdog@80082000 { compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; reg = <0 0x80082000 0 0x400>, From d3112a820ccfe9a39c171fe3bc313794f1325711 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 24 Dec 2025 17:52:01 +0000 Subject: [PATCH 455/757] arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable CANFD Enable CANFD channel 0, which is available on the CN55 connector. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251224175204.3400062-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index c8e983b43675..eedea1ce57e6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -171,6 +171,16 @@ }; }; +&canfd { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -199,6 +209,17 @@ }; &pinctrl { + /* + * CAN0 Pin Configuration: + * + * SW7[1] OFF; SW7[2] ON - Use P24_4 as CANTX0. + * SW7[3] OFF; SW7[4] ON - Use P24_3 as CANRX0. + */ + can0_pins: can0-pins { + pinmux = , /* CANRX0 */ + ; /* CANTX0 */ + }; + /* * GMAC2 Pin Configuration: * From 3e6c313f4f996ce73b80873b8172610003e90f35 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 24 Dec 2025 17:52:02 +0000 Subject: [PATCH 456/757] arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Enable CANFD Enable CANFD channel 1, which is available on the CN35 connector. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251224175204.3400062-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 252f1c21ff90..5d1da4de8af6 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -29,6 +29,13 @@ #define SD0_EMMC 1 #define SD0_SD (!SD0_EMMC) +/* + * To enable CANFD interface disable both eMMC and SD card on SDHI0 by + * setting SD0_EMMC and SD0_SD macros to 0 as pins P12_0 and P12_1 + * will be used for CANFD interface. + */ +#define CANFD_ENABLE (!SD0_EMMC && !SD0_SD) + /* * P17_4 = SD1_CD; DSW5[3] = ON; DSW19[1] = OFF; DSW19[2] = ON * P08_6 = SD1_IOVS; DSW5[3] = ON @@ -203,6 +210,18 @@ }; }; +#if CANFD_ENABLE +&canfd { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel1 { + status = "okay"; + }; +}; +#endif + #if I2C0 &i2c0 { pinctrl-0 = <&i2c0_pins>; @@ -239,6 +258,16 @@ }; &pinctrl { + /* + * CAN1 Pin Configuration: + * + * DSW5[1] ON; DSW5[2] OFF - Use P12_0 and P12_1 for CAN1 interface. + */ + can1_pins: can1-pins { + pinmux = , /* CANRX1 */ + ; /* CANTX1 */ + }; + /* * GMAC2 Pin Configuration: * From edd0ce2e33ce2dae0c31e3b39108d0c327b8fb2b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 24 Dec 2025 17:52:03 +0000 Subject: [PATCH 457/757] arm64: dts: renesas: r9a09g056: Add CANFD node Add CANFD node to RZ/V2N ("R9A09G056") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251224175204.3400062-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi index fa425d9273a8..9fb15ca24984 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -694,6 +694,66 @@ status = "disabled"; }; + canfd: can@12440000 { + compatible = "renesas,r9a09g056-canfd", "renesas,r9a09g047-canfd"; + reg = <0 0x12440000 0 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx", + "ch2_err", "ch2_rec", "ch2_trx", + "ch3_err", "ch3_rec", "ch3_trx", + "ch4_err", "ch4_rec", "ch4_trx", + "ch5_err", "ch5_rec", "ch5_trx"; + clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, + <&cpg CPG_MOD 0x9e>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_MOD 0x9e>; + assigned-clock-rates = <80000000>; + resets = <&cpg 0xa1>, <&cpg 0xa2>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + channel2 { + status = "disabled"; + }; + channel3 { + status = "disabled"; + }; + channel4 { + status = "disabled"; + }; + channel5 { + status = "disabled"; + }; + }; + rspi0: spi@12800000 { compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi"; reg = <0x0 0x12800000 0x0 0x400>; From 688fded2fc74b0539cd848b775418200c52a1fc2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 24 Dec 2025 17:52:04 +0000 Subject: [PATCH 458/757] arm64: dts: renesas: r9a09g057: Add CANFD node Add CANFD node to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251224175204.3400062-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 77f986a957ba..80cba9fcfe7b 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -690,6 +690,66 @@ status = "disabled"; }; + canfd: can@12440000 { + compatible = "renesas,r9a09g057-canfd", "renesas,r9a09g047-canfd"; + reg = <0 0x12440000 0 0x40000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx", + "ch2_err", "ch2_rec", "ch2_trx", + "ch3_err", "ch3_rec", "ch3_trx", + "ch4_err", "ch4_rec", "ch4_trx", + "ch5_err", "ch5_rec", "ch5_trx"; + clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, + <&cpg CPG_MOD 0x9e>; + clock-names = "fck", "ram_clk", "can_clk"; + assigned-clocks = <&cpg CPG_MOD 0x9e>; + assigned-clock-rates = <80000000>; + resets = <&cpg 0xa1>, <&cpg 0xa2>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; + channel2 { + status = "disabled"; + }; + channel3 { + status = "disabled"; + }; + channel4 { + status = "disabled"; + }; + channel5 { + status = "disabled"; + }; + }; + rspi0: spi@12800000 { compatible = "renesas,r9a09g057-rspi"; reg = <0x0 0x12800000 0x0 0x400>; From a1b1ee0348f889ec262482e16e9ff670617db7b0 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 6 Jan 2026 13:13:19 +0000 Subject: [PATCH 459/757] arm64: dts: renesas: rzt2h-n2h-evk-common: Use GPIO for SD0 write protect Switch SD0 write-protect detection to a GPIO on the RZ/T2H and RZ/N2H EVKs. Both boards use a full-size SD card slot on the SD0 channel with a dedicated WP pin. The RZ/T2H and RZ/N2H SoCs use of_data_rcar_gen3, which sets MMC_CAP2_NO_WRITE_PROTECT and causes the core to ignore the WP signal unless a wp-gpios property is provided. Describe the WP pin as a GPIO to allow the MMC core to evaluate the write-protect status correctly. Fixes: d065453e5ee0 ("arm64: dts: renesas: rzt2h-rzn2h-evk: Enable SD card slot") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260106131319.643084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 3eed1f3948e8..63bd91690b54 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -224,8 +224,7 @@ ctrl-pins { pinmux = , /* SD0_CLK */ , /* SD0_CMD */ - , /* SD0_CD */ - ; /* SD0_WP */ + ; /* SD0_CD */ }; }; @@ -282,6 +281,7 @@ pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sdhi0>; + wp-gpios = <&pinctrl RZT2H_GPIO(22, 6) GPIO_ACTIVE_HIGH>; bus-width = <4>; sd-uhs-sdr50; sd-uhs-sdr104; From ee021b27333b657d0799ac791c1a6b9ddb293547 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 9 Jan 2026 16:14:34 +0100 Subject: [PATCH 460/757] arm64: dts: qcom: kodiak: Add missing clock votes for lpass_tlmm Without the correct clock votes set, we may be hitting a synchronous external abort error when touching the lpi registers. Internal error: synchronous external abort: 0000000096000010 [#1] SMP <...> Call trace: lpi_gpio_read.isra.0+0x2c/0x58 (P) pinmux_enable_setting+0x218/0x300 pinctrl_commit_state+0xb0/0x280 pinctrl_select_state+0x28/0x48 pinctrl_bind_pins+0x1f4/0x2a0 really_probe+0x64/0x3a8 Add the clocks to fix that. Platforms with this SoC using AudioReach won't be impacted due to qcs6490-audioreach.dtsi already setting clocks & clock-names for q6prmcc. The sc7280-chrome-common.dtsi has also been adjusted to keep the behavior the same as they also do not use Elite with q6afecc. Signed-off-by: Luca Weiss Tested-by: Bhushan Shah # On fairphone-fp5 Link: https://lore.kernel.org/r/20260109-kodiak-lpass-tlmm-clocks-v1-1-746112687772@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 5 +++++ arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 076069f14495..f478c5e1d2d5 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2994,6 +2994,11 @@ compatible = "qcom,sc7280-lpass-lpi-pinctrl"; reg = <0 0x033c0000 0x0 0x20000>, <0 0x03550000 0x0 0x10000>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 15>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 84c6d662b54f..617a39d32488 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -67,6 +67,11 @@ status = "okay"; }; +&lpass_tlmm { + /delete-property/ clocks; + /delete-property/ clock-names; +}; + &lpasscc { status = "okay"; }; From 0e09a596ad2e23d62e2707d5d1a68eaa76787f1b Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Fri, 9 Jan 2026 17:03:59 +0300 Subject: [PATCH 461/757] arm64: dts: qcom: sdm630: Add LPASS LPI TLMM The LPASS LPI TLMM pin controller controls pins for use by the analog and digital codecs, such as the PDM bus, the digital microphone pins, and the compander pins. Add it to support the codecs. Signed-off-by: Richard Acayan Co-developed-by: Nickolay Goppen Signed-off-by: Nickolay Goppen Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260109-qcom-sdm660-lpass-lpi-dts-v1-1-d3eb84f10a39@mainlining.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 73 ++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e38d9648a1ac..4a72e0718fe4 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2269,6 +2269,79 @@ status = "disabled"; }; + lpi_tlmm: pinctrl@15070000 { + compatible = "qcom,sdm660-lpass-lpi-pinctrl"; + reg = <0x15070000 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_pdm_default: cdc-pdm-default-state { + clk-pins { + pins = "gpio18"; + function = "pdm_clk"; + drive-strength = <8>; + output-high; + }; + + sync-pins { + pins = "gpio19"; + function = "pdm_sync"; + drive-strength = <4>; + output-high; + }; + + tx-pins { + pins = "gpio20"; + function = "pdm_tx"; + drive-strength = <8>; + }; + + rx-pins { + pins = "gpio21", "gpio23", "gpio25"; + function = "pdm_rx"; + drive-strength = <4>; + output-high; + }; + }; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <8>; + }; + + cdc_dmic_default: cdc-dmic-default-state { + dmic1-clk-pins { + pins = "gpio26"; + function = "dmic1_clk"; + drive-strength = <8>; + output-high; + }; + + dmic1-data-pins { + pins = "gpio27"; + function = "dmic1_data"; + drive-strength = <8>; + output-high; + }; + + dmic2-clk-pins { + pins = "gpio28"; + function = "dmic2_clk"; + drive-strength = <8>; + input-enable; + }; + + dmic2-data-pins { + pins = "gpio29"; + function = "dmic2_data"; + drive-strength = <8>; + input-enable; + }; + }; + }; + adsp_pil: remoteproc@15700000 { compatible = "qcom,sdm660-adsp-pas"; reg = <0x15700000 0x4040>; From 960609b22be58baa16823103894de3c6858e6cf4 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 9 Jan 2026 18:45:02 +0800 Subject: [PATCH 462/757] arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports Since describing the PCIe PHY directly under the RC node is now deprecated, move the references to the respective PCIe port nodes, creating them where necessary.Also add port nodes for PCIe5 and PCIe6a with proper PHY references. And also move the PCIe PERST and wake GPIOs from the controller nodes to the corresponding PCIe port nodes on Hamoa-based platforms: - x1e001de-devkit - x1e78100-lenovo-thinkpad-t14s - x1e80100-asus-vivobook-s15 - x1e80100-asus-zenbook-a14 - x1e80100-dell-xps13-9345 - x1e80100-lenovo-yoga-slim7x - x1e80100-microsoft-romulus - x1e80100-qcp Signed-off-by: Ziyue Zhang Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260109104504.3147745-2-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 42 +++++++++++++------ arch/arm64/boot/dts/qcom/x1e001de-devkit.dts | 24 +++++++---- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 24 +++++++---- .../dts/qcom/x1e80100-asus-vivobook-s15.dts | 14 ++++--- .../dts/qcom/x1e80100-asus-zenbook-a14.dts | 3 ++ .../dts/qcom/x1e80100-dell-xps13-9345.dts | 14 ++++--- .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 8 ++-- .../dts/qcom/x1e80100-microsoft-romulus.dtsi | 19 ++++++--- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 21 ++++++---- 9 files changed, 108 insertions(+), 61 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index a559f6340af9..f464ff3b89cb 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -3261,9 +3261,6 @@ power-domains = <&gcc GCC_PCIE_3_GDSC>; - phys = <&pcie3_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; @@ -3404,12 +3401,14 @@ }; }; - pcie3_port: pcie@0 { + pcie3_port0: pcie@0 { device_type = "pci"; compatible = "pciclass,0604"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie3_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -3538,13 +3537,22 @@ power-domains = <&gcc GCC_PCIE_6A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie6a_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; status = "disabled"; + + pcie6a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie6a_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie6a_phy: phy@1bfc000 { @@ -3670,12 +3678,21 @@ power-domains = <&gcc GCC_PCIE_5_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie5_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; status = "disabled"; + + pcie5_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + phys = <&pcie5_phy>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie5_phy: phy@1c06000 { @@ -3800,9 +3817,6 @@ power-domains = <&gcc GCC_PCIE_4_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie4_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; status = "disabled"; @@ -3812,6 +3826,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie4_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts index a9643cd746d5..d5a60671a383 100644 --- a/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts +++ b/arch/arm64/boot/dts/qcom/x1e001de-devkit.dts @@ -1003,9 +1003,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -1019,10 +1016,12 @@ status = "okay"; }; -&pcie5 { - perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; +&pcie5 { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-0 = <&pcie5_default>; @@ -1038,10 +1037,12 @@ status = "okay"; }; -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; +&pcie6a { vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -1057,6 +1058,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index 7aee9a20c6df..b45e377a22c6 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -1113,9 +1113,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -1129,10 +1126,12 @@ status = "okay"; }; -&pcie5 { - perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +&pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; +&pcie5 { vddpe-3v3-supply = <&vreg_wwan>; pinctrl-0 = <&pcie5_default>; @@ -1148,10 +1147,12 @@ status = "okay"; }; -&pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; +&pcie6a { vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -1167,6 +1168,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts index 34467b84a2fa..17269eb0638a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts @@ -907,9 +907,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -924,6 +921,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -941,9 +941,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -959,6 +956,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts index 0408ade7150f..b42318c75ed2 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-asus-zenbook-a14.dts @@ -82,6 +82,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts index 2f533e56c8c8..4c95b1af2c64 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts @@ -941,9 +941,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -958,6 +955,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -975,9 +975,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -993,6 +990,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts index 4c31d14a07bc..d6472e5a3f9f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts @@ -1160,9 +1160,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -1178,6 +1175,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi index 7e1e808ea983..37539a09b76e 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi @@ -1094,9 +1094,6 @@ }; &pcie3 { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie3_default>; pinctrl-names = "default"; @@ -1112,6 +1109,11 @@ status = "okay"; }; +&pcie3_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4 { status = "okay"; }; @@ -1124,6 +1126,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1141,9 +1146,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie6a_default>; @@ -1159,6 +1161,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index b742aabd9c04..1d402ef86512 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -979,8 +979,6 @@ &pcie3 { pinctrl-names = "default"; pinctrl-0 = <&pcie3_default>; - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -992,16 +990,16 @@ status = "okay"; }; -&pcie3_port { +&pcie3_port0 { vpcie12v-supply = <&vreg_pcie_12v>; vpcie3v3-supply = <&vreg_pcie_3v3>; vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; + + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -1016,6 +1014,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1033,9 +1034,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -1051,6 +1049,11 @@ status = "okay"; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &qupv3_0 { status = "okay"; }; From a395b859ecacedc6ff28e6b62e43a7cd1abc34ee Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 9 Jan 2026 18:45:03 +0800 Subject: [PATCH 463/757] arm64: dts: qcom: Add PCIe3 and PCIe5 support for HAMOA-IOT-SOM platform HAMOA IoT SOM requires PCIe3 and PCIe5 connectivity for SATA controller and SDX65. Add the required sideband signals (PERST#, WAKE#, CLKREQ#), pinctrl states and power supply properties in the device tree, which PCIe3 and PCIe5 require. Signed-off-by: Ziyue Zhang Reviewed-by: Krishna Chaitanya Chundru Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260109104504.3147745-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 4a69852e9176..81866f94fe01 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -390,6 +390,20 @@ firmware-name = "qcom/x1e80100/gen70500_zap.mbn"; }; +&pcie3 { + pinctrl-0 = <&pcie3_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie3_phy { + vdda-phy-supply = <&vreg_l3c_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + &pcie4 { perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; @@ -407,6 +421,20 @@ status = "okay"; }; +&pcie5 { + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l3i_0p8>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + status = "okay"; +}; + &pcie6a { perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; @@ -453,6 +481,29 @@ &tlmm { gpio-reserved-ranges = <34 2>; /* TPM LP & INT */ + pcie3_default: pcie3-default-state { + clkreq-n-pins { + pins = "gpio144"; + function = "pcie3_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio143"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio145"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; @@ -476,6 +527,29 @@ }; }; + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio150"; + function = "pcie5_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio149"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio151"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie6a_default: pcie6a-default-state { clkreq-n-pins { pins = "gpio153"; From ac62730dbc71e4e2320b368e86e0c6ea3e41f1f5 Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Fri, 9 Jan 2026 18:45:04 +0800 Subject: [PATCH 464/757] arm64: dts: qcom: Add PCIe3 and PCIe5 regulators for HAMAO-IOT-EVK board HAMAO IoT EVK uses PCIe5 to connect an SDX65 module for WWAN functionality and PCIe3 to connect a SATA controller. These interfaces require multiple voltage rails: PCIe5 needs 3.3V supplied by vreg_wwan, while PCIe3 requires 12V, 3.3V, and 3.3V AUX rails, controlled via PMIC GPIOs. Add the required fixed regulators with related pin configuration, and connect them to the PCIe3 and PCIe5 ports to ensure proper power for the SDX65 module and SATA controller. Move reset and wake GPIO properties from RC nodes to port nodes. Signed-off-by: Ziyue Zhang Reviewed-by: Krishna Chaitanya Chundru Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260109104504.3147745-4-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 97 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi | 6 -- 2 files changed, 97 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 898b92627f84..07378ee183f9 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -253,6 +253,48 @@ regulator-boot-on; }; + vreg_pcie_12v: regulator-pcie-12v { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + + gpio = <&pm8550ve_8_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pcie_x8_12v>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3: regulator-pcie-3v3 { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_main_3p3_en>; + pinctrl-names = "default"; + }; + + vreg_pcie_3v3_aux: regulator-pcie-3v3-aux { + compatible = "regulator-fixed"; + + regulator-name = "VREG_PCIE_3P3_AUX"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmc8380_3_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&pm_sde7_aux_3p3_en>; + pinctrl-names = "default"; + }; + /* Left unused as the retimer is not used on this board. */ vreg_rtmr0_1p15: regulator-rtmr0-1p15 { compatible = "regulator-fixed"; @@ -920,7 +962,19 @@ status = "okay"; }; +&pcie3_port0 { + vpcie12v-supply = <&vreg_pcie_12v>; + vpcie3v3-supply = <&vreg_pcie_3v3>; + vpcie3v3aux-supply = <&vreg_pcie_3v3_aux>; + + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie4_port0 { + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -937,10 +991,24 @@ }; }; +&pcie5 { + vddpe-3v3-supply = <&vreg_wwan>; +}; + +&pcie5_port0 { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; +}; + &pcie6a { vddpe-3v3-supply = <&vreg_nvme>; }; +&pcie6a_port0 { + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; + &pm8550_gpios { rtmr0_default: rtmr0-reset-n-active-state { pins = "gpio10"; @@ -961,6 +1029,17 @@ }; }; +&pm8550ve_8_gpios { + pcie_x8_12v: pcie-12v-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + output-high; + bias-pull-down; + power-source = <0>; + }; +}; + &pm8550ve_9_gpios { usb0_1p8_reg_en: usb0-1p8-reg-en-state { pins = "gpio8"; @@ -1025,6 +1104,24 @@ }; }; +&pmc8380_3_gpios { + pm_sde7_aux_3p3_en: pcie-aux-3p3-default-state { + pins = "gpio8"; + function = "normal"; + output-enable; + bias-pull-down; + power-source = <0>; + }; + + pm_sde7_main_3p3_en: pcie-main-3p3-default-state { + pins = "gpio6"; + function = "normal"; + output-enable; + bias-pull-down; + power-source = <0>; + }; +}; + &pmc8380_5_gpios { usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { pins = "gpio8"; diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi index 81866f94fe01..b8e3e04a6fbd 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-som.dtsi @@ -405,9 +405,6 @@ }; &pcie4 { - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie4_default>; pinctrl-names = "default"; @@ -436,9 +433,6 @@ }; &pcie6a { - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie6a_default>; pinctrl-names = "default"; From 4f791e008807a1e7743cf6048822bab259b2ad0c Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Mon, 3 Nov 2025 15:06:22 +0800 Subject: [PATCH 465/757] arm64: dts: qcom: monaco: Add CTCU and ETR nodes Add CTCU and ETR nodes in DT to enable expected functionalities. Acked-by: Konrad Dybcio Signed-off-by: Jie Gan Link: https://lore.kernel.org/r/20251103-enable-ctcu-for-monaco-v4-2-92ff83201584@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 153 +++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 31b4145a1d23..83780cd3dc8a 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -2873,6 +2873,35 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ctcu@4001000 { + compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; + reg = <0x0 0x04001000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ctcu_in0: endpoint { + remote-endpoint = <&etr0_out>; + }; + }; + + port@1 { + reg = <1>; + + ctcu_in1: endpoint { + remote-endpoint = <&etr1_out>; + }; + }; + }; + }; + stm@4002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x04002000 0x0 0x1000>, @@ -2903,6 +2932,14 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + swao_rep_out0: endpoint { + remote-endpoint = <&qdss_rep_in>; + }; + }; + port@1 { reg = <1>; @@ -3067,6 +3104,122 @@ }; }; + replicator@4046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x04046000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + qdss_rep_in: endpoint { + remote-endpoint = <&swao_rep_out0>; + }; + }; + }; + + out-ports { + port { + qdss_rep_out0: endpoint { + remote-endpoint = <&etr_rep_in>; + }; + }; + }; + }; + + tmc@4048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x04048000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04c0 0x00>; + + arm,scatter-gather; + + in-ports { + port { + etr0_in: endpoint { + remote-endpoint = <&etr_rep_out0>; + }; + }; + }; + + out-ports { + port { + etr0_out: endpoint { + remote-endpoint = <&ctcu_in0>; + }; + }; + }; + }; + + replicator@404e000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x0 0x0404e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_rep_in: endpoint { + remote-endpoint = <&qdss_rep_out0>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + etr_rep_out0: endpoint { + remote-endpoint = <&etr0_in>; + }; + }; + + port@1 { + reg = <1>; + + etr_rep_out1: endpoint { + remote-endpoint = <&etr1_in>; + }; + }; + }; + }; + + tmc@404f000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x0404f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + iommus = <&apps_smmu 0x04a0 0x40>; + + arm,scatter-gather; + arm,buffer-size = <0x400000>; + + in-ports { + port { + etr1_in: endpoint { + remote-endpoint = <&etr_rep_out1>; + }; + }; + }; + + out-ports { + port { + etr1_out: endpoint { + remote-endpoint = <&ctcu_in1>; + }; + }; + }; + }; + tpdm@4841000 { compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0 0x04841000 0x0 0x1000>; From d106f9681d1952b7c19726b0713cee6ae11211f5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 6 Jan 2026 19:51:24 +0100 Subject: [PATCH 466/757] arm64: dts: qcom: ipq5018: Correct USB DWC3 wrapper interrupts Interrupts for DWC3 node were completely mixed up - SPI interrupt 62 is not listed in reference manual at all. It was also causing dtbs_check warnings: ipq5018-rdp432-c2.dtb: usb@8af8800 (qcom,ipq5018-dwc3): interrupt-names:0: 'pwr_event' was expected ipq5018-rdp432-c2.dtb: usb@8af8800 (qcom,ipq5018-dwc3): interrupt-names: ['hs_phy_irq'] is too short Warning itself was introduced by commit 53c6d854be4e ("dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding"), but this was trying to bring sanity to the interrupts overall, although did a mistake for IPQ5018. IPQ5018 does not have QUSB2 PHY and its interrupts should rather match ones used in IPQ5332. Correct it by using interrupts matching the bindings and reference manual. Signed-off-by: Krzysztof Kozlowski Tested-by: George Moussalem Link: https://lore.kernel.org/r/20260106185123.19929-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 721b642acf8e..6f8004a22a1f 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -571,8 +571,12 @@ compatible = "qcom,ipq5018-dwc3", "qcom,dwc3"; reg = <0x08af8800 0x400>; - interrupts = ; - interrupt-names = "hs_phy_irq"; + interrupts = , + , + ; + interrupt-names = "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; clocks = <&gcc GCC_USB0_MASTER_CLK>, <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, From bd2dc325db8c8cb29b65b0c636e31babc2bfeddf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 6 Jan 2026 19:51:25 +0100 Subject: [PATCH 467/757] arm64: dts: qcom: ipq9574: Complete USB DWC3 wrapper interrupts Complete interrupts for DWC3 node to match what is required by Devicetree bindings, as reported by dtbs_check: ipq9574-rdp433.dtb: usb@8af8800 (qcom,ipq9574-dwc3): interrupt-names: ['pwr_event'] is too short The actual interrupt numbers are taken from reference manual of similar chip, but not IPQ9574, due to lack of access to it. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Kathiravan Thirumoorthy Tested-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20260106185123.19929-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 86c9cb9fffc9..d7278f2137ac 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -765,8 +765,14 @@ assigned-clock-rates = <200000000>, <24000000>; - interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event"; + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event", + "qusb2_phy", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; resets = <&gcc GCC_USB_BCR>; status = "disabled"; From ca25bb421bdc81849dd527641cd7405fb5eba8fc Mon Sep 17 00:00:00 2001 From: Yuanjie Yang Date: Thu, 8 Jan 2026 17:25:41 +0800 Subject: [PATCH 468/757] arm64: dts: qcom: talos: switch to interrupt-cells 4 to add PPI partitions The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch to interrupt-cells = <4> in the GIC node to allow adding an interrupt partition map phandle as the 4th cell value for GIC_PPI interrupts. Signed-off-by: Yuanjie Yang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260108092542.1371-2-yuanjie.yang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 308 ++++++++++++++-------------- 1 file changed, 154 insertions(+), 154 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 96bacae93c70..571c42801ae1 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -489,7 +489,7 @@ smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; - interrupts = ; + interrupts = ; /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ mboxes = <&apss_shared 26>; @@ -511,7 +511,7 @@ smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; - interrupts = ; + interrupts = ; mboxes = <&apss_shared 6>; qcom,local-pid = <0>; @@ -689,8 +689,8 @@ "cqhci", "ice"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -751,14 +751,14 @@ compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0x0 0x800000 0x0 0x60000>; #dma-cells = <3>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; dma-channels = <8>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0xd6 0x0>; @@ -785,7 +785,7 @@ clock-names = "se"; pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -802,7 +802,7 @@ reg = <0x0 0x884000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c1_data_clk>; @@ -830,7 +830,7 @@ reg = <0x0 0x888000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c2_data_clk>; @@ -856,7 +856,7 @@ spi2: spi@888000 { compatible = "qcom,geni-spi"; reg = <0x0 0x00888000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; @@ -881,7 +881,7 @@ uart2: serial@888000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00888000 0x0 0x4000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; clock-names = "se"; pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, @@ -903,7 +903,7 @@ reg = <0x0 0x88c000 0x0 0x4000>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; clock-names = "se"; pinctrl-0 = <&qup_i2c3_data_clk>; @@ -931,14 +931,14 @@ compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; reg = <0x0 0xa00000 0x0 0x60000>; #dma-cells = <3>; - interrupts = , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + ; dma-channels = <8>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0x376 0x0>; @@ -965,7 +965,7 @@ clock-names = "se"; pinctrl-0 = <&qup_i2c4_data_clk>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -993,7 +993,7 @@ clock-names = "se"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1019,7 +1019,7 @@ pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1038,7 +1038,7 @@ clock-names = "se"; pinctrl-0 = <&qup_i2c5_data_clk>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1066,7 +1066,7 @@ clock-names = "se"; pinctrl-0 = <&qup_i2c6_data_clk>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1094,7 +1094,7 @@ clock-names = "se"; pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1120,7 +1120,7 @@ pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1139,7 +1139,7 @@ clock-names = "se"; pinctrl-0 = <&qup_i2c7_data_clk>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1167,7 +1167,7 @@ clock-names = "se"; pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS @@ -1193,7 +1193,7 @@ pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; pinctrl-names = "default"; - interrupts = ; + interrupts = ; interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS @@ -1260,15 +1260,15 @@ linux,pci-domain = <0>; num-lanes = <1>; - interrupts = , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + ; interrupt-names = "msi0", "msi1", "msi2", @@ -1281,10 +1281,10 @@ #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, @@ -1388,7 +1388,7 @@ reg-names = "std", "ice"; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -1497,7 +1497,7 @@ cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x24000>; - interrupts = ; + interrupts = ; #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; @@ -1536,7 +1536,7 @@ reg-names = "east", "west", "south"; - interrupts = ; + interrupts = ; gpio-ranges = <&tlmm 0 0 124>; gpio-controller; #gpio-cells = <2>; @@ -3463,7 +3463,7 @@ compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; reg = <0x0 0x08300000 0x0 0x4040>; - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -3490,7 +3490,7 @@ status = "disabled"; glink-edge { - interrupts = ; + interrupts = ; mboxes = <&apss_shared 4>; label = "cdsp"; qcom,remote-pid = <5>; @@ -3550,7 +3550,7 @@ pmu@90b6300 { compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0x0 0x090b6300 0x0 0x600>; - interrupts = ; + interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -3572,7 +3572,7 @@ pmu@90cd000 { compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x090cd000 0x0 0x1000>; - interrupts = ; + interrupts = ; interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; @@ -3624,8 +3624,8 @@ reg = <0x0 0x08804000 0x0 0x1000>; reg-names = "hc"; - interrupts = , - ; + interrupts = , + ; interrupt-names = "hc_irq", "pwr_irq"; @@ -3698,7 +3698,7 @@ venus: video-codec@aa00000 { compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; reg = <0x0 0x0aa00000 0x0 0x100000>; - interrupts = ; + interrupts = ; clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, <&videocc VIDEO_CC_VENUS_AHB_CLK>, @@ -3809,7 +3809,7 @@ <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK>; - interrupts = ; + interrupts = ; interrupt-controller; #interrupt-cells = <1>; @@ -4082,7 +4082,7 @@ aoss_qmp: power-management@c300000 { compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; - interrupts = ; + interrupts = ; mboxes = <&apss_shared 0>; #clock-cells = <0>; @@ -4114,71 +4114,71 @@ #global-interrupts = <1>; dma-coherent; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; spmi_bus: spmi@c440000 { @@ -4207,9 +4207,9 @@ compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ - interrupts = ; + interrupts = ; #address-cells = <0>; - #interrupt-cells = <3>; + #interrupt-cells = <4>; interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; @@ -4225,7 +4225,7 @@ watchdog: watchdog@17c10000 { compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; reg = <0x0 0x17c10000 0x0 0x1000>; - interrupts = ; + interrupts = ; clocks = <&sleep_clk>; }; @@ -4240,49 +4240,49 @@ reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; frame-number = <0>; - interrupts = , - ; + interrupts = , + ; }; frame@17c23000 { reg = <0x17c23000 0x1000>; frame-number = <1>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@17c25000 { reg = <0x17c25000 0x1000>; frame-number = <2>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@17c27000 { reg = <0x17c27000 0x1000>; frame-number = <3>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@17c29000 { reg = <0x17c29000 0x1000>; frame-number = <4>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@17c2b000 { reg = <0x17c2b000 0x1000>; frame-number = <5>; - interrupts = ; + interrupts = ; status = "disabled"; }; frame@17c2d000 { reg = <0x17c2d000 0x1000>; frame-number = <6>; - interrupts = ; + interrupts = ; status = "disabled"; }; }; @@ -4296,9 +4296,9 @@ "drv-1", "drv-2"; - interrupts = , - , - ; + interrupts = , + , + ; qcom,drv-id = <2>; qcom,tcs-offset = <0xd00>; @@ -4488,8 +4488,8 @@ <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 9 IRQ_TYPE_EDGE_BOTH>, <&pdc 8 IRQ_TYPE_EDGE_BOTH>, <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; @@ -4515,7 +4515,7 @@ reg = <0x0 0x0a600000 0x0 0xcd00>; iommus = <&apps_smmu 0x140 0x0>; - interrupts = ; + interrupts = ; phys = <&usb_1_hsphy>, <&usb_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; @@ -4552,8 +4552,8 @@ <&gcc GCC_USB20_SEC_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 11 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "pwr_event", @@ -4579,7 +4579,7 @@ reg = <0x0 0x0a800000 0x0 0xcd00>; iommus = <&apps_smmu 0xe0 0x0>; - interrupts = ; + interrupts = ; phys = <&usb_hsphy_2>; phy-names = "usb2-phy"; @@ -4598,8 +4598,8 @@ compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; reg = <0x0 0x0c263000 0x0 0x1000>, <0x0 0x0c222000 0x0 0x1000>; - interrupts = , - ; + interrupts = , + ; interrupt-names = "uplow", "critical"; #qcom,sensors = <16>; #thermal-sensor-cells = <1>; @@ -4609,7 +4609,7 @@ compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; reg = <0x0 0x62400000 0x0 0x4040>; - interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING 0>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, @@ -4636,7 +4636,7 @@ status = "disabled"; glink_edge: glink-edge { - interrupts = ; + interrupts = ; mboxes = <&apss_shared 24>; label = "lpass"; qcom,remote-pid = <2>; @@ -4695,10 +4695,10 @@ arch_timer: timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; thermal-zones { From 63a47fc13cbef0a4fc5e011f07f47a921312fc81 Mon Sep 17 00:00:00 2001 From: Yuanjie Yang Date: Thu, 8 Jan 2026 17:25:42 +0800 Subject: [PATCH 469/757] arm64: dts: qcom: talos: Add PMU support Add the PMU node for talos platforms. Signed-off-by: Yuanjie Yang Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260108092542.1371-3-yuanjie.yang@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 571c42801ae1..d956c91c7cc8 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -550,6 +550,16 @@ }; }; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = ; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = ; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -4213,6 +4223,16 @@ interrupt-controller; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu6 &cpu7>; + }; + }; }; apss_shared: mailbox@17c00000 { From 97a9b5edcdd4179063773f17a00904a464b8aa7c Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 19 Nov 2025 16:55:26 -0600 Subject: [PATCH 470/757] arm64: dts: rockchip: Add HDMI to Gameforce Ace Add support for the HDMI port for the Gameforce Ace. The HDMI port has no HPD pin present (the manufacturer's devicetree states the pin is reused for an additional face button) so add the attribute of no-hpd to poll for connected devices. Signed-off-by: Chris Morgan Link: https://patch.msgid.link/20251119225526.70588-4-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- .../dts/rockchip/rk3588s-gameforce-ace.dts | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts index 21eb003198fe..e8ad525ba3f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-gameforce-ace.dts @@ -300,6 +300,20 @@ sound-name-prefix = "Headphones Amplifier"; }; + hdmi0-con { + compatible = "hdmi-connector"; + ddc-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&hdmi0_en>; + pinctrl-names = "default"; + type = "d"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + pwm_fan: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; @@ -498,6 +512,34 @@ status = "okay"; }; +&hdmi0 { + no-hpd; + pinctrl-0 = <&hdmim0_tx0_cec>, <&hdmim0_tx0_scl>, + <&hdmim0_tx0_sda>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c0 { pinctrl-0 = <&i2c0m2_xfer>; pinctrl-names = "default"; @@ -746,6 +788,10 @@ status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &mipidcphy0 { status = "okay"; }; @@ -846,6 +892,13 @@ }; }; + hdmi { + hdmi0_en: hdmi0-en { + rockchip,pins = + <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = @@ -1450,6 +1503,16 @@ status = "okay"; }; +&vp0 { + #address-cells = <1>; + #size-cells = <0>; + + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; + &vp3 { #address-cells = <1>; #size-cells = <0>; From a770eb1f3219dfc4c28dac66c96735fa8acba4e6 Mon Sep 17 00:00:00 2001 From: David Petry Date: Tue, 21 Oct 2025 18:06:02 +0200 Subject: [PATCH 471/757] arm64: dts: rockchip: Enable second HDMI output on CM3588 Enable the second HDMI output port found on FriendlyElec CM3588 and CM3588 Plus Signed-off-by: David Petry Link: https://patch.msgid.link/20251021160603.96934-1-petry103@gmail.com Signed-off-by: Heiko Stuebner --- .../rk3588-friendlyelec-cm3588-nas.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts index 5fbbeb6f5a93..10a7d3691a26 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -101,6 +101,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; @@ -335,6 +346,22 @@ }; }; +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + &hdmi_receiver_cma { status = "okay"; }; @@ -350,6 +377,10 @@ status = "okay"; }; +&hdptxphy1 { + status = "okay"; +}; + /* Connected to MIPI-DSI0 */ &i2c5 { pinctrl-names = "default"; @@ -840,3 +871,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; From 5d719a4703566267492129d13516d87066f288f8 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 27 Oct 2025 23:56:35 +0200 Subject: [PATCH 472/757] dt-bindings: arm: rockchip: Add Orange Pi CM5 Base The Orange Pi CM5 Base board is a carrier board for the Orange Pi CM5 compute module. It has 3 ethernet ports, 2 USB ports, one HDMI output and 4 CSI-2 inputs. Signed-off-by: Laurent Pinchart Acked-by: Conor Dooley Link: https://patch.msgid.link/20251027215637.20715-2-laurent.pinchart@ideasonboard.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 59a7aed538b4..c9b078be3a90 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1306,6 +1306,12 @@ properties: - xunlong,orangepi-5b - const: rockchip,rk3588s + - description: Xunlong Orange Pi CM5 + items: + - const: xunlong,orangepi-cm5-base + - const: xunlong,orangepi-cm5 + - const: rockchip,rk3588s + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 From 3cdaec4d5e8c24ce3298c93bac80c31820b91aff Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 27 Oct 2025 23:56:36 +0200 Subject: [PATCH 473/757] arm64: dts: rockchip: Add rk3588s-orangepi-cm5-base device tree The Orange Pi CM5 Base board is a carrier board for the Orange Pi CM5 compute module. It has 3 ethernet ports, 2 USB ports, one HDMI output and 4 CSI-2 inputs. The device tree is split in two files, a .dtsi for the compute module and a .dts for the carrier board. All the devices present on the carrier board are enabled and tested, with the exception of the IR receiver due to missing support for input capture in the PWM device's DT binding (and driver). This work is based on a combination of the Orange Pi 5 device tree from the upstream kernel and the Orange Pi CM5 device tree from the BSP kernel. All nodes and properties have been carefully checked to the best of my abilities against the schematics of the carrier board. The schematics of the compute module is not available publicly, so the configuration of the PMIC hasn't been double-checked. Signed-off-by: Laurent Pinchart Link: https://patch.msgid.link/20251027215637.20715-3-laurent.pinchart@ideasonboard.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3588s-orangepi-cm5-base.dts | 355 +++++++++++++ .../dts/rockchip/rk3588s-orangepi-cm5.dtsi | 472 ++++++++++++++++++ 3 files changed, 828 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 105dae928f97..a02510bb9c48 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -210,6 +210,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-cm5-base.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts new file mode 100644 index 000000000000..06120b2db690 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5-base.dts @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +#include "rk3588s-orangepi-cm5.dtsi" + +/ { + model = "Xunlong Orange Pi CM5 Base"; + compatible = "xunlong,orangepi-cm5-base", "xunlong,orangepi-cm5", "rockchip,rk3588s"; + + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button { + debounce-interval = <50>; + gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + label = "USERKEY"; + linux,code = ; + wakeup-source; + }; + }; + + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + + pwm-leds { + compatible = "pwm-leds"; + + led-1 { + color = ; + function = LED_FUNCTION_STATUS; + linux,default-trigger = "heartbeat"; + max-brightness = <255>; + pwms = <&pwm2 0 25000 0>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_WAN; + max-brightness = <255>; + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + max-brightness = <255>; + pwms = <&pwm5 0 25000 PWM_POLARITY_INVERTED>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; + }; + }; + + vbus_5v0: regulator-vbus-5v0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus_5v0_en_pin>; + regulator-name = "vbus_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_3v3_en_pin>; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-vcc-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_rx_bus2 + &gmac1_tx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + status = "okay"; +}; + +&hdmi0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd + &hdmim0_tx0_scl &hdmim0_tx0_sda + &hdmi_frl_pin>; + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_pin>; + wakeup-source; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@1 { + /* YT8531C */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_phy_pin>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pinctrl { + camera { + cam1_reset_pin: cam1-reset-pin { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam2_reset_pin: cam2-reset-pin { + rockchip,pins = <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam3_reset_pin: cam3-reset-pin { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + cam4_reset_pin: cam4-reset-pin { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + rgmii_phy_pin: rgmii-phy-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmi { + hdmi_frl_pin: hdmi-frl-pin { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + power { + vcc_3v3_en_pin: vcc-3v3-en-pin { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtc { + rtc_int_pin: rtc-int-pin { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vbus_5v0_en_pin: vbus-5v0-en-pin { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +&pwm6 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus_5v0>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vbus_5v0>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi new file mode 100644 index 000000000000..32357eba4b78 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dtsi @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include + +#include "rk3588s.dtsi" +#include "rk8xx.h" + +/ { + aliases { + mmc0 = &sdhci; + }; + + /* Can't be verified due to missing schematics for the CM5. */ + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + rockchip,reset-mode = ; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + /* + * The TSADC_SHUT pin is exposed to carrier boards as a signal named + * PMIC_RESET_L, meant to be driven externally. Reference carrier + * boards connect it to a reset button that pulls the signal to GND + * through a 100Ω resistor. This is too weak to overcome even the + * minimum drive strength of the TSADC_SHUT pin when driven in + * push-pull mode. Configure it as a GPIO, reset will be generated + * through the CRU. + */ + pinctrl-0 = <&tsadc_gpio_func>; + status = "okay"; +}; From 54b5415739300c89cdd6b1db152bb5acf047ce40 Mon Sep 17 00:00:00 2001 From: Khalid Faisal Ansari Date: Wed, 12 Nov 2025 13:12:09 +0530 Subject: [PATCH 474/757] arm64: dts: qcom: hamoa-iot-evk: Enable TPM (ST33) on SPI11 Enable ST33HTPM TPM over SPI11 on the Hamoa IoT EVK by adding the required SPI and TPM nodes. Signed-off-by: Khalid Faisal Ansari Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251112-arm64-dts-qcom-hamoa-iot-evk-enable-st33-tpm-on-spi11-v3-1-39b19eb55cc3@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts index 07378ee183f9..2390648a248f 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts +++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts @@ -1171,6 +1171,16 @@ vdd3-supply = <&vreg_l8b_3p0>; }; +&spi11 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + &swr0 { status = "okay"; From f61731bd60627b129b688c2d7b2071a5fe7f01d7 Mon Sep 17 00:00:00 2001 From: Detlev Casanova Date: Mon, 20 Oct 2025 17:20:08 -0400 Subject: [PATCH 475/757] arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588 Add the vdpu381 Video Decoders to the rk3588-base devicetree. The RK3588 based SoCs all embed 2 vdpu381 decoders. This also adds the dedicated IOMMU controllers. Signed-off-by: Detlev Casanova Link: https://patch.msgid.link/20251020212009.8852-2-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 2a7921793020..aa74e8d7b4e9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1353,6 +1353,70 @@ #iommu-cells = <0>; }; + vdec0: video-codec@fdc38000 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdc38100 0x0 0x500>, + <0x0 0xfdc38000 0x0 0x100>, + <0x0 0xfdc38600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = ; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, + <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus = <&vdec0_mmu>; + power-domains = <&power RK3588_PD_RKVDEC0>; + resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, + <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&vdec0_sram>; + }; + + vdec0_mmu: iommu@fdc38700 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RKVDEC0>; + #iommu-cells = <0>; + }; + + vdec1: video-codec@fdc40000 { + compatible = "rockchip,rk3588-vdec"; + reg = <0x0 0xfdc40100 0x0 0x500>, + <0x0 0xfdc40000 0x0 0x100>, + <0x0 0xfdc40600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = ; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, + <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + iommus = <&vdec1_mmu>; + power-domains = <&power RK3588_PD_RKVDEC1>; + resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, + <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&vdec1_sram>; + }; + + vdec1_mmu: iommu@fdc40700 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RKVDEC1>; + #iommu-cells = <0>; + }; + av1d: video-codec@fdc70000 { compatible = "rockchip,rk3588-av1-vpu"; reg = <0x0 0xfdc70000 0x0 0x800>; @@ -3249,6 +3313,16 @@ ranges = <0x0 0x0 0xff001000 0xef000>; #address-cells = <1>; #size-cells = <1>; + + vdec0_sram: codec-sram@0 { + reg = <0x0 0x78000>; + pool; + }; + + vdec1_sram: codec-sram@78000 { + reg = <0x78000 0x77000>; + pool; + }; }; pinctrl: pinctrl { From da0de806d8b46238ac3891a894806da4d1c26cdf Mon Sep 17 00:00:00 2001 From: Detlev Casanova Date: Mon, 20 Oct 2025 17:20:09 -0400 Subject: [PATCH 476/757] arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576 Add the vdpu383 Video Decoder variant to the RK3576 device tree. Also allow using the dedicated SRAM as a pool. Signed-off-by: Detlev Casanova Link: https://patch.msgid.link/20251020212009.8852-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 792857aee4f7..7286d968e2b0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1279,6 +1279,41 @@ status = "disabled"; }; + vdec: video-codec@27b00000 { + compatible = "rockchip,rk3576-vdec"; + reg = <0x0 0x27b00100 0x0 0x500>, + <0x0 0x27b00000 0x0 0x100>, + <0x0 0x27b00600 0x0 0x100>; + reg-names = "function", "link", "cache"; + interrupts = ; + clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, + <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <600000000>, <600000000>, + <500000000>, <1000000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3576_PD_VDEC>; + resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, + <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; + sram = <&rkvdec_sram>; + }; + + vdec_mmu: iommu@27b00800 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; + interrupts = ; + clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3576_PD_VDEC>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + }; + vop: vop@27d00000 { compatible = "rockchip,rk3576-vop"; reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; @@ -2684,6 +2719,7 @@ /* start address and size should be 4k align */ rkvdec_sram: rkvdec-sram@0 { reg = <0x0 0x78000>; + pool; }; }; From 71630e581a0e34c03757f5c1706f57c853b92555 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 29 Dec 2025 00:49:07 +0200 Subject: [PATCH 477/757] arm: dts: lpc32xx: add clocks property to Motor Control PWM device tree node Motor Control PWM depends on its own supply clock, the clock gate control is present in TIMCLK_CTRL1 register. Fixes: b7d41c937ed7 ("ARM: LPC32xx: Add the motor PWM to base dts file") Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index e89ef62f9fbb..7fa91d1ac9ea 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -322,6 +322,7 @@ mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled"; }; From 2940a49ab7e31e9fc4f43637dc9ef75b5e8951d4 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Sat, 10 Jan 2026 03:45:24 +0200 Subject: [PATCH 478/757] arm: dts: lpc32xx: add interrupts property to Motor Control PWM Motor Control PWM shares an interrupt line with TIMER4 on MIC interrupt controller, the interrupt serves as period (timer limit), pulse-width (match) and capture event interrupt. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 7fa91d1ac9ea..e94df78def18 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -322,6 +322,7 @@ mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled"; From 01a08fd967301e75b2a9350b28a3f09fa2c3b838 Mon Sep 17 00:00:00 2001 From: Gary Yang Date: Sat, 10 Jan 2026 17:34:05 +0800 Subject: [PATCH 479/757] dt-bindings: arm: cix: add OrangePi 6 Plus board OrangePi 6 Plus adopts CIX CD8180/CD8160 SoC, built-in 12-core 64-bit processor + NPU processor,integrated graphics processor, equipped with 16GB/32GB/64GB LPDDR5, and provides two M.2 KEY-M interfaces 2280 for NVMe SSD,as well as SPI FLASH and TF slots to meet the needs of fast read/write and high-capacity storage Reviewed-by: Krzysztof Kozlowski Signed-off-by: Gary Yang Link: https://lore.kernel.org/r/20260110093406.2700505-2-gary.yang@cixtech.com Signed-off-by: Peter Chen --- Documentation/devicetree/bindings/arm/cix.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/cix.yaml b/Documentation/devicetree/bindings/arm/cix.yaml index 114dab4bc4d2..21e66df7f696 100644 --- a/Documentation/devicetree/bindings/arm/cix.yaml +++ b/Documentation/devicetree/bindings/arm/cix.yaml @@ -16,9 +16,11 @@ properties: compatible: oneOf: - - description: Radxa Orion O6 + - description: Sky1 based boards items: - - const: radxa,orion-o6 + - enum: + - radxa,orion-o6 # Radxa Orion O6 board + - xunlong,orangepi-6-plus # Xunlong orangepi 6 plus board - const: cix,sky1 additionalProperties: true From e39fadd6ef7b797e1db7bb7bf2ed9a1784632a8b Mon Sep 17 00:00:00 2001 From: Gary Yang Date: Sat, 10 Jan 2026 17:34:06 +0800 Subject: [PATCH 480/757] arm64: dts: cix: Add OrangePi 6 Plus board support OrangePi 6 Plus adopts CIX CD8180/CD8160 SoC, built-in 12-core 64-bit processor + NPU processor,integrated graphics processor, equipped with 16GB/32GB/64GB LPDDR5, and provides two M.2 KEY-M interfaces 2280 for NVMe SSD,as well as SPI FLASH and TF slots to meet the needs of fast read/write and high-capacity storage Signed-off-by: Gary Yang Link: https://lore.kernel.org/r/20260110093406.2700505-3-gary.yang@cixtech.com Signed-off-by: Peter Chen --- arch/arm64/boot/dts/cix/Makefile | 1 + arch/arm64/boot/dts/cix/sky1-xcp.dts | 83 ++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+) create mode 100644 arch/arm64/boot/dts/cix/sky1-xcp.dts diff --git a/arch/arm64/boot/dts/cix/Makefile b/arch/arm64/boot/dts/cix/Makefile index ed3713982012..8a6c6fdc4ec0 100644 --- a/arch/arm64/boot/dts/cix/Makefile +++ b/arch/arm64/boot/dts/cix/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_CIX) += sky1-orion-o6.dtb +dtb-$(CONFIG_ARCH_CIX) += sky1-xcp.dtb diff --git a/arch/arm64/boot/dts/cix/sky1-xcp.dts b/arch/arm64/boot/dts/cix/sky1-xcp.dts new file mode 100644 index 000000000000..1fae52dc9bb0 --- /dev/null +++ b/arch/arm64/boot/dts/cix/sky1-xcp.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2025 Cix Technology Group Co., Ltd. + * + */ + +/dts-v1/; + +#include "sky1.dtsi" +#include "sky1-pinfunc.h" + +/ { + model = "Xunlong,OrangePi 6 Plus"; + compatible = "xunlong,orangepi-6-plus", "cix,sky1"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = &uart2; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x28000000>; + linux,cma-default; + }; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hog-cfg { + pins { + pinmux = , + , + , + ; + bias-pull-down; + drive-strength = <8>; + }; + }; +}; + +&iomuxc_s5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_s5>; + + pinctrl_hog_s5: hog-s5-cfg { + pins { + pinmux = ; + bias-pull-up; + drive-strength = <8>; + + }; + }; +}; + +&pcie_x8_rc { + status = "okay"; +}; + +&pcie_x2_rc { + status = "okay"; +}; + +&pcie_x1_1_rc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; From 13e566e8df89b5521f8d60297c629c00f28e49ea Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Fri, 12 Dec 2025 14:32:07 -0600 Subject: [PATCH 481/757] arm/arm64: dts: renesas: Drop unused .dtsi These .dtsi files are not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) Acked-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251212203226.458694-1-robh@kernel.org Signed-off-by: Geert Uytterhoeven --- .../renesas/gr-peach-audiocamerashield.dtsi | 75 ---- .../dts/renesas/r8a77xx-aa121td01-panel.dtsi | 39 -- arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi | 332 ------------------ arch/arm64/boot/dts/renesas/r8a779m0.dtsi | 12 - arch/arm64/boot/dts/renesas/r8a779m2.dtsi | 12 - arch/arm64/boot/dts/renesas/r8a779m4.dtsi | 12 - arch/arm64/boot/dts/renesas/r8a779m6.dtsi | 12 - arch/arm64/boot/dts/renesas/r8a779m7.dtsi | 12 - arch/arm64/boot/dts/renesas/r8a779m8.dtsi | 17 - arch/arm64/boot/dts/renesas/r8a779mb.dtsi | 12 - arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi | 25 -- arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi | 18 - arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi | 18 - arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi | 18 - 14 files changed, 614 deletions(-) delete mode 100644 arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi delete mode 100644 arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r8a779m0.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r8a779m2.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r8a779m4.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r8a779m6.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r8a779m7.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r8a779m8.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r8a779mb.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi delete mode 100644 arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi diff --git a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi b/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi deleted file mode 100644 index 8d77579807ec..000000000000 --- a/arch/arm/boot/dts/renesas/gr-peach-audiocamerashield.dtsi +++ /dev/null @@ -1,75 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for the GR-Peach audiocamera shield expansion board - * - * Copyright (C) 2017 Jacopo Mondi - */ - -#include "r7s72100.dtsi" -#include -#include - -/ { - /* On-board camera clock. */ - camera_clk: camera_clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <27000000>; - }; -}; - -&pinctrl { - i2c1_pins: i2c1 { - /* P1_2 as SCL; P1_3 as SDA */ - pinmux = , ; - }; - - vio_pins: vio { - /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ - pinmux = , /* VIO_VD */ - , /* VIO_HD */ - , /* VIO_D0 */ - , /* VIO_D1 */ - , /* VIO_D2 */ - , /* VIO_D3 */ - , /* VIO_D4 */ - , /* VIO_D5 */ - , /* VIO_D6 */ - , /* VIO_D7 */ - ; /* VIO_CLK */ - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <100000>; - - camera@48 { - compatible = "aptina,mt9v111"; - reg = <0x48>; - - clocks = <&camera_clk>; - - port { - mt9v111_out: endpoint { - remote-endpoint = <&ceu_in>; - }; - }; - }; -}; - -&ceu { - pinctrl-names = "default"; - pinctrl-0 = <&vio_pins>; - - status = "okay"; - - port { - ceu_in: endpoint { - remote-endpoint = <&mt9v111_out>; - }; - }; -}; diff --git a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi b/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi deleted file mode 100644 index 6e7589ea7562..000000000000 --- a/arch/arm/boot/dts/renesas/r8a77xx-aa121td01-panel.dtsi +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Common file for the AA121TD01 panel connected to Renesas R-Car boards - * - * Copyright (C) 2015 Renesas Electronics Corp. - */ - -/ { - panel { - compatible = "mitsubishi,aa121td01", "panel-lvds"; - - width-mm = <261>; - height-mm = <163>; - data-mapping = "jeida-18"; - - panel-timing { - /* 1280x800 @60Hz */ - clock-frequency = <71000000>; - hactive = <1280>; - vactive = <800>; - hsync-len = <70>; - hfront-porch = <20>; - hback-porch = <70>; - vsync-len = <5>; - vfront-porch = <3>; - vback-porch = <15>; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds_connector>; - }; - }; - }; -}; - -&lvds_connector { - remote-endpoint = <&panel_in>; -}; diff --git a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi deleted file mode 100644 index e0930d1ba3aa..000000000000 --- a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi +++ /dev/null @@ -1,332 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Ideas on Board - * Copyright (C) 2021 Jacopo Mondi - * - * Device Tree Source (overlay) that describes GMSL camera connected to - * Fakra connectors for the Eagle V3M and Condor V3H (and compatible) boards. - * - * The following cameras are currently supported: RDACM20 and RDACM21. - * - * The board .dts file that include this has to select which cameras are in use - * by specifying the camera model with: - * - * #define GMSL_CAMERA_RDACM20 - * or - * #define GMSL_CAMERA_RDACM21 - * - * And which cameras are connected to the board by defining: - * for GMSL channel 0: - * #define GMSL_CAMERA_0 - * #define GMSL_CAMERA_1 - * #define GMSL_CAMERA_2 - * #define GMSL_CAMERA_3 - * - * for GMSL channel 1: - * #define GMSL_CAMERA_4 - * #define GMSL_CAMERA_5 - * #define GMSL_CAMERA_6 - * #define GMSL_CAMERA_7 - */ - -#include - -/* Validate the board file settings. */ -#if !defined(GMSL_CAMERA_RDACM20) && !defined(GMSL_CAMERA_RDACM21) -#error "Camera model should be defined by the board file" -#endif - -#if defined(GMSL_CAMERA_RDACM20) && defined(GMSL_CAMERA_RDACM21) -#error "A single camera model should be selected" -#endif - -#if !defined(GMSL_CAMERA_0) && !defined(GMSL_CAMERA_1) && \ - !defined(GMSL_CAMERA_2) && !defined(GMSL_CAMERA_3) && \ - !defined(GMSL_CAMERA_4) && !defined(GMSL_CAMERA_5) && \ - !defined(GMSL_CAMERA_6) && !defined(GMSL_CAMERA_7) -#error "At least one camera should be selected" -#endif - -/* Deduce from the enabled cameras which GMSL channels are active. */ -#if defined(GMSL_CAMERA_0) || defined(GMSL_CAMERA_1) || \ - defined(GMSL_CAMERA_2) || defined(GMSL_CAMERA_3) -#define GMSL_0 -#endif - -#if defined(GMSL_CAMERA_4) || defined(GMSL_CAMERA_5) || \ - defined(GMSL_CAMERA_6) || defined(GMSL_CAMERA_7) -#define GMSL_1 -#endif - -/* Deduce the camera model compatible string. */ -#if defined(GMSL_CAMERA_RDACM20) -#define GMSL_CAMERA_MODEL "imi,rdacm20" -#elif defined(GMSL_CAMERA_RDACM21) -#define GMSL_CAMERA_MODEL "imi,rdacm21" -#endif - -#ifdef GMSL_0 -&vin0 { - status = "okay"; -}; - -&vin1 { - status = "okay"; -}; - -&vin2 { - status = "okay"; -}; - -&vin3 { - status = "okay"; -}; - -&gmsl0 { - status = "okay"; - -#if defined(GMSL_CAMERA_RDACM21) - maxim,reverse-channel-microvolt = <100000>; -#endif - - ports { -#ifdef GMSL_CAMERA_0 - port@0 { - max9286_in0: endpoint { - remote-endpoint = <&fakra_con0>; - }; - }; -#endif - -#ifdef GMSL_CAMERA_1 - port@1 { - max9286_in1: endpoint { - remote-endpoint = <&fakra_con1>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_2 - port@2 { - max9286_in2: endpoint { - remote-endpoint = <&fakra_con2>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_3 - port@3 { - max9286_in3: endpoint { - remote-endpoint = <&fakra_con3>; - }; - - }; -#endif - }; - - i2c-mux { -#ifdef GMSL_CAMERA_0 - i2c@0 { - status = "okay"; - - camera@51 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x51>, <0x61>; - - port { - fakra_con0: endpoint { - remote-endpoint = <&max9286_in0>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_1 - i2c@1 { - status = "okay"; - - camera@52 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x52>, <0x62>; - - port { - fakra_con1: endpoint { - remote-endpoint = <&max9286_in1>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_2 - i2c@2 { - status = "okay"; - - camera@53 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x53>, <0x63>; - - port { - fakra_con2: endpoint { - remote-endpoint = <&max9286_in2>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_3 - i2c@3 { - status = "okay"; - - camera@54 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x54>, <0x64>; - - port { - fakra_con3: endpoint { - remote-endpoint = <&max9286_in3>; - }; - }; - }; - }; -#endif - }; -}; -#endif /* ifdef GMSL_0 */ - -#ifdef GMSL_1 -&vin4 { - status = "okay"; -}; - -&vin5 { - status = "okay"; -}; - -&vin6 { - status = "okay"; -}; - -&vin7 { - status = "okay"; -}; - -&gmsl1 { - status = "okay"; - -#if defined(GMSL_CAMERA_RDACM21) - maxim,reverse-channel-microvolt = <100000>; -#endif - - ports { -#ifdef GMSL_CAMERA_4 - port@0 { - max9286_in4: endpoint { - remote-endpoint = <&fakra_con4>; - }; - }; -#endif - -#ifdef GMSL_CAMERA_5 - port@1 { - max9286_in5: endpoint { - remote-endpoint = <&fakra_con5>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_6 - port@2 { - max9286_in6: endpoint { - remote-endpoint = <&fakra_con6>; - }; - - }; -#endif - -#ifdef GMSL_CAMERA_7 - port@3 { - max9286_in7: endpoint { - remote-endpoint = <&fakra_con7>; - }; - - }; -#endif - }; - - i2c-mux { -#ifdef GMSL_CAMERA_4 - i2c@0 { - status = "okay"; - - camera@55 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x55>, <0x65>; - - port { - fakra_con4: endpoint { - remote-endpoint = <&max9286_in4>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_5 - i2c@1 { - status = "okay"; - - camera@56 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x56>, <0x66>; - - port { - fakra_con5: endpoint { - remote-endpoint = <&max9286_in5>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_6 - i2c@2 { - status = "okay"; - - camera@57 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x57>, <0x67>; - - port { - fakra_con6: endpoint { - remote-endpoint = <&max9286_in6>; - }; - }; - }; - }; -#endif - -#ifdef GMSL_CAMERA_7 - i2c@3 { - status = "okay"; - - camera@58 { - compatible = GMSL_CAMERA_MODEL; - reg = <0x58>, <0x68>; - - port { - fakra_con7: endpoint { - remote-endpoint = <&max9286_in7>; - }; - }; - }; - }; -#endif - }; -}; -#endif /* ifdef GMSL_1 */ diff --git a/arch/arm64/boot/dts/renesas/r8a779m0.dtsi b/arch/arm64/boot/dts/renesas/r8a779m0.dtsi deleted file mode 100644 index 38978360e722..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m0.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3e (R8A779M0) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779m0", "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m2.dtsi b/arch/arm64/boot/dts/renesas/r8a779m2.dtsi deleted file mode 100644 index bced12764c69..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m2.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car M3e (R8A779M2) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77961.dtsi" - -/ { - compatible = "renesas,r8a779m2", "renesas,r8a77961"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m4.dtsi b/arch/arm64/boot/dts/renesas/r8a779m4.dtsi deleted file mode 100644 index ae8486056962..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m4.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car M3Ne (R8A779M4) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77965.dtsi" - -/ { - compatible = "renesas,r8a779m4", "renesas,r8a77965"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m6.dtsi b/arch/arm64/boot/dts/renesas/r8a779m6.dtsi deleted file mode 100644 index 94d6a6cf503e..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m6.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car E3e (R8A779M6) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77990.dtsi" - -/ { - compatible = "renesas,r8a779m6", "renesas,r8a77990"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m7.dtsi b/arch/arm64/boot/dts/renesas/r8a779m7.dtsi deleted file mode 100644 index 0580fa614034..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m7.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car D3e (R8A779M7) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77995.dtsi" - -/ { - compatible = "renesas,r8a779m7", "renesas,r8a77995"; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi b/arch/arm64/boot/dts/renesas/r8a779m8.dtsi deleted file mode 100644 index dfccc080fb3e..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3Ne (R8A779M8) SoC - * - * Copyright (C) 2021 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779m8", "renesas,r8a7795"; -}; - -&cluster0_opp { - /delete-node/ opp-1600000000; - /delete-node/ opp-1700000000; -}; diff --git a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi b/arch/arm64/boot/dts/renesas/r8a779mb.dtsi deleted file mode 100644 index 181b737c91cd..000000000000 --- a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Device Tree Source for the R-Car H3Ne-1.7G (R8A779MB) SoC - * - * Copyright (C) 2022 Glider bv - */ - -#include "r8a77951.dtsi" - -/ { - compatible = "renesas,r8a779mb", "renesas,r8a7795"; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi deleted file mode 100644 index 56a979e82c4f..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g044.dtsi" - -/ { - compatible = "renesas,r9a07g044c1", "renesas,r9a07g044"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; - -&soc { - /delete-node/ ssi@1004a800; - /delete-node/ serial@1004c800; - /delete-node/ adc@10059000; - /delete-node/ ethernet@11c30000; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi deleted file mode 100644 index 9cf27ca9f1d2..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g044l1.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g044.dtsi" - -/ { - compatible = "renesas,r9a07g044l1", "renesas,r9a07g044"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi deleted file mode 100644 index d85a6ac0f024..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts - * - * Copyright (C) 2021 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a07g054.dtsi" - -/ { - compatible = "renesas,r9a07g054l1", "renesas,r9a07g054"; - - cpus { - /delete-node/ cpu-map; - /delete-node/ cpu@100; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi deleted file mode 100644 index e50d9159e832..000000000000 --- a/arch/arm64/boot/dts/renesas/r9a09g047e37.dtsi +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the RZ/G3E R9A09G047E37 SoC specific parts - * - * Copyright (C) 2024 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r9a09g047.dtsi" - -/ { - compatible = "renesas,r9a09g047e37", "renesas,r9a09g047"; - - cpus { - /delete-node/ cpu@200; - /delete-node/ cpu@300; - }; -}; From fd4be5de4594a3f045a51b749a770b3d5a8e4368 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:23:59 +0100 Subject: [PATCH 482/757] arm64: dts: renesas: Use hyphens in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251223152358.152533-3-krzysztof.kozlowski@oss.qualcomm.com [geert: Fix'em all] Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi | 2 +- arch/arm64/boot/dts/renesas/condor-common.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/draak.dtsi | 2 +- arch/arm64/boot/dts/renesas/ebisu.dtsi | 2 +- arch/arm64/boot/dts/renesas/hihope-rev4.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 4 ++-- arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 4 ++-- arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 4 ++-- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 4 ++-- arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 +- 10 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index d40a7224f9c3..af6d15f90c65 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -158,7 +158,7 @@ reg = <0x51>; }; - versaclock5: versaclock_som@6a { + versaclock5: versaclock-som@6a { compatible = "idt,5p49v6965"; reg = <0x6a>; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi index 38d486e7b8c3..6b22cc0b05b1 100644 --- a/arch/arm64/boot/dts/renesas/condor-common.dtsi +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -501,7 +501,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -509,7 +509,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 733a55f77cfb..c83c97d99113 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -660,7 +660,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index adc4449b809a..692a2b12aa03 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -765,7 +765,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi index deb69c272775..8bfc66b8ef86 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi @@ -50,7 +50,7 @@ pinctrl-names = "default"; status = "okay"; - cs2000: clk_multiplier@4f { + cs2000: clk-multiplier@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index b7328f9f7d4b..b26c5a709777 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -364,7 +364,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -372,7 +372,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index f18d26360610..343f9610f892 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -255,7 +255,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -263,7 +263,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index 87a9bb44cad6..e3725304fed0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -236,7 +236,7 @@ reg = <0x00040000 0x080000>; read-only; }; - cert_header_sa3@c0000 { + cert-header-sa3@c0000 { reg = <0x000c0000 0x080000>; read-only; }; @@ -244,7 +244,7 @@ reg = <0x00140000 0x040000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index fa8bfee07b3c..d4a921bed4c3 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -501,7 +501,7 @@ }; }; - cs2000: clk_multiplier@4f { + cs2000: clk-multiplier@4f { #clock-cells = <0>; compatible = "cirrus,cs2000-cp"; reg = <0x4f>; @@ -890,7 +890,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a9e53b36f1d9..241caf737abb 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -413,7 +413,7 @@ reg = <0x00040000 0x140000>; read-only; }; - cert_header_sa6@180000 { + cert-header-sa6@180000 { reg = <0x00180000 0x040000>; read-only; }; From 2b84bd93eda9f08ab57cd4322387fc0ca44a9fb9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:24:00 +0100 Subject: [PATCH 483/757] arm64: dts: renesas: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20251223152358.152533-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 52 +++++++++---------- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 52 +++++++++---------- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 52 +++++++++---------- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 52 +++++++++---------- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 52 +++++++++---------- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 52 +++++++++---------- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 52 +++++++++---------- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 +- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 +- .../dts/renesas/r9a09g057h44-rzv2h-evk.dts | 2 +- .../boot/dts/renesas/r9a09g057h48-kakip.dts | 2 +- 11 files changed, 186 insertions(+), 186 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index f0729a482cef..36675f5bcdea 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1901,7 +1901,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1909,7 +1909,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1921,7 +1921,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1929,23 +1929,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1957,27 +1957,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2001,15 +2001,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2021,19 +2021,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2065,7 +2065,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2077,19 +2077,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index c9857ea944ed..ceef0104f75e 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1785,7 +1785,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1793,7 +1793,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1805,7 +1805,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1813,23 +1813,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1841,27 +1841,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -1885,15 +1885,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -1905,19 +1905,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -1949,7 +1949,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -1961,19 +1961,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 52920a6bf592..9df5f1a42400 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1944,7 +1944,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1952,7 +1952,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1964,7 +1964,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1972,23 +1972,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2000,27 +2000,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2044,15 +2044,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2064,19 +2064,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2108,7 +2108,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2120,19 +2120,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 9ad700bde4ba..607f62a448d8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2176,7 +2176,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -2184,7 +2184,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2196,7 +2196,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2204,23 +2204,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2232,27 +2232,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2276,15 +2276,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2296,19 +2296,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2340,7 +2340,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2352,19 +2352,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index e03b1f7cbfd6..e64c7b1aebc4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2101,7 +2101,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -2109,7 +2109,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2121,7 +2121,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2129,23 +2129,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2157,27 +2157,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2201,15 +2201,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2221,19 +2221,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2265,7 +2265,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2277,19 +2277,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 31b11bdab69b..89f6c052c5e0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1981,7 +1981,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1989,7 +1989,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -2001,7 +2001,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -2009,23 +2009,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -2037,27 +2037,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2081,15 +2081,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2101,19 +2101,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2145,7 +2145,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2157,19 +2157,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 4e730144e5fd..425561e658ca 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1911,7 +1911,7 @@ dma-names = "rx", "tx"; }; ssiu04: ssiu-4 { - dmas = <&audma0 0x3F>, <&audma1 0x40>; + dmas = <&audma0 0x3f>, <&audma1 0x40>; dma-names = "rx", "tx"; }; ssiu05: ssiu-5 { @@ -1919,7 +1919,7 @@ dma-names = "rx", "tx"; }; ssiu06: ssiu-6 { - dmas = <&audma0 0x4F>, <&audma1 0x50>; + dmas = <&audma0 0x4f>, <&audma1 0x50>; dma-names = "rx", "tx"; }; ssiu07: ssiu-7 { @@ -1931,7 +1931,7 @@ dma-names = "rx", "tx"; }; ssiu11: ssiu-9 { - dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dmas = <&audma0 0x4b>, <&audma1 0x4c>; dma-names = "rx", "tx"; }; ssiu12: ssiu-10 { @@ -1939,23 +1939,23 @@ dma-names = "rx", "tx"; }; ssiu13: ssiu-11 { - dmas = <&audma0 0x59>, <&audma1 0x5A>; + dmas = <&audma0 0x59>, <&audma1 0x5a>; dma-names = "rx", "tx"; }; ssiu14: ssiu-12 { - dmas = <&audma0 0x5F>, <&audma1 0x60>; + dmas = <&audma0 0x5f>, <&audma1 0x60>; dma-names = "rx", "tx"; }; ssiu15: ssiu-13 { - dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dmas = <&audma0 0xc3>, <&audma1 0xc4>; dma-names = "rx", "tx"; }; ssiu16: ssiu-14 { - dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dmas = <&audma0 0xc7>, <&audma1 0xc8>; dma-names = "rx", "tx"; }; ssiu17: ssiu-15 { - dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dmas = <&audma0 0xcb>, <&audma1 0xcc>; dma-names = "rx", "tx"; }; ssiu20: ssiu-16 { @@ -1967,27 +1967,27 @@ dma-names = "rx", "tx"; }; ssiu22: ssiu-18 { - dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dmas = <&audma0 0x6b>, <&audma1 0x6c>; dma-names = "rx", "tx"; }; ssiu23: ssiu-19 { - dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dmas = <&audma0 0x6d>, <&audma1 0x6e>; dma-names = "rx", "tx"; }; ssiu24: ssiu-20 { - dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dmas = <&audma0 0xcf>, <&audma1 0xce>; dma-names = "rx", "tx"; }; ssiu25: ssiu-21 { - dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dmas = <&audma0 0xeb>, <&audma1 0xec>; dma-names = "rx", "tx"; }; ssiu26: ssiu-22 { - dmas = <&audma0 0xED>, <&audma1 0xEE>; + dmas = <&audma0 0xed>, <&audma1 0xee>; dma-names = "rx", "tx"; }; ssiu27: ssiu-23 { - dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dmas = <&audma0 0xef>, <&audma1 0xf0>; dma-names = "rx", "tx"; }; ssiu30: ssiu-24 { @@ -2011,15 +2011,15 @@ dma-names = "rx", "tx"; }; ssiu35: ssiu-29 { - dmas = <&audma0 0x29>, <&audma1 0x2A>; + dmas = <&audma0 0x29>, <&audma1 0x2a>; dma-names = "rx", "tx"; }; ssiu36: ssiu-30 { - dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dmas = <&audma0 0x2b>, <&audma1 0x2c>; dma-names = "rx", "tx"; }; ssiu37: ssiu-31 { - dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dmas = <&audma0 0x2d>, <&audma1 0x2e>; dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { @@ -2031,19 +2031,19 @@ dma-names = "rx", "tx"; }; ssiu42: ssiu-34 { - dmas = <&audma0 0x19>, <&audma1 0x1A>; + dmas = <&audma0 0x19>, <&audma1 0x1a>; dma-names = "rx", "tx"; }; ssiu43: ssiu-35 { - dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dmas = <&audma0 0x1b>, <&audma1 0x1c>; dma-names = "rx", "tx"; }; ssiu44: ssiu-36 { - dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dmas = <&audma0 0x1d>, <&audma1 0x1e>; dma-names = "rx", "tx"; }; ssiu45: ssiu-37 { - dmas = <&audma0 0x1F>, <&audma1 0x20>; + dmas = <&audma0 0x1f>, <&audma1 0x20>; dma-names = "rx", "tx"; }; ssiu46: ssiu-38 { @@ -2075,7 +2075,7 @@ dma-names = "rx", "tx"; }; ssiu91: ssiu-45 { - dmas = <&audma0 0x7F>, <&audma1 0x80>; + dmas = <&audma0 0x7f>, <&audma1 0x80>; dma-names = "rx", "tx"; }; ssiu92: ssiu-46 { @@ -2087,19 +2087,19 @@ dma-names = "rx", "tx"; }; ssiu94: ssiu-48 { - dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dmas = <&audma0 0xa3>, <&audma1 0xa4>; dma-names = "rx", "tx"; }; ssiu95: ssiu-49 { - dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dmas = <&audma0 0xa5>, <&audma1 0xa6>; dma-names = "rx", "tx"; }; ssiu96: ssiu-50 { - dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dmas = <&audma0 0xa7>, <&audma1 0xa8>; dma-names = "rx", "tx"; }; ssiu97: ssiu-51 { - dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dmas = <&audma0 0xa9>, <&audma1 0xaa>; dma-names = "rx", "tx"; }; }; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index bd52d60bafb9..29273da81995 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1371,7 +1371,7 @@ wdt1: watchdog@12800c00 { compatible = "renesas,r9a07g044-wdt", "renesas,rzg2l-wdt"; - reg = <0 0x12800C00 0 0x400>; + reg = <0 0x12800c00 0 0x400>; clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, <&cpg CPG_MOD R9A07G044_WDT1_CLK>; clock-names = "pclk", "oscclk"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 4e0256d3201d..0dee48c4f1e4 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1379,7 +1379,7 @@ wdt1: watchdog@12800c00 { compatible = "renesas,r9a07g054-wdt", "renesas,rzg2l-wdt"; - reg = <0 0x12800C00 0 0x400>; + reg = <0 0x12800c00 0 0x400>; clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, <&cpg CPG_MOD R9A07G054_WDT1_CLK>; clock-names = "pclk", "oscclk"; diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 962a544fc50a..dc4577ebf2e9 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -61,7 +61,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x1 0xF8000000>; + reg = <0x0 0x48000000 0x1 0xf8000000>; }; memory@240000000 { diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts index e8523bb6705a..3028ed406306 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dts @@ -27,7 +27,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x1 0xF8000000>; + reg = <0x0 0x48000000 0x1 0xf8000000>; }; reg_1p8v: regulator-1p8v { From c3f6d533b76e27a6dd4264b0240f7742a4d79323 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 12 Jan 2026 16:55:42 +0800 Subject: [PATCH 484/757] arm64: dts: mediatek: mt8188-geralt: drop firmware-name from first SCP core Arnd pointed out that having firmware-name in the device tree is wrong. Drop it. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi index 7fedbacdac44..8e423504ec05 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi @@ -1166,7 +1166,6 @@ &scp_c0 { pinctrl-names = "default"; pinctrl-0 = <&scp_pins>; - firmware-name = "mediatek/mt8188/scp.img"; memory-region = <&scp_mem_reserved>; status = "okay"; }; From c68a509320a635f5bfa6c43d0c91c964a8fa678f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:37 +0100 Subject: [PATCH 485/757] arm64: dts: mediatek: mt8173: Fix pinctrl node names and cleanup Fix the pinctrl node names to adhere to the bindings, as the main pin node is supposed to be named like "uart0-pins" and the pinmux node named like "pins-bus". While at it, also cleanup all of the MTK_DRIVE_(x)mA by changing that to just the (x) number. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8173-elm-hana.dtsi | 34 ++--- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 138 +++++++++--------- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 60 ++++---- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 28 ++-- 4 files changed, 128 insertions(+), 132 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi index dfc5c2f0ddef..1004eb8ea52c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -5,6 +5,14 @@ #include "mt8173-elm.dtsi" +&hdmi_mux_pins { + pins-mux { + pinmux = ; + bias-pull-up; + output-high; + }; +}; + &i2c0 { clock-frequency = <200000>; }; @@ -67,26 +75,16 @@ }; }; -&mmc1 { - wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; +&mmc1_pins_default { + pins-wp { + pinmux = ; + input-enable; + bias-pull-up; + }; }; -&pio { - hdmi_mux_pins: hdmi_mux_pins { - pins2 { - pinmux = ; - bias-pull-up; - output-high; - }; - }; - - mmc1_pins_default: mmc1default { - pins_wp { - pinmux = ; - input-enable; - bias-pull-up; - }; - }; +&mmc1 { + wp-gpios = <&pio 42 GPIO_ACTIVE_HIGH>; }; &touchscreen { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 0d995b342d46..9ec930058b92 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -601,8 +601,8 @@ "SOC_I2C4_1V8_SDA_400K", "SOC_I2C4_1V8_SCL_400K"; - aud_i2s2: aud_i2s2 { - pins1 { + aud_i2s2: aud-i2s2-pins { + pins-bus { pinmux = , , , @@ -614,55 +614,55 @@ }; }; - bl_fixed_pins: bl_fixed_pins { - pins1 { + bl_fixed_pins: backlight-pins { + pins-blon { pinmux = ; output-low; }; }; - bt_wake_pins: bt_wake_pins { - pins1 { + bt_wake_pins: bt-pins { + pins-wake { pinmux = ; bias-pull-up; }; }; - disp_pwm0_pins: disp_pwm0_pins { + disp_pwm0_pins: disp-pwm0-pins { pins1 { pinmux = ; output-low; }; }; - gpio_keys_pins: gpio_keys_pins { - volume_pins { + gpio_keys_pins: gpio-keys-pins { + pins-volumeupdn { pinmux = , ; bias-pull-up; }; - tablet_mode_pins { + pins-tabletmode { pinmux = ; bias-pull-up; }; }; - hdmi_mux_pins: hdmi_mux_pins { - pins1 { + hdmi_mux_pins: hdmi-pins { + pins-mux { pinmux = ; }; }; - i2c1_pins_a: i2c1 { - da9211_pins { + i2c1_pins_a: i2c1-pins { + pins-da9211 { pinmux = ; bias-pull-up; }; }; - mmc0_pins_default: mmc0default { - pins_cmd_dat { + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { pinmux = , , , @@ -675,68 +675,68 @@ bias-pull-up; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; - mmc1_pins_default: mmc1default { - pins_cmd_dat { + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { pinmux = , , , , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; - drive-strength = ; + drive-strength = <4>; }; - pins_insert { + pins-insert { pinmux = ; bias-pull-up; }; }; - mmc3_pins_default: mmc3default { - pins_dat { + mmc3_pins_default: mmc3-default-pins { + pins-dat { pinmux = , , , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; - pins_cmd { + pins-cmd { pinmux = ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; - drive-strength = ; + drive-strength = <8>; }; }; - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { pinmux = , , , @@ -747,109 +747,109 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; - pins_ds { + pins-ds { pinmux = ; drive-strength = ; bias-pull-down = ; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { + mmc1_pins_uhs: mmc1-pins { + pins-cmd-dat { pinmux = , , , , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; }; - mmc3_pins_uhs: mmc3 { - pins_dat { + mmc3_pins_uhs: mmc3-pins { + pins-dat { pinmux = , , , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; - pins_cmd { + pins-cmd { pinmux = ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; }; - nor_gpio1_pins: nor { + nor_gpio1_pins: nor-pins { pins1 { pinmux = , , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up; }; pins2 { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-up; }; - pins_clk { + pins-clk { pinmux = ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up; }; }; - panel_backlight_en_pins: panel_backlight_en_pins { + panel_backlight_en_pins: panel-backlight-en-pins { pins1 { pinmux = ; }; }; - panel_fixed_pins: panel_fixed_pins { + panel_fixed_pins: panel-fixed-pins { pins1 { pinmux = ; }; }; - ps8640_pins: ps8640_pins { + ps8640_pins: ps8640-pins { pins1 { pinmux = , , @@ -857,33 +857,33 @@ }; }; - ps8640_fixed_pins: ps8640_fixed_pins { + ps8640_fixed_pins: ps8640-fixed-pins { pins1 { pinmux = ; }; }; - rt5650_irq: rt5650_irq { - pins1 { + rt5650_irq: rt5650-pins { + pins-intn { pinmux = ; bias-pull-down; }; }; - sdio_fixed_3v3_pins: sdio_fixed_3v3_pins { + sdio_fixed_3v3_pins: sdio-vreg-3v3-pins { pins1 { pinmux = ; output-low; }; }; - spi_pins_a: spi1 { + spi_pins_a: spi1-pins { pins1 { pinmux = ; bias-pull-up; }; - pins_spi { + pins-spi { pinmux = , , , @@ -892,15 +892,15 @@ }; }; - trackpad_irq: trackpad_irq { - pins1 { + trackpad_irq: trackpad-pins { + pins-intn { pinmux = ; input-enable; bias-pull-up; }; }; - usb_pins: usb { + usb_pins: usb-pins { pins1 { pinmux = ; output-high; @@ -908,8 +908,8 @@ }; }; - wifi_wake_pins: wifi_wake_pins { - pins1 { + wifi_wake_pins: wifi-pins { + pins-wake { pinmux = ; bias-pull-up; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 9fffed0ef4bf..51118a4149d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -172,15 +172,15 @@ }; &pio { - disp_pwm0_pins: disp_pwm0_pins { + disp_pwm0_pins: disp-pwm0-pins { pins1 { pinmux = ; output-low; }; }; - mmc0_pins_default: mmc0default { - pins_cmd_dat { + mmc0_pins_default: mmc0-default-pins { + pins-cmd-dat { pinmux = , , , @@ -194,19 +194,19 @@ bias-pull-up; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; - mmc1_pins_default: mmc1default { - pins_cmd_dat { + mmc1_pins_default: mmc1-default-pins { + pins-cmd-dat { pinmux = , , , @@ -217,20 +217,20 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; bias-pull-down; drive-strength = <4>; }; - pins_insert { + pins-insert { pinmux = ; bias-pull-up; }; }; - mmc0_pins_uhs: mmc0 { - pins_cmd_dat { + mmc0_pins_uhs: mmc0-uhs-pins { + pins-cmd-dat { pinmux = , , , @@ -245,20 +245,29 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; drive-strength = <2>; bias-pull-down = ; }; - pins_rst { + pins-rst { pinmux = ; bias-pull-up; }; }; - mmc1_pins_uhs: mmc1 { - pins_cmd_dat { + spi_pins_a: spi0-pins { + pins-bus { + pinmux = , + , + , + ; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-cmd-dat { pinmux = , , , @@ -269,22 +278,22 @@ bias-pull-up = ; }; - pins_clk { + pins-clk { pinmux = ; drive-strength = <4>; bias-pull-down = ; }; }; - usb_id_pins_float: usb_iddig_pull_up { - pins_iddig { + usb_id_pins_float: usb-iddig-pu-pins { + pins-iddig-pu { pinmux = ; bias-pull-up; }; }; - usb_id_pins_ground: usb_iddig_pull_down { - pins_iddig { + usb_id_pins_ground: usb-iddig-pd-pins { + pins-iddig-pd { pinmux = ; bias-pull-down; }; @@ -473,17 +482,6 @@ }; }; -&pio { - spi_pins_a: spi0 { - pins_spi { - pinmux = , - , - , - ; - }; - }; -}; - &spi { pinctrl-names = "default"; pinctrl-0 = <&spi_pins_a>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 122a57c3780b..78c2ccd5be13 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -391,58 +391,58 @@ , ; - hdmi_pin: xxx { + hdmi_pin: hdmi-hotplug-pins { /*hdmi htplg pin*/ - pins1 { + pins-htplg { pinmux = ; input-enable; bias-pull-down; }; }; - i2c0_pins_a: i2c0 { - pins1 { + i2c0_pins_a: i2c0-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c1_pins_a: i2c1 { - pins1 { + i2c1_pins_a: i2c1-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c2_pins_a: i2c2 { - pins1 { + i2c2_pins_a: i2c2-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c3_pins_a: i2c3 { - pins1 { + i2c3_pins_a: i2c3-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c4_pins_a: i2c4 { - pins1 { + i2c4_pins_a: i2c4-pins { + pins-bus { pinmux = , ; bias-disable; }; }; - i2c6_pins_a: i2c6 { - pins1 { + i2c6_pins_a: i2c6-pins { + pins-bus { pinmux = , ; bias-disable; From 846348a699f9cf9fba4188870b929f88e7556cc1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:39 +0100 Subject: [PATCH 486/757] arm64: dts: mediatek: mt8183-evb: Fix dtbs_check warnings Change the Murata NCM03WF104 node name from "thermal-sensor" to "thermistor" (as that's what it is, after all), and change all of the pinmux main nodes to have a "-pins" suffix to satisfy devicetree bindings checks. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++++++++++----------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index f04baea5d6cb..acfdd5fb041f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -38,7 +38,7 @@ }; }; - thermal-sensor { + thermistor { compatible = "murata,ncp03wf104"; pullup-uv = <1800000>; pullup-ohm = <390000>; @@ -155,7 +155,7 @@ }; &pio { - i2c_pins_0: i2c0 { + i2c_pins_0: i2c0-pins { pins_i2c { pinmux = , ; @@ -163,7 +163,7 @@ }; }; - i2c_pins_1: i2c1 { + i2c_pins_1: i2c1-pins { pins_i2c { pinmux = , ; @@ -171,7 +171,7 @@ }; }; - i2c_pins_2: i2c2 { + i2c_pins_2: i2c2-pins { pins_i2c { pinmux = , ; @@ -179,7 +179,7 @@ }; }; - i2c_pins_3: i2c3 { + i2c_pins_3: i2c3-pins { pins_i2c { pinmux = , ; @@ -187,7 +187,7 @@ }; }; - i2c_pins_4: i2c4 { + i2c_pins_4: i2c4-pins { pins_i2c { pinmux = , ; @@ -195,7 +195,7 @@ }; }; - i2c_pins_5: i2c5 { + i2c_pins_5: i2c5-pins { pins_i2c { pinmux = , ; @@ -203,7 +203,7 @@ }; }; - spi_pins_0: spi0 { + spi_pins_0: spi0-pins { pins_spi { pinmux = , , @@ -213,7 +213,7 @@ }; }; - mmc0_pins_default: mmc0default { + mmc0_pins_default: mmc0-default-pins { pins_cmd_dat { pinmux = , , @@ -239,7 +239,7 @@ }; }; - mmc0_pins_uhs: mmc0 { + mmc0_pins_uhs: mmc0-uhs-pins { pins_cmd_dat { pinmux = , , @@ -274,7 +274,7 @@ }; }; - mmc1_pins_default: mmc1default { + mmc1_pins_default: mmc1-default-pins { pins_cmd_dat { pinmux = , , @@ -298,7 +298,7 @@ }; }; - mmc1_pins_uhs: mmc1 { + mmc1_pins_uhs: mmc1-pins { pins_cmd_dat { pinmux = , , @@ -318,7 +318,7 @@ }; }; - spi_pins_1: spi1 { + spi_pins_1: spi1-pins { pins_spi { pinmux = , , @@ -328,7 +328,7 @@ }; }; - spi_pins_2: spi2 { + spi_pins_2: spi2-pins { pins_spi { pinmux = , , @@ -338,7 +338,7 @@ }; }; - spi_pins_3: spi3 { + spi_pins_3: spi3-pins { pins_spi { pinmux = , , @@ -348,7 +348,7 @@ }; }; - spi_pins_4: spi4 { + spi_pins_4: spi4-pins { pins_spi { pinmux = , , @@ -358,7 +358,7 @@ }; }; - spi_pins_5: spi5 { + spi_pins_5: spi5-pins { pins_spi { pinmux = , , @@ -368,7 +368,7 @@ }; }; - pwm_pins_1: pwm1 { + pwm_pins_1: pwm1-pins { pins_pwm { pinmux = ; }; From 55828e41e7398b630b036eabf3329828706491a0 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:40 +0100 Subject: [PATCH 487/757] arm64: dts: mediatek: mt7981b-openwrt-one: Remove useless cells from flash@0 In spi2's flash@0 there is only one `partitions` subnode: this alone makes specifying address and size cells useless, but then this subnode has no address and no size, which even makes the currently declared address/size cells wrong. Fixes: 869b3bb5ada2 ("arm64: dts: mediatek: mt7981b-openwrt-one: Enable SPI NOR") Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 3de368c73bc8..48b80af90438 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -213,8 +213,6 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <40000000>; - #address-cells = <1>; - #size-cells = <1>; partitions { compatible = "fixed-partitions"; From b1fc81a986c9b8089db31e21a372cc8b6514e900 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:41 +0100 Subject: [PATCH 488/757] arm64: dts: mediatek: mt8183-jacuzzi-pico6: Fix typo in pinmux node Rename "piins-bt-wakeup" to "pins-bt-wakeup" to fix a dtbs_check warning happening due to this typo. Fixes: 055ef10ccdd4 ("arm64: dts: mt8183: Add jacuzzi pico/pico6 board") Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts index cce326aec1aa..40af5656d6f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -91,7 +91,7 @@ &pio { bt_pins_wakeup: bt-pins-wakeup { - piins-bt-wakeup { + pins-bt-wakeup { pinmux = ; input-enable; }; From 08076645d9ac216b5d78930f52d4fc4d6807cd22 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:42 +0100 Subject: [PATCH 489/757] arm64: dts: mediatek: mt8183-pumpkin: Fix pinmux node names Change all of the pinmux main nodes to have a "-pins" suffix to satisfy devicetree bindings checks. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index f60ef3e53a09..e47955602c83 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -241,7 +241,7 @@ }; &pio { - i2c_pins_0: i2c0 { + i2c_pins_0: i2c0-pins { pins_i2c { pinmux = , ; @@ -249,7 +249,7 @@ }; }; - i2c_pins_1: i2c1 { + i2c_pins_1: i2c1-pins { pins_i2c { pinmux = , ; @@ -257,7 +257,7 @@ }; }; - i2c_pins_2: i2c2 { + i2c_pins_2: i2c2-pins { pins_i2c { pinmux = , ; @@ -265,7 +265,7 @@ }; }; - i2c_pins_3: i2c3 { + i2c_pins_3: i2c3-pins { pins_i2c { pinmux = , ; @@ -273,7 +273,7 @@ }; }; - i2c_pins_4: i2c4 { + i2c_pins_4: i2c4-pins { pins_i2c { pinmux = , ; @@ -281,7 +281,7 @@ }; }; - i2c_pins_5: i2c5 { + i2c_pins_5: i2c5-pins { pins_i2c { pinmux = , ; @@ -289,7 +289,7 @@ }; }; - i2c6_pins: i2c6 { + i2c6_pins: i2c6-pins { pins_cmd_dat { pinmux = , ; @@ -297,7 +297,7 @@ }; }; - keyboard_pins: keyboard { + keyboard_pins: keyboard-pins { pins_keyboard { pinmux = , , From 870ffe2999b5b558e2e6bfc7e7c6324130f08e47 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:43 +0100 Subject: [PATCH 490/757] arm64: dts: mediatek: mt8173-elm: Fix bluetooth node name and reorder Change the node name for Marvell SD8897 SDIO Bluetooth from `btmrvl@2` to `bluetooth@2` to fix a dtbs_check warning. While at it, also change the WiFi one from `mwifiex@1" to a generic "wifi@1" and reorder the nodes so that wifi@1 comes before bluetooth@2. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 9ec930058b92..59813fff7833 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -432,20 +432,20 @@ #address-cells = <1>; #size-cells = <0>; - btmrvl: btmrvl@2 { + mwifiex: wifi@1 { + compatible = "marvell,sd8897"; + reg = <1>; + interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>; + marvell,wakeup-pin = <3>; + }; + + btmrvl: bluetooth@2 { compatible = "marvell,sd8897-bt"; reg = <2>; interrupts-extended = <&pio 119 IRQ_TYPE_LEVEL_LOW>; marvell,wakeup-pin = /bits/ 16 <0x0d>; marvell,wakeup-gap-ms = /bits/ 16 <0x64>; }; - - mwifiex: mwifiex@1 { - compatible = "marvell,sd8897"; - reg = <1>; - interrupts-extended = <&pio 38 IRQ_TYPE_LEVEL_LOW>; - marvell,wakeup-pin = <3>; - }; }; &nor_flash { From 6c0ecd0ae8f64b8d70ba3522ef6903753425e2c4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:44 +0100 Subject: [PATCH 491/757] arm64: dts: mediatek: mt8173-elm: Fix dsi0 ports warning Since only a single port is present, remove the inner `ports` parent node and just declare the single port as `port`. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 59813fff7833..dc064cdcedb5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -206,11 +206,9 @@ &dsi0 { status = "okay"; - ports { - port { - dsi0_out: endpoint { - remote-endpoint = <&ps8640_in>; - }; + port { + dsi0_out: endpoint { + remote-endpoint = <&ps8640_in>; }; }; }; From 04ccbc5325ccd2b96ef5c3dde1a50495980404c8 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:45 +0100 Subject: [PATCH 492/757] arm64: dts: mediatek: mt8173-elm: Remove regulators from thermal node The only reason to have a regulator in the thermal node is to keep the CPU cores up while reading temperatures, but this is incorrect because the AUXADC Thermal IP doesn't need any regulators to work, at all. Since the thermal node was inherited only for adding vregs, remove it entirely. This change is safe also because, among other things, the actual driver never used those regulators anyway. This also fixes a dtbs_check warning. Reviewed-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index dc064cdcedb5..a0573bc359fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1147,11 +1147,6 @@ status = "okay"; }; -&thermal { - bank0-supply = <&mt6397_vpca15_reg>; - bank1-supply = <&da9211_vcpu_reg>; -}; - &uart0 { status = "okay"; }; From 96cb8d6257d65e74f9c91a382f71a830393467a5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:46 +0100 Subject: [PATCH 493/757] arm64: dts: mediatek: mt8192-asurada: Remove unused clock-stretch-ns Remove the clock-stretch-ns property from i2c2, as it has always been (and still is) unused. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 0b4664f044a1..eadf1b2d156f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -344,7 +344,6 @@ status = "okay"; clock-frequency = <400000>; - clock-stretch-ns = <12600>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; From ab3a124fe08948bb217d1e146f4a8ecd066f63d7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 9 Jan 2026 12:47:47 +0100 Subject: [PATCH 494/757] arm64: dts: mediatek: mt6795-xperia-m5: Add UHS pins for MMC1 and 2 Add the UHS state pins for the MMC1 and MMC2 controllers and, while at it, also add the correct drive strength parameters for the default pin states for those two. Reviewed-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt6795-sony-xperia-m5.dts | 48 ++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index fccb948cfa45..ecd13d089ceb 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -227,8 +227,9 @@ &mmc1 { /* MicroSD card slot */ - pinctrl-names = "default"; + pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -236,8 +237,9 @@ &mmc2 { /* SDIO WiFi on MMC2 */ - pinctrl-names = "default"; + pinctrl-names = "default", "state_uhs"; pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_uhs>; vmmc-supply = <&mt6331_vmc_reg>; vqmmc-supply = <&mt6331_vmch_reg>; status = "okay"; @@ -324,11 +326,32 @@ ; input-enable; bias-pull-up = ; + drive-strength = <4>; }; pins-clk { pinmux = ; bias-pull-down = ; + drive-strength = <4>; + }; + }; + + mmc1_pins_uhs: microsd-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + drive-strength = <6>; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + drive-strength = <8>; }; }; @@ -341,11 +364,32 @@ ; input-enable; bias-pull-up = ; + drive-strength = <4>; }; pins-clk { pinmux = ; bias-pull-down = ; + drive-strength = <4>; + }; + }; + + mmc2_pins_uhs: sdio-uhs-pins { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + drive-strength = <8>; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + drive-strength = <8>; }; }; From e9ea7552eb5ebff9f22a8517ac074277b9ddca95 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 9 Jan 2026 16:25:43 +0100 Subject: [PATCH 495/757] arm64: dts: apple: Add chassis-type property for all Macbooks All Macbook Air and Pro devices are laptops so annotate this as chassis-tpe in the root node. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa Reviewed-by: Mark Kettenis Link: https://patch.msgid.link/20260109-apple-dt-chassis-type-v1-1-c215503734c5@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi | 2 ++ arch/arm64/boot/dts/apple/t8103-j293.dts | 1 + arch/arm64/boot/dts/apple/t8103-j313.dts | 1 + arch/arm64/boot/dts/apple/t8112-j413.dts | 1 + arch/arm64/boot/dts/apple/t8112-j415.dts | 1 + arch/arm64/boot/dts/apple/t8112-j493.dts | 1 + 6 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index c0aac59a6fae..15bd157a486c 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -12,6 +12,8 @@ #include / { + chassis-type = "laptop"; + aliases { bluetooth0 = &bluetooth0; serial0 = &serial0; diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index 5b3c42e9f0e6..91cca3000abc 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M1, 2020)"; + chassis-type = "laptop"; /* * All of those are used by the bootloader to pass calibration diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts index 97a4344d8dca..778e482a6fb6 100644 --- a/arch/arm64/boot/dts/apple/t8103-j313.dts +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j313", "apple,t8103", "apple,arm-platform"; model = "Apple MacBook Air (M1, 2020)"; + chassis-type = "laptop"; led-controller { compatible = "pwm-leds"; diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts/apple/t8112-j413.dts index 6f69658623bf..bb9f34e8dc90 100644 --- a/arch/arm64/boot/dts/apple/t8112-j413.dts +++ b/arch/arm64/boot/dts/apple/t8112-j413.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j413", "apple,t8112", "apple,arm-platform"; model = "Apple MacBook Air (13-inch, M2, 2022)"; + chassis-type = "laptop"; aliases { bluetooth0 = &bluetooth0; diff --git a/arch/arm64/boot/dts/apple/t8112-j415.dts b/arch/arm64/boot/dts/apple/t8112-j415.dts index b54e218e5384..061629e153ea 100644 --- a/arch/arm64/boot/dts/apple/t8112-j415.dts +++ b/arch/arm64/boot/dts/apple/t8112-j415.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j415", "apple,t8112", "apple,arm-platform"; model = "Apple MacBook Air (15-inch, M2, 2023)"; + chassis-type = "laptop"; aliases { bluetooth0 = &bluetooth0; diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts index fb8ad7d4c65a..1f98ab70d7c3 100644 --- a/arch/arm64/boot/dts/apple/t8112-j493.dts +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -16,6 +16,7 @@ / { compatible = "apple,j493", "apple,t8112", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M2, 2022)"; + chassis-type = "laptop"; /* * All of those are used by the bootloader to pass calibration From 5a7277c1bc19624b0644ab3e89b215a1d480e781 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 9 Jan 2026 16:25:44 +0100 Subject: [PATCH 496/757] arm64: dts: apple: Add chassis-type property for Apple desktop devices Apple's Mac mini and Studio are desktop devices. The SMBIOS has chassis types which might be more accurate like "low profile desktop" or "mini pc" but without clear definition what those are use plain "desktop" as chassis-type in the root node. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa Reviewed-by: Mark Kettenis Link: https://patch.msgid.link/20260109-apple-dt-chassis-type-v1-2-c215503734c5@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t600x-j375.dtsi | 2 ++ arch/arm64/boot/dts/apple/t8103-j274.dts | 1 + arch/arm64/boot/dts/apple/t8112-j473.dts | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index c0fb93ae72f4..5bba233b5383 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -10,6 +10,8 @@ */ / { + chassis-type = "desktop"; + aliases { bluetooth0 = &bluetooth0; ethernet0 = ðernet0; diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index 1c3e37f86d46..b379ca25b1b7 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -15,6 +15,7 @@ / { compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; model = "Apple Mac mini (M1, 2020)"; + chassis-type = "desktop"; aliases { ethernet0 = ðernet0; diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts/apple/t8112-j473.dts index 06fe257f08be..a05951e91a02 100644 --- a/arch/arm64/boot/dts/apple/t8112-j473.dts +++ b/arch/arm64/boot/dts/apple/t8112-j473.dts @@ -15,6 +15,7 @@ / { compatible = "apple,j473", "apple,t8112", "apple,arm-platform"; model = "Apple Mac mini (M2, 2023)"; + chassis-type = "desktop"; aliases { ethernet0 = ðernet0; From 126ee92bff557853d15f57997c2cb16c14259c00 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 9 Jan 2026 16:25:45 +0100 Subject: [PATCH 497/757] arm64: dts: apple: Add chassis-type property for Mac Pro The tower and rack mount Mac Pro variants share the same .dts file and are identical except for the chassis. There doesn't appear to be a property in Apple's device tree to distinguish these two devices so use "server" as chassis type which describes both if one doesn't look too carefully. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa Reviewed-by: Mark Kettenis Link: https://patch.msgid.link/20260109-apple-dt-chassis-type-v1-3-c215503734c5@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6022-j180d.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6022-j180d.dts b/arch/arm64/boot/dts/apple/t6022-j180d.dts index dca6bd167c22..55a5e1956389 100644 --- a/arch/arm64/boot/dts/apple/t6022-j180d.dts +++ b/arch/arm64/boot/dts/apple/t6022-j180d.dts @@ -15,6 +15,8 @@ / { compatible = "apple,j180d", "apple,t6022", "apple,arm-platform"; model = "Apple Mac Pro (M2 Ultra, 2023)"; + chassis-type = "server"; + aliases { nvram = &nvram; serial0 = &serial0; From ba9dbb701e9fd3a8411be72ca22dc51f52fa2eee Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 9 Jan 2026 16:25:46 +0100 Subject: [PATCH 498/757] arm64: dts: apple: Add chassis-type property for Apple iMacs Apple iMac (M1, 2021) are all-in-one devices with an integrated display. Signed-off-by: Janne Grunau Reviewed-by: Neal Gompa Reviewed-by: Mark Kettenis Link: https://patch.msgid.link/20260109-apple-dt-chassis-type-v1-4-c215503734c5@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-j456.dts | 1 + arch/arm64/boot/dts/apple/t8103-j457.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts index 58c8e43789b4..2436f0e692e3 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -15,6 +15,7 @@ / { compatible = "apple,j456", "apple,t8103", "apple,arm-platform"; model = "Apple iMac (24-inch, 4x USB-C, M1, 2021)"; + chassis-type = "all-in-one"; aliases { ethernet0 = ðernet0; diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts index 7089ccf3ce55..208171adde12 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -15,6 +15,7 @@ / { compatible = "apple,j457", "apple,t8103", "apple,arm-platform"; model = "Apple iMac (24-inch, 2x USB-C, M1, 2021)"; + chassis-type = "all-in-one"; aliases { ethernet0 = ðernet0; From 3e4e729325131fe6f7473a0673f7d8cdde53f5a0 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 8 Jan 2026 22:04:01 +0100 Subject: [PATCH 499/757] arm64: dts: apple: t8112-j473: Keep the HDMI port powered on Add the display controller and DPTX phy power-domains to the framebuffer node to keep the framebuffer and display out working after device probing finished. The OS has more control about the display pipeline used for the HDMI output on M2 based devices. The HDMI output is driven by an integrated DisplayPort to HDMI converter (Parade PS190). The DPTX phy is now controlled by the OS and no longer by firmware running on the display co-processor. This allows using the second display controller on the second USB type-c port or tunneling 2 DisplayPort connections over USB4/Thunderbolt. The m1n1 bootloader uses the second display controller to drive the HDMI output. Adjust for this difference compared to the notebooks as well. Fixes: 2d5ce3fbef32 ("arm64: dts: apple: t8112: Initial t8112 (M2) device trees") Cc: stable@vger.kernel.org Signed-off-by: Janne Grunau Link: https://patch.msgid.link/20260108-apple-dt-pmgr-fixes-v1-1-cfdce629c0a8@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8112-j473.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts/apple/t8112-j473.dts index a05951e91a02..bfa959023a0d 100644 --- a/arch/arm64/boot/dts/apple/t8112-j473.dts +++ b/arch/arm64/boot/dts/apple/t8112-j473.dts @@ -22,6 +22,25 @@ }; }; +/* + * Keep the power-domains used for the HDMI port on. + */ +&framebuffer0 { + power-domains = <&ps_dispext_cpu0>, <&ps_dptx_ext_phy>; +}; + +/* + * The M2 Mac mini uses dispext for the HDMI output so it's not necessary to + * keep disp0 power-domains always-on. + */ +&ps_disp0_sys { + /delete-property/ apple,always-on; +}; + +&ps_disp0_fe { + /delete-property/ apple,always-on; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader From 54347056828d9a0d92c1696cf1571a3ed4b6010f Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Thu, 8 Jan 2026 22:04:02 +0100 Subject: [PATCH 500/757] arm64: dts: apple: t8103: Mark ATC USB AON domains as always-on Shutting these down breaks dwc3 init done by the firmware. We probably never want to do this anyway. "always-on" is a plausible interpretation of the "aon" suffix. The t8112, t600x and t602x "ps_atc?_usb_aon" power-controller nodes are have already "apple,always-on" properties. Signed-off-by: Hector Martin Signed-off-by: Janne Grunau Link: https://patch.msgid.link/20260108-apple-dt-pmgr-fixes-v1-2-cfdce629c0a8@jannau.net [sven: removed stale comment about PHY from commit message] Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi index c41c57d63997..4bfe0d2de30a 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -1103,6 +1103,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = "atc0_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ }; ps_atc1_usb_aon: power-controller@90 { @@ -1111,6 +1112,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = "atc1_usb_aon"; + apple,always-on; /* Needs to stay on for dwc3 to work */ }; ps_atc0_usb: power-controller@98 { From 84220bfe9b794c051f927e1374c90ce288295b96 Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Thu, 8 Jan 2026 22:04:03 +0100 Subject: [PATCH 501/757] arm64: dts: apple: t8103: Add ps_pmp dependency to ps_gfx AGX appears to have a hidden communication channel to pmp, a power management related co-processor already brought up by Apple's bootloader. As there is not driver for this co-processor its power-domain gets shut down after the initial boot. This crashes the firmware running on AGX immediately. Until there is a pmp driver and the dependency between AGX and pmp is understood keep "ps_pmp" as dependency of "ps_gfx". Signed-off-by: Janne Grunau Link: https://patch.msgid.link/20260108-apple-dt-pmgr-fixes-v1-3-cfdce629c0a8@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-pmgr.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi index 4bfe0d2de30a..fef8a4058f14 100644 --- a/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-pmgr.dtsi @@ -733,6 +733,7 @@ #power-domain-cells = <0>; #reset-cells = <0>; label = "gfx"; + power-domains = <&ps_pmp>; }; ps_dcs4: power-controller@320 { From 2b737cc5be70b280cd6f8e25c306bc94d4189b41 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Fri, 9 Jan 2026 15:07:04 +0100 Subject: [PATCH 502/757] arm64: dts: apple: t8103: Add nodes for integrated USB Type-C ports Add device nodes and connections to support USB 3.x on the SoC's integrated USB-C ports of M1-based devices. Each Type-C port has an Apple Type-C PHY for USB 2.0, USB 3.x, USB4/Thunderbolt, and DisplayPort, a Synopsys Designware USB 3.x controller, two DART iommu instances and a CD321x USB PD controller. The iMac variant with four USB-C ports has two SoC integrated USB-C ports and two additional USB-C ports driven by an AsMedia PCIe USB controller. The latter ports are not covered by this change. The port labels use Apple's established naming scheme for the ports. Signed-off-by: Hector Martin Co-developed-by: Sven Peter Signed-off-by: Janne Grunau Tested-by: Sven Peter # M1 mac mini and macbook air Reviewed-by: Sven Peter Reviewed-by: Neal Gompa Link: https://patch.msgid.link/20260109-apple-dt-usb-c-atc-dwc3-v1-1-ce0e92c1a016@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-j274.dts | 12 ++ arch/arm64/boot/dts/apple/t8103-j293.dts | 12 ++ arch/arm64/boot/dts/apple/t8103-j313.dts | 12 ++ arch/arm64/boot/dts/apple/t8103-j456.dts | 12 ++ arch/arm64/boot/dts/apple/t8103-j457.dts | 12 ++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 134 ++++++++++++++++++++++ arch/arm64/boot/dts/apple/t8103.dtsi | 105 +++++++++++++++++ 7 files changed, 299 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts/apple/t8103-j274.dts index 1c3e37f86d46..968fe22163d4 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -29,6 +29,18 @@ brcm,board-type = "apple,atlantisb"; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Back-left"; +}; + +&typec1 { + label = "USB-C Back-right"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts/apple/t8103-j293.dts index 5b3c42e9f0e6..678f89c3d47f 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -46,6 +46,18 @@ brcm,board-type = "apple,honshu"; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; + &i2c2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts/apple/t8103-j313.dts index 97a4344d8dca..bce9b911009e 100644 --- a/arch/arm64/boot/dts/apple/t8103-j313.dts +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -41,3 +41,15 @@ &fpwm1 { status = "okay"; }; + +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts/apple/t8103-j456.dts index 58c8e43789b4..9983e11cacdf 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -47,6 +47,18 @@ }; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Back-right"; +}; + +&typec1 { + label = "USB-C Back-right-middle"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts/apple/t8103-j457.dts index 7089ccf3ce55..6703f4a3d3db 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -37,6 +37,18 @@ brcm,board-type = "apple,santorini"; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Back-right"; +}; + +&typec1 { + label = "USB-C Back-left"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi index 0c8206156bfe..686fb1dd215d 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -15,6 +15,8 @@ serial0 = &serial0; serial2 = &serial2; wifi0 = &wifi0; + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; }; chosen { @@ -53,6 +55,29 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <106 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -61,6 +86,115 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <106 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 8b7b27887968..c48b10ac65ef 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "apple,t8103", "apple,arm-platform"; @@ -1007,6 +1008,110 @@ resets = <&ps_ans2>; }; + dwc3_0: usb@382280000 { + compatible = "apple,t8103-dwc3"; + reg = <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + power-domains = <&ps_atc0_usb>; + resets = <&atcphy0>; + phys = <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + dwc3_0_dart_0: iommu@382f00000 { + compatible = "apple,t8103-dart"; + reg = <0x3 0x82f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_atc0_usb>; + }; + + dwc3_0_dart_1: iommu@382f80000 { + compatible = "apple,t8103-dart"; + reg = <0x3 0x82f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_atc0_usb>; + }; + + atcphy0: phy@383000000 { + compatible = "apple,t8103-atcphy"; + reg = <0x3 0x83000000 0x0 0x4c000>, + <0x3 0x83050000 0x0 0x8000>, + <0x3 0x80000000 0x0 0x4000>, + <0x3 0x82a90000 0x0 0x4000>, + <0x3 0x82a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&ps_atc0_usb>; + }; + + dwc3_1: usb@502280000 { + compatible = "apple,t8103-dwc3"; + reg = <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; + power-domains = <&ps_atc1_usb>; + resets = <&atcphy1>; + phys = <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + dwc3_1_dart_0: iommu@502f00000 { + compatible = "apple,t8103-dart"; + reg = <0x5 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_atc1_usb>; + }; + + dwc3_1_dart_1: iommu@502f80000 { + compatible = "apple,t8103-dart"; + reg = <0x5 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_atc1_usb>; + }; + + atcphy1: phy@503000000 { + compatible = "apple,t8103-atcphy"; + reg = <0x5 0x03000000 0x0 0x4c000>, + <0x5 0x03050000 0x0 0x8000>, + <0x5 0x0 0x0 0x4000>, + <0x5 0x02a90000 0x0 0x4000>, + <0x5 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&ps_atc1_usb>; + }; + pcie0_dart_0: iommu@681008000 { compatible = "apple,t8103-dart"; reg = <0x6 0x81008000 0x0 0x4000>; From b4f4054864e6395672c06efd0bbfcf6777d43c97 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Fri, 9 Jan 2026 15:07:05 +0100 Subject: [PATCH 503/757] arm64: dts: apple: t8112: Add nodes for integrated USB Type-C ports Add device nodes and connections to support USB 3.x on the SoC's integrated USBi Type-C ports of M2-based devices. Each Type-C port has an Apple Type-C PHY for USB 2.0, USB 3.x, USB4/Thunderbolt, and DisplayPort, a Synopsys Designware USB 3.x controller, two DART iommu instances and a CD321x USB PD controller. The port labels use Apple's established naming scheme for the ports. Signed-off-by: Hector Martin Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Tested-by: Sven Peter # M1 mac mini and macbook air Reviewed-by: Sven Peter Reviewed-by: Neal Gompa Link: https://patch.msgid.link/20260109-apple-dt-usb-c-atc-dwc3-v1-2-ce0e92c1a016@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8112-j413.dts | 12 ++ arch/arm64/boot/dts/apple/t8112-j415.dts | 12 ++ arch/arm64/boot/dts/apple/t8112-j473.dts | 12 ++ arch/arm64/boot/dts/apple/t8112-j493.dts | 12 ++ arch/arm64/boot/dts/apple/t8112-jxxx.dtsi | 134 ++++++++++++++++++++++ arch/arm64/boot/dts/apple/t8112.dtsi | 105 +++++++++++++++++ 6 files changed, 287 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8112-j413.dts b/arch/arm64/boot/dts/apple/t8112-j413.dts index 6f69658623bf..21e81a8899d8 100644 --- a/arch/arm64/boot/dts/apple/t8112-j413.dts +++ b/arch/arm64/boot/dts/apple/t8112-j413.dts @@ -60,6 +60,18 @@ }; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; + &i2c0 { /* MagSafe port */ hpm5: usb-pd@3a { diff --git a/arch/arm64/boot/dts/apple/t8112-j415.dts b/arch/arm64/boot/dts/apple/t8112-j415.dts index b54e218e5384..b4f72fbafaf1 100644 --- a/arch/arm64/boot/dts/apple/t8112-j415.dts +++ b/arch/arm64/boot/dts/apple/t8112-j415.dts @@ -60,6 +60,18 @@ }; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; + &i2c0 { /* MagSafe port */ hpm5: usb-pd@3a { diff --git a/arch/arm64/boot/dts/apple/t8112-j473.dts b/arch/arm64/boot/dts/apple/t8112-j473.dts index 06fe257f08be..81994f0a7df9 100644 --- a/arch/arm64/boot/dts/apple/t8112-j473.dts +++ b/arch/arm64/boot/dts/apple/t8112-j473.dts @@ -52,3 +52,15 @@ &pcie2_dart { status = "okay"; }; + +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Back-left"; +}; + +&typec1 { + label = "USB-C Back-right"; +}; diff --git a/arch/arm64/boot/dts/apple/t8112-j493.dts b/arch/arm64/boot/dts/apple/t8112-j493.dts index fb8ad7d4c65a..f8e442152ff2 100644 --- a/arch/arm64/boot/dts/apple/t8112-j493.dts +++ b/arch/arm64/boot/dts/apple/t8112-j493.dts @@ -108,6 +108,18 @@ }; }; +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label = "USB-C Left-back"; +}; + +&typec1 { + label = "USB-C Left-front"; +}; + &i2c4 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi index 6da35496a4c8..562e7a25a1e8 100644 --- a/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8112-jxxx.dtsi @@ -11,6 +11,8 @@ / { aliases { + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; serial0 = &serial0; serial2 = &serial2; }; @@ -53,6 +55,29 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -61,6 +86,115 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t8112.dtsi b/arch/arm64/boot/dts/apple/t8112.dtsi index 3f79878b25af..2d645cdec4a7 100644 --- a/arch/arm64/boot/dts/apple/t8112.dtsi +++ b/arch/arm64/boot/dts/apple/t8112.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include / { @@ -1010,6 +1011,110 @@ resets = <&ps_ans>; }; + dwc3_0: usb@382280000 { + compatible = "apple,t8112-dwc3", "apple,t8103-dwc3"; + reg = <0x3 0x82280000 0x0 0xcd00>, <0x3 0x8228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + power-domains = <&ps_atc0_usb>; + resets = <&atcphy0>; + phys = <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + dwc3_0_dart_0: iommu@382f00000 { + compatible = "apple,t8110-dart"; + reg = <0x3 0x82f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_atc0_usb>; + }; + + dwc3_0_dart_1: iommu@382f80000 { + compatible = "apple,t8110-dart"; + reg = <0x3 0x82f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_atc0_usb>; + }; + + atcphy0: phy@383000000 { + compatible = "apple,t8112-atcphy", "apple,t8103-atcphy"; + reg = <0x3 0x83000000 0x0 0x4c000>, + <0x3 0x83050000 0x0 0x8000>, + <0x3 0x80000000 0x0 0x4000>, + <0x3 0x82a90000 0x0 0x4000>, + <0x3 0x82a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&ps_atc0_usb>; + }; + + dwc3_1: usb@502280000 { + compatible = "apple,t8112-dwc3", "apple,t8103-dwc3"; + reg = <0x5 0x02280000 0x0 0xcd00>, <0x5 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; + power-domains = <&ps_atc1_usb>; + resets = <&atcphy1>; + phys = <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + dwc3_1_dart_0: iommu@502f00000 { + compatible = "apple,t8110-dart"; + reg = <0x5 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_atc1_usb>; + }; + + dwc3_1_dart_1: iommu@502f80000 { + compatible = "apple,t8110-dart"; + reg = <0x5 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_atc1_usb>; + }; + + atcphy1: phy@503000000 { + compatible = "apple,t8112-atcphy", "apple,t8103-atcphy"; + reg = <0x5 0x03000000 0x0 0x4c000>, + <0x5 0x03050000 0x0 0x8000>, + <0x5 0x0 0x0 0x4000>, + <0x5 0x02a90000 0x0 0x4000>, + <0x5 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&ps_atc1_usb>; + }; + pcie0_dart: iommu@681008000 { compatible = "apple,t8110-dart"; reg = <0x6 0x81008000 0x0 0x4000>; From e21c8e2e027633875e874a3bd38318c940416b0f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 9 Jan 2026 15:07:06 +0100 Subject: [PATCH 504/757] arm64: dts: apple: t60xx: Add nodes for integrated USB Type-C ports Add device nodes and connections to support USB 3.x on the SoC's integrated Type-C ports of M1 and M2 Pro, Max and Ultra based devices. Each Type-C port has an Apple Type-C PHY for USB 2.0, USB 3.x, USB4/Thunderbolt, and DisplayPort, a Synopsys Designware USB 3.x controller, two DART iommu instances and a CD321x USB PD controller. M1 and M2 Max based Mac Studio device have two additional USB Type-C ports on the front which are driven by an AsMedia PCIe USB controller and integrated USB hub. These ports are not covered by this change. The port labels use Apple's established naming scheme for the ports. Co-developed-by: R Signed-off-by: R Co-developed-by: Hector Martin Signed-off-by: Hector Martin Signed-off-by: Janne Grunau Tested-by: Sven Peter # M1 mac mini and macbook air Reviewed-by: Sven Peter Reviewed-by: Neal Gompa Link: https://patch.msgid.link/20260109-apple-dt-usb-c-atc-dwc3-v1-3-ce0e92c1a016@jannau.net Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t6001.dtsi | 1 + arch/arm64/boot/dts/apple/t6002-j375d.dts | 150 +++++++ arch/arm64/boot/dts/apple/t6002.dtsi | 1 + arch/arm64/boot/dts/apple/t600x-dieX.dtsi | 212 +++++++++ .../arm64/boot/dts/apple/t600x-j314-j316.dtsi | 234 ++++++++++ arch/arm64/boot/dts/apple/t600x-j375.dtsi | 270 ++++++++++++ arch/arm64/boot/dts/apple/t6022-j180d.dts | 415 ++++++++++++++++++ arch/arm64/boot/dts/apple/t6022-j475d.dts | 31 ++ arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi | 133 ++++++ arch/arm64/boot/dts/apple/t602x-dieX.dtsi | 212 +++++++++ 10 files changed, 1659 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t6001.dtsi b/arch/arm64/boot/dts/apple/t6001.dtsi index ffbe823b71bc..6dcb71a1d65a 100644 --- a/arch/arm64/boot/dts/apple/t6001.dtsi +++ b/arch/arm64/boot/dts/apple/t6001.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "multi-die-cpp.h" diff --git a/arch/arm64/boot/dts/apple/t6002-j375d.dts b/arch/arm64/boot/dts/apple/t6002-j375d.dts index 2b7f80119618..a2a24d028cbb 100644 --- a/arch/arm64/boot/dts/apple/t6002-j375d.dts +++ b/arch/arm64/boot/dts/apple/t6002-j375d.dts @@ -15,6 +15,10 @@ / { compatible = "apple,j375d", "apple,t6002", "apple,arm-platform"; model = "Apple Mac Studio (M1 Ultra, 2022)"; + aliases { + atcphy4 = &atcphy0_die1; + atcphy5 = &atcphy1_die1; + }; }; /* USB Type C */ @@ -26,6 +30,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec4: connector { + compatible = "usb-c-connector"; + label = "USB-C Front Right"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec4_connector_hs: endpoint { + remote-endpoint = <&dwc3_4_hs>; + }; + }; + port@1 { + reg = <1>; + typec4_connector_ss: endpoint { + remote-endpoint = <&atcphy4_typec_lanes>; + }; + }; + }; + }; }; /* front-left */ @@ -35,6 +63,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec5: connector { + compatible = "usb-c-connector"; + label = "USB-C Front Left"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec5_connector_hs: endpoint { + remote-endpoint = <&dwc3_5_hs>; + }; + }; + port@1 { + reg = <1>; + typec5_connector_ss: endpoint { + remote-endpoint = <&atcphy5_typec_lanes>; + }; + }; + }; + }; }; }; @@ -46,6 +98,104 @@ brcm,board-type = "apple,okinawa"; }; +/* USB controllers on die 1 */ +&dwc3_0_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_4_hs: endpoint { + remote-endpoint = <&typec4_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_4_ss: endpoint { + remote-endpoint = <&atcphy4_usb3>; + }; + }; + }; +}; + +&dwc3_1_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_5_hs: endpoint { + remote-endpoint = <&typec5_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_5_ss: endpoint { + remote-endpoint = <&atcphy5_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy4_typec_lanes: endpoint { + remote-endpoint = <&typec4_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy4_usb3: endpoint { + remote-endpoint = <&dwc3_4_ss>; + }; + }; + }; +}; + +&atcphy1_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy5_typec_lanes: endpoint { + remote-endpoint = <&typec5_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy5_usb3: endpoint { + remote-endpoint = <&dwc3_5_ss>; + }; + }; + }; +}; + +/* delete unused USB nodes on die 1 */ + +/delete-node/ &dwc3_2_dart_0_die1; +/delete-node/ &dwc3_2_dart_1_die1; +/delete-node/ &dwc3_2_die1; +/delete-node/ &atcphy2_die1; + +/delete-node/ &dwc3_3_dart_0_die1; +/delete-node/ &dwc3_3_dart_1_die1; +/delete-node/ &dwc3_3_die1; +/delete-node/ &atcphy3_die1; + /* delete unused always-on power-domains on die 1 */ /delete-node/ &ps_atc2_usb_aon_die1; diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi index 8fb648836b53..a532e5401c4e 100644 --- a/arch/arm64/boot/dts/apple/t6002.dtsi +++ b/arch/arm64/boot/dts/apple/t6002.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "multi-die-cpp.h" diff --git a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi index a32ff0c9d7b0..9676d5127039 100644 --- a/arch/arm64/boot/dts/apple/t600x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-dieX.dtsi @@ -119,3 +119,215 @@ interrupt-controller; #interrupt-cells = <2>; }; + + DIE_NODE(dwc3_0): usb@702280000 { + compatible = "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg = <0x7 0x02280000 0x0 0xcd00>, <0x7 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_0_dart_0) 0>, + <&DIE_NODE(dwc3_0_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + resets = <&DIE_NODE(atcphy0)>; + phys = <&DIE_NODE(atcphy0) PHY_TYPE_USB2>, <&DIE_NODE(atcphy0) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_0_dart_0): iommu@702f00000 { + compatible = "apple,t6000-dart"; + reg = <0x7 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_0_dart_1): iommu@702f80000 { + compatible = "apple,t6000-dart"; + reg = <0x7 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy0): phy@703000000 { + compatible = "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg = <0x7 0x03000000 0x0 0x4c000>, + <0x7 0x03050000 0x0 0x8000>, + <0x7 0x00000000 0x0 0x4000>, + <0x7 0x02a90000 0x0 0x4000>, + <0x7 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + }; + + DIE_NODE(dwc3_1): usb@b02280000 { + compatible = "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg = <0xb 0x02280000 0x0 0xcd00>, <0xb 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_1_dart_0) 0>, + <&DIE_NODE(dwc3_1_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + resets = <&DIE_NODE(atcphy1)>; + phys = <&DIE_NODE(atcphy1) PHY_TYPE_USB2>, <&DIE_NODE(atcphy1) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_1_dart_0): iommu@b02f00000 { + compatible = "apple,t6000-dart"; + reg = <0xb 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_1_dart_1): iommu@b02f80000 { + compatible = "apple,t6000-dart"; + reg = <0xb 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy1): phy@b03000000 { + compatible = "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg = <0xb 0x03000000 0x0 0x4c000>, + <0xb 0x03050000 0x0 0x8000>, + <0xb 0x00000000 0x0 0x4000>, + <0xb 0x02a90000 0x0 0x4000>, + <0xb 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + }; + + DIE_NODE(dwc3_2): usb@f02280000 { + compatible = "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg = <0xf 0x02280000 0x0 0xcd00>, <0xf 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_2_dart_0) 0>, + <&DIE_NODE(dwc3_2_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + resets = <&DIE_NODE(atcphy2)>; + phys = <&DIE_NODE(atcphy2) PHY_TYPE_USB2>, <&DIE_NODE(atcphy2) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_2_dart_0): iommu@f02f00000 { + compatible = "apple,t6000-dart"; + reg = <0xf 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_2_dart_1): iommu@f02f80000 { + compatible = "apple,t6000-dart"; + reg = <0xf 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy2): phy@f03000000 { + compatible = "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg = <0xf 0x03000000 0x0 0x4c000>, + <0xf 0x03050000 0x0 0x8000>, + <0xf 0x00000000 0x0 0x4000>, + <0xf 0x02a90000 0x0 0x4000>, + <0xf 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + }; + + DIE_NODE(dwc3_3): usb@1302280000 { + compatible = "apple,t6000-dwc3", "apple,t8103-dwc3"; + reg = <0x13 0x02280000 0x0 0xcd00>, <0x13 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_3_dart_0) 0>, + <&DIE_NODE(dwc3_3_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + resets = <&DIE_NODE(atcphy3)>; + phys = <&DIE_NODE(atcphy3) PHY_TYPE_USB2>, <&DIE_NODE(atcphy3) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_3_dart_0): iommu@1302f00000 { + compatible = "apple,t6000-dart"; + reg = <0x13 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_3_dart_1): iommu@1302f80000 { + compatible = "apple,t6000-dart"; + reg = <0x13 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy3): phy@1303000000 { + compatible = "apple,t6000-atcphy", "apple,t8103-atcphy"; + reg = <0x13 0x03000000 0x0 0x4c000>, + <0x13 0x03050000 0x0 0x8000>, + <0x13 0x00000000 0x0 0x4000>, + <0x13 0x02a90000 0x0 0x4000>, + <0x13 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + }; diff --git a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi index c0aac59a6fae..6b3b32723081 100644 --- a/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j314-j316.dtsi @@ -13,6 +13,10 @@ / { aliases { + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; + atcphy2 = &atcphy2; + atcphy3 = &atcphy3; bluetooth0 = &bluetooth0; serial0 = &serial0; wifi0 = &wifi0; @@ -63,6 +67,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + label = "USB-C Left Rear"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -71,6 +99,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + label = "USB-C Left Front"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; }; hpm2: usb-pd@3b { @@ -79,6 +131,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec2: connector { + compatible = "usb-c-connector"; + label = "USB-C Right"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec2_connector_hs: endpoint { + remote-endpoint = <&dwc3_2_hs>; + }; + }; + port@1 { + reg = <1>; + typec2_connector_ss: endpoint { + remote-endpoint = <&atcphy2_typec_lanes>; + }; + }; + }; + }; }; /* MagSafe port */ @@ -130,4 +206,162 @@ status = "okay"; }; +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +&dwc3_2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_2_hs: endpoint { + remote-endpoint = <&typec2_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_2_ss: endpoint { + remote-endpoint = <&atcphy2_usb3>; + }; + }; + }; +}; + +/* + * ps_atc3_usb_aon power-domain is always-on to keep dwc3 working over suspend. + * atc3 is used exclusively for the DP-to-HDMI so do not keep this always on. + */ +&ps_atc3_usb_aon { + /delete-property/ apple,always-on; +}; + +/* ATC3 is used for DisplayPort -> HDMI only */ +&dwc3_3_dart_0 { + status = "disabled"; +}; + +&dwc3_3_dart_1 { + status = "disabled"; +}; + +&dwc3_3 { + status = "disabled"; +}; + +/* Delete unused dwc3_3 to prevent dt_disable_missing_devs() from disabling + * atcphy3 via phandle references from a disablecd device. + */ +/delete-node/ &dwc3_3; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; + }; +}; + +&atcphy2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy2_typec_lanes: endpoint { + remote-endpoint = <&typec2_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy2_usb3: endpoint { + remote-endpoint = <&dwc3_2_ss>; + }; + }; + }; +}; + +&atcphy3 { + status = "disabled"; +}; + #include "spi1-nvram.dtsi" diff --git a/arch/arm64/boot/dts/apple/t600x-j375.dtsi b/arch/arm64/boot/dts/apple/t600x-j375.dtsi index c0fb93ae72f4..a4bb5cbb67a0 100644 --- a/arch/arm64/boot/dts/apple/t600x-j375.dtsi +++ b/arch/arm64/boot/dts/apple/t600x-j375.dtsi @@ -11,6 +11,10 @@ / { aliases { + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; + atcphy2 = &atcphy2; + atcphy3 = &atcphy3; bluetooth0 = &bluetooth0; ethernet0 = ðernet0; serial0 = &serial0; @@ -50,6 +54,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + label = "USB-C Back Left"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -58,6 +86,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + label = "USB-C Back Left Middle"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; }; hpm2: usb-pd@3b { @@ -66,6 +118,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec2: connector { + compatible = "usb-c-connector"; + label = "USB-C Back Right Middle"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec2_connector_hs: endpoint { + remote-endpoint = <&dwc3_2_hs>; + }; + }; + port@1 { + reg = <1>; + typec2_connector_ss: endpoint { + remote-endpoint = <&atcphy2_typec_lanes>; + }; + }; + }; + }; }; hpm3: usb-pd@3c { @@ -74,6 +150,200 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <174 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec3: connector { + compatible = "usb-c-connector"; + label = "USB-C Back Right"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec3_connector_hs: endpoint { + remote-endpoint = <&dwc3_3_hs>; + }; + }; + port@1 { + reg = <1>; + typec3_connector_ss: endpoint { + remote-endpoint = <&atcphy3_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +&dwc3_2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_2_hs: endpoint { + remote-endpoint = <&typec2_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_2_ss: endpoint { + remote-endpoint = <&atcphy2_usb3>; + }; + }; + }; +}; + +&dwc3_3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_3_hs: endpoint { + remote-endpoint = <&typec3_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_3_ss: endpoint { + remote-endpoint = <&atcphy3_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; + }; +}; + +&atcphy2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy2_typec_lanes: endpoint { + remote-endpoint = <&typec2_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy2_usb3: endpoint { + remote-endpoint = <&dwc3_2_ss>; + }; + }; + }; +}; + +&atcphy3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy3_typec_lanes: endpoint { + remote-endpoint = <&typec3_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy3_usb3: endpoint { + remote-endpoint = <&dwc3_3_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t6022-j180d.dts b/arch/arm64/boot/dts/apple/t6022-j180d.dts index dca6bd167c22..741199d456fb 100644 --- a/arch/arm64/boot/dts/apple/t6022-j180d.dts +++ b/arch/arm64/boot/dts/apple/t6022-j180d.dts @@ -16,6 +16,14 @@ compatible = "apple,j180d", "apple,t6022", "apple,arm-platform"; model = "Apple Mac Pro (M2 Ultra, 2023)"; aliases { + atcphy0 = &atcphy0; + atcphy1 = &atcphy1; + atcphy2 = &atcphy2; + atcphy3 = &atcphy3; + atcphy4 = &atcphy0_die1; + atcphy5 = &atcphy1_die1; + atcphy6 = &atcphy2_die1; + atcphy7 = &atcphy3_die1; nvram = &nvram; serial0 = &serial0; }; @@ -54,6 +62,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec2: connector { + compatible = "usb-c-connector"; + label = "USB-C Back 1"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec2_connector_hs: endpoint { + remote-endpoint = <&dwc3_2_hs>; + }; + }; + port@1 { + reg = <1>; + typec2_connector_ss: endpoint { + remote-endpoint = <&atcphy2_typec_lanes>; + }; + }; + }; + }; }; hpm3: usb-pd@3c { @@ -62,6 +94,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec3: connector { + compatible = "usb-c-connector"; + label = "USB-C Back 2"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec3_connector_hs: endpoint { + remote-endpoint = <&dwc3_3_hs>; + }; + }; + port@1 { + reg = <1>; + typec3_connector_ss: endpoint { + remote-endpoint = <&atcphy3_typec_lanes>; + }; + }; + }; + }; }; /* hpm4 and hpm5 included from t6022-jxxxd.dtsi */ @@ -72,6 +128,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec6: connector { + compatible = "usb-c-connector"; + label = "USB-C Back 5"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec6_connector_hs: endpoint { + remote-endpoint = <&dwc3_6_hs>; + }; + }; + port@1 { + reg = <1>; + typec6_connector_ss: endpoint { + remote-endpoint = <&atcphy6_typec_lanes>; + }; + }; + }; + }; }; hpm7: usb-pd@3e { @@ -80,9 +160,41 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec7: connector { + compatible = "usb-c-connector"; + label = "USB-C Back 6"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec7_connector_hs: endpoint { + remote-endpoint = <&dwc3_7_hs>; + }; + }; + port@1 { + reg = <1>; + typec7_connector_ss: endpoint { + remote-endpoint = <&atcphy7_typec_lanes>; + }; + }; + }; + }; }; }; +&typec4 { + label = "USB-C Back 3"; +}; + +&typec5 { + label = "USB-C Back 4"; +}; + /* USB Type C Front */ &i2c3 { status = "okay"; @@ -93,6 +205,30 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <60 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec0: connector { + compatible = "usb-c-connector"; + label = "USB-C Top Right"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec0_connector_hs: endpoint { + remote-endpoint = <&dwc3_0_hs>; + }; + }; + port@1 { + reg = <1>; + typec0_connector_ss: endpoint { + remote-endpoint = <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; hpm1: usb-pd@3f { @@ -101,6 +237,285 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <60 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec1: connector { + compatible = "usb-c-connector"; + label = "USB-C Top Left"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec1_connector_hs: endpoint { + remote-endpoint = <&dwc3_1_hs>; + }; + }; + port@1 { + reg = <1>; + typec1_connector_ss: endpoint { + remote-endpoint = <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_0_hs: endpoint { + remote-endpoint = <&typec0_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_0_ss: endpoint { + remote-endpoint = <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_1_hs: endpoint { + remote-endpoint = <&typec1_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_1_ss: endpoint { + remote-endpoint = <&atcphy1_usb3>; + }; + }; + }; +}; + +&dwc3_2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_2_hs: endpoint { + remote-endpoint = <&typec2_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_2_ss: endpoint { + remote-endpoint = <&atcphy2_usb3>; + }; + }; + }; +}; + +&dwc3_3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_3_hs: endpoint { + remote-endpoint = <&typec3_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_3_ss: endpoint { + remote-endpoint = <&atcphy3_usb3>; + }; + }; + }; +}; + +/* USB controllers on die 1 */ +&dwc3_2_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_6_hs: endpoint { + remote-endpoint = <&typec6_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_6_ss: endpoint { + remote-endpoint = <&atcphy6_usb3>; + }; + }; + }; +}; + +&dwc3_3_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_7_hs: endpoint { + remote-endpoint = <&typec7_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_7_ss: endpoint { + remote-endpoint = <&atcphy7_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint = <&typec0_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy0_usb3: endpoint { + remote-endpoint = <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint = <&typec1_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy1_usb3: endpoint { + remote-endpoint = <&dwc3_1_ss>; + }; + }; + }; +}; + +&atcphy2 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy2_typec_lanes: endpoint { + remote-endpoint = <&typec2_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy2_usb3: endpoint { + remote-endpoint = <&dwc3_2_ss>; + }; + }; + }; +}; + +&atcphy3 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy3_typec_lanes: endpoint { + remote-endpoint = <&typec3_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy3_usb3: endpoint { + remote-endpoint = <&dwc3_3_ss>; + }; + }; + }; +}; + +&atcphy2_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy6_typec_lanes: endpoint { + remote-endpoint = <&typec6_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy6_usb3: endpoint { + remote-endpoint = <&dwc3_6_ss>; + }; + }; + }; +}; + +&atcphy3_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy7_typec_lanes: endpoint { + remote-endpoint = <&typec7_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy7_usb3: endpoint { + remote-endpoint = <&dwc3_7_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t6022-j475d.dts b/arch/arm64/boot/dts/apple/t6022-j475d.dts index 736594544f79..31f24bbda968 100644 --- a/arch/arm64/boot/dts/apple/t6022-j475d.dts +++ b/arch/arm64/boot/dts/apple/t6022-j475d.dts @@ -16,6 +16,11 @@ / { compatible = "apple,j475d", "apple,t6022", "apple,arm-platform"; model = "Apple Mac Studio (M2 Ultra, 2023)"; + + aliases { + atcphy4 = &atcphy0_die1; + atcphy5 = &atcphy1_die1; + }; }; &framebuffer0 { @@ -31,6 +36,32 @@ status = "okay"; }; +&typec4 { + label = "USB-C Front Right"; +}; + +&typec5 { + label = "USB-C Front Left"; +}; + +/* delete unused USB nodes on die 1 */ +/delete-node/ &dwc3_2_dart_0_die1; +/delete-node/ &dwc3_2_dart_1_die1; +/delete-node/ &dwc3_2_die1; +/delete-node/ &atcphy2_die1; + +/delete-node/ &dwc3_3_dart_0_die1; +/delete-node/ &dwc3_3_dart_1_die1; +/delete-node/ &dwc3_3_die1; +/delete-node/ &atcphy3_die1; + +/* delete unused always-on power-domains on die 1 */ +/delete-node/ &ps_atc2_usb_aon_die1; +/delete-node/ &ps_atc2_usb_die1; + +/delete-node/ &ps_atc3_usb_aon_die1; +/delete-node/ &ps_atc3_usb_die1; + &wifi0 { compatible = "pci14e4,4434"; brcm,board-type = "apple,canary"; diff --git a/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi index 4f7bf2ebfe39..dc877bd604f8 100644 --- a/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi +++ b/arch/arm64/boot/dts/apple/t6022-jxxxd.dtsi @@ -25,6 +25,29 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec4: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec4_connector_hs: endpoint { + remote-endpoint = <&dwc3_4_hs>; + }; + }; + port@1 { + reg = <1>; + typec4_connector_ss: endpoint { + remote-endpoint = <&atcphy4_typec_lanes>; + }; + }; + }; + }; }; /* front-left */ @@ -34,5 +57,115 @@ interrupt-parent = <&pinctrl_ap>; interrupts = <44 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + + typec5: connector { + compatible = "usb-c-connector"; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + typec5_connector_hs: endpoint { + remote-endpoint = <&dwc3_5_hs>; + }; + }; + port@1 { + reg = <1>; + typec5_connector_ss: endpoint { + remote-endpoint = <&atcphy5_typec_lanes>; + }; + }; + }; + }; + }; +}; + + +/* USB controllers on die 1 */ +&dwc3_0_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_4_hs: endpoint { + remote-endpoint = <&typec4_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_4_ss: endpoint { + remote-endpoint = <&atcphy4_usb3>; + }; + }; + }; +}; + +&dwc3_1_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dwc3_5_hs: endpoint { + remote-endpoint = <&typec5_connector_hs>; + }; + }; + + port@1 { + reg = <1>; + dwc3_5_ss: endpoint { + remote-endpoint = <&atcphy5_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy4_typec_lanes: endpoint { + remote-endpoint = <&typec4_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy4_usb3: endpoint { + remote-endpoint = <&dwc3_4_ss>; + }; + }; + }; +}; + +&atcphy1_die1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + atcphy5_typec_lanes: endpoint { + remote-endpoint = <&typec5_connector_ss>; + }; + }; + + port@1 { + reg = <1>; + atcphy5_usb3: endpoint { + remote-endpoint = <&dwc3_5_ss>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi index cb07fd82b32e..ae3d535c5acb 100644 --- a/arch/arm64/boot/dts/apple/t602x-dieX.dtsi +++ b/arch/arm64/boot/dts/apple/t602x-dieX.dtsi @@ -126,3 +126,215 @@ reg = <0x4 0x4e80000 0 0x4000>; }; + + DIE_NODE(dwc3_0): usb@702280000 { + compatible = "apple,t6020-dwc3", "apple,t8103-dwc3"; + reg = <0x7 0x02280000 0x0 0xcd00>, <0x7 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_0_dart_0) 0>, + <&DIE_NODE(dwc3_0_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + resets = <&DIE_NODE(atcphy0)>; + phys = <&DIE_NODE(atcphy0) PHY_TYPE_USB2>, <&DIE_NODE(atcphy0) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_0_dart_0): iommu@702f00000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x7 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_0_dart_1): iommu@702f80000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x7 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy0): phy@703000000 { + compatible = "apple,t6020-atcphy", "apple,t8103-atcphy"; + reg = <0x7 0x03000000 0x0 0x4c000>, + <0x7 0x03050000 0x0 0x8000>, + <0x7 0x00000000 0x0 0x4000>, + <0x7 0x02a90000 0x0 0x4000>, + <0x7 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc0_usb)>; + }; + + DIE_NODE(dwc3_1): usb@b02280000 { + compatible = "apple,t6020-dwc3", "apple,t8103-dwc3"; + reg = <0xb 0x02280000 0x0 0xcd00>, <0xb 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_1_dart_0) 0>, + <&DIE_NODE(dwc3_1_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + resets = <&DIE_NODE(atcphy1)>; + phys = <&DIE_NODE(atcphy1) PHY_TYPE_USB2>, <&DIE_NODE(atcphy1) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_1_dart_0): iommu@b02f00000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0xb 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_1_dart_1): iommu@b02f80000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0xb 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy1): phy@b03000000 { + compatible = "apple,t6020-atcphy", "apple,t8103-atcphy"; + reg = <0xb 0x03000000 0x0 0x4c000>, + <0xb 0x03050000 0x0 0x8000>, + <0xb 0x00000000 0x0 0x4000>, + <0xb 0x02a90000 0x0 0x4000>, + <0xb 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc1_usb)>; + }; + + DIE_NODE(dwc3_2): usb@f02280000 { + compatible = "apple,t6020-dwc3", "apple,t8103-dwc3"; + reg = <0xf 0x02280000 0x0 0xcd00>, <0xf 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_2_dart_0) 0>, + <&DIE_NODE(dwc3_2_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + resets = <&DIE_NODE(atcphy2)>; + phys = <&DIE_NODE(atcphy2) PHY_TYPE_USB2>, <&DIE_NODE(atcphy2) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_2_dart_0): iommu@f02f00000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0xf 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_2_dart_1): iommu@f02f80000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0xf 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy2): phy@f03000000 { + compatible = "apple,t6020-atcphy", "apple,t8103-atcphy"; + reg = <0xf 0x03000000 0x0 0x4c000>, + <0xf 0x03050000 0x0 0x8000>, + <0xf 0x00000000 0x0 0x4000>, + <0xf 0x02a90000 0x0 0x4000>, + <0xf 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc2_usb)>; + }; + + DIE_NODE(dwc3_3): usb@1302280000 { + compatible = "apple,t6020-dwc3", "apple,t8103-dwc3"; + reg = <0x13 0x02280000 0x0 0xcd00>, <0x13 0x0228cd00 0x0 0x3200>; + reg-names = "dwc3-core", "dwc3-apple"; + interrupt-parent = <&aic>; + interrupts = ; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + iommus = <&DIE_NODE(dwc3_3_dart_0) 0>, + <&DIE_NODE(dwc3_3_dart_1) 1>; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + resets = <&DIE_NODE(atcphy3)>; + phys = <&DIE_NODE(atcphy3) PHY_TYPE_USB2>, <&DIE_NODE(atcphy3) PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + }; + + DIE_NODE(dwc3_3_dart_0): iommu@1302f00000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x13 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(dwc3_3_dart_1): iommu@1302f80000 { + compatible = "apple,t6020-dart", "apple,t8110-dart"; + reg = <0x13 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + #iommu-cells = <1>; + }; + + DIE_NODE(atcphy3): phy@1303000000 { + compatible = "apple,t6020-atcphy", "apple,t8103-atcphy"; + reg = <0x13 0x03000000 0x0 0x4c000>, + <0x13 0x03050000 0x0 0x8000>, + <0x13 0x00000000 0x0 0x4000>, + <0x13 0x02a90000 0x0 0x4000>, + <0x13 0x02a84000 0x0 0x4000>; + reg-names = "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells = <1>; + #reset-cells = <0>; + + orientation-switch; + mode-switch; + power-domains = <&DIE_NODE(ps_atc3_usb)>; + }; From d7b70ebf2bf4a9983fe64b8c221db55f15c4c56c Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 9 Jan 2026 22:02:17 +0100 Subject: [PATCH 505/757] arm64: dts: amlogic: move CPU OPP table and clock assignment to SoC.dtsi Move the assignment of the CPU clocks and the CPU OPP table(s) from board.dts to SoC.dtsi to reduce the code duplication. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260109210217.828961-1-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong --- .../boot/dts/amlogic/meson-g12a-fbx8am.dts | 8 ------- .../dts/amlogic/meson-g12a-radxa-zero.dts | 8 ------- .../boot/dts/amlogic/meson-g12a-sei510.dts | 8 ------- .../boot/dts/amlogic/meson-g12a-u200.dts | 8 ------- .../boot/dts/amlogic/meson-g12a-x96-max.dts | 8 ------- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 8 +++++++ .../amlogic/meson-g12b-a311d-libretech-cc.dts | 13 ---------- .../boot/dts/amlogic/meson-g12b-a311d.dtsi | 24 +++++++++++++++++++ .../dts/amlogic/meson-g12b-bananapi-cm4.dtsi | 12 ---------- .../boot/dts/amlogic/meson-g12b-bananapi.dtsi | 12 ---------- .../dts/amlogic/meson-g12b-khadas-vim3.dtsi | 12 ---------- .../amlogic/meson-g12b-odroid-go-ultra.dts | 12 ---------- .../boot/dts/amlogic/meson-g12b-odroid.dtsi | 12 ---------- .../dts/amlogic/meson-g12b-radxa-zero2.dts | 12 ---------- .../boot/dts/amlogic/meson-g12b-s922x.dtsi | 24 +++++++++++++++++++ .../boot/dts/amlogic/meson-g12b-w400.dtsi | 12 ---------- arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 7 ++++++ .../boot/dts/amlogic/meson-sm1-ac2xx.dtsi | 8 ------- .../boot/dts/amlogic/meson-sm1-bananapi.dtsi | 8 ------- .../dts/amlogic/meson-sm1-khadas-vim3l.dts | 8 ------- .../boot/dts/amlogic/meson-sm1-odroid.dtsi | 8 ------- .../amlogic/meson-sm1-s905d3-libretech-cc.dts | 9 ------- .../boot/dts/amlogic/meson-sm1-sei610.dts | 8 ------- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 8 +++++++ 24 files changed, 71 insertions(+), 186 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts index d0a3b4b9229c..abf6b63ea0d7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts @@ -265,26 +265,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts index 4353485c6f26..a85f383a1699 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts @@ -218,26 +218,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index f39fcabc763f..5b6716aeaae5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -312,26 +312,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index b5bf8ecc91e6..dd9da7a5ec5f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -405,26 +405,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &clkc_audio { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 5ab460a3e637..015e3c7e3a91 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -261,26 +261,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 1321ad95923d..51317d11f263 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -25,6 +25,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu1: cpu@1 { @@ -40,6 +42,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu2: cpu@2 { @@ -55,6 +59,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu3: cpu@3 { @@ -70,6 +76,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; l2: l2-cache0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts index 82546b738977..5747acf8f337 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d-libretech-cc.dts @@ -6,7 +6,6 @@ /dts-v1/; -#include #include "meson-g12b-a311d.dtsi" #include "meson-libretech-cottonwood.dtsi" @@ -74,38 +73,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &pwm_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi index 8ecb5bd125c1..f15baa708b36 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi @@ -109,3 +109,27 @@ }; }; }; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table_0>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table_0>; +}; + +&cpu100 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu101 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu102 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu103 { + operating-points-v2 = <&cpub_opp_table_1>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi index 39011b645128..7a204d324dd4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -153,38 +153,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index 1b08303c4282..4321d08d11a6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -261,38 +261,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi index fc737499f207..b16247e0df9f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi @@ -49,38 +49,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &pwm_ab { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index d5938a4a6da3..c81d7fdbe2f5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -279,38 +279,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; /* RK817 only supports 12.5mV steps, round up the values */ diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi index 3298d59833b6..88d995006f94 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid.dtsi @@ -225,38 +225,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu_thermal { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index 1e5c6f984945..e95e193eaebc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -257,38 +257,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu_thermal { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi index 19cad93a6889..eef98add05c6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi @@ -99,3 +99,27 @@ }; }; }; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table_0>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table_0>; +}; + +&cpu100 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu101 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu102 { + operating-points-v2 = <&cpub_opp_table_1>; +}; + +&cpu103 { + operating-points-v2 = <&cpub_opp_table_1>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi index 9b6d780eada7..4834f418bef5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi @@ -211,38 +211,26 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table_0>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu100 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu101 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu102 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cpu103 { cpu-supply = <&vddcpu_a>; - operating-points-v2 = <&cpub_opp_table_1>; - clocks = <&clkc CLKID_CPUB_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi index 23358d94844c..18506d54d239 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi @@ -57,6 +57,7 @@ i-cache-sets = <32>; next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu1: cpu@1 { @@ -73,6 +74,7 @@ i-cache-sets = <32>; next-level-cache = <&l2_cache_l>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu100: cpu@100 { @@ -89,6 +91,7 @@ i-cache-sets = <32>; next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPUB_CLK>; }; cpu101: cpu@101 { @@ -105,6 +108,7 @@ i-cache-sets = <32>; next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPUB_CLK>; }; cpu102: cpu@102 { @@ -121,6 +125,7 @@ i-cache-sets = <64>; next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; + clocks = <&clkc CLKID_CPUB_CLK>; }; cpu103: cpu@103 { @@ -137,6 +142,8 @@ i-cache-sets = <64>; next-level-cache = <&l2_cache_b>; #cooling-cells = <2>; + operating-points-v2 = <&cpub_opp_table_1>; + clocks = <&clkc CLKID_CPUB_CLK>; }; l2_cache_l: l2-cache-cluster0 { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi index 9be3084b090d..661e454ca673 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi @@ -145,26 +145,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; &cvbs_vdac_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi index 5e07f0f9538e..f0e4b168a411 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi @@ -183,26 +183,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts index a3d9b66b6878..4e1e9a502666 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-khadas-vim3l.dts @@ -49,26 +49,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; &pwm_AO_cd { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index c4524eb4f099..ad886d446e96 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -248,26 +248,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; &ext_mdio { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts index 5daadfb170b4..2a16f54332df 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-s905d3-libretech-cc.dts @@ -6,7 +6,6 @@ /dts-v1/; -#include #include "meson-sm1.dtsi" #include "meson-libretech-cottonwood.dtsi" @@ -62,24 +61,16 @@ &cpu0 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu_b>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index 024d2eb8e6ee..e275b0f36b09 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -357,26 +357,18 @@ &cpu0 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU_CLK>; }; &cpu1 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU1_CLK>; }; &cpu2 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU2_CLK>; }; &cpu3 { cpu-supply = <&vddcpu>; - operating-points-v2 = <&cpu_opp_table>; - clocks = <&clkc CLKID_CPU3_CLK>; }; ðmac { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index e5db8ce94062..8f5b850b1774 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -63,6 +63,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; }; cpu1: cpu@1 { @@ -78,6 +80,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; }; cpu2: cpu@2 { @@ -93,6 +97,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; }; cpu3: cpu@3 { @@ -108,6 +114,8 @@ i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; }; l2: l2-cache0 { From f0761f6be5ed62bc282349c46784d676571ace83 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 4 Jan 2026 20:14:44 +0100 Subject: [PATCH 506/757] arm64: dts: rockchip: Move SoC include to individual QNAP TSx33 boards The TS133 while mostly similar, is based around the RK3566 variant, so needs a different SoC include. By moving the SoC include to the board devicetrees, we can still keep the shared common setup, while supporting the different base SoCs. Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260104191448.2693309-2-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts | 1 + arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 1 + arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi | 1 - 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts index f16d1c628793..9a7d58e7ccc0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include "rk3568.dtsi" #include "rk3568-qnap-tsx33.dtsi" / { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index d1e3b7e7a280..02d0974d79be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -6,6 +6,7 @@ /dts-v1/; +#include "rk3568.dtsi" #include "rk3568-qnap-tsx33.dtsi" / { diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi index f009275c72c8..c372ca40fd50 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi @@ -1,7 +1,6 @@ #include #include #include -#include "rk3568.dtsi" / { aliases { From 5a16e131ddbacdd7acfb8cab6ff0ca1c57339600 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 4 Jan 2026 20:14:45 +0100 Subject: [PATCH 507/757] arm64: dts: rockchip: Fix the common combophy + SATA on QNAP TSx33 devices The common used SATA controller on all TSx33 devices is actually SATA2. So move the SATA controller + combophy enablement to their correct position between shared dtsi and board devicetrees. Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260104191448.2693309-3-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts | 6 +++--- arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 6 +++--- arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi | 10 +++++----- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts index 9a7d58e7ccc0..e76502180788 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts @@ -18,8 +18,8 @@ }; }; -/* connected to sata2 */ -&combphy2 { +/* Connected to usb_host0_xhci */ +&combphy0 { status = "okay"; }; @@ -93,7 +93,7 @@ }; }; -&sata2 { +&sata1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index 02d0974d79be..708e7f1f8d0d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -28,8 +28,8 @@ }; }; -/* connected to sata2 */ -&combphy2 { +/* Connected to usb_host0_xhci */ +&combphy0 { status = "okay"; }; @@ -151,7 +151,7 @@ }; }; -&sata2 { +&sata1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi index c372ca40fd50..482d8584ec88 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi @@ -112,13 +112,13 @@ }; }; -/* connected to usb_host0_xhci */ -&combphy0 { +/* Connected USB3 on TS133 / SATA1 on all the others */ +&combphy1 { status = "okay"; }; -/* connected to sata1 */ -&combphy1 { +/* Connected to SATA2 */ +&combphy2 { status = "okay"; }; @@ -484,7 +484,7 @@ status = "okay"; }; -&sata1 { +&sata2 { status = "okay"; }; From a81a2d211344675de4d945eb2070e3ef1202060f Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 4 Jan 2026 20:14:46 +0100 Subject: [PATCH 508/757] arm64: dts: rockchip: Move copy-key to TSx33 board files The copy-key is not present on all device variants, so move it to the individual boards that have this key. Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260104191448.2693309-4-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts | 11 +++++++++++ arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi | 10 ++-------- 3 files changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts index e76502180788..52b741376ef5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts233.dts @@ -51,6 +51,17 @@ }; }; +&keys { + pinctrl-names = "default"; + pinctrl-0 = <©_button_pin>, <&reset_button_pin>; + + key-copy { + label = "copy"; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; +}; + &leds { led-1 { color = ; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts index 708e7f1f8d0d..7d2aedfe616d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-ts433.dts @@ -61,6 +61,17 @@ }; }; +&keys { + pinctrl-names = "default"; + pinctrl-0 = <©_button_pin>, <&reset_button_pin>; + + key-copy { + label = "copy"; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + linux,code = ; + }; +}; + &leds { led-1 { color = ; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi index 482d8584ec88..cca7b7d0685f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-qnap-tsx33.dtsi @@ -12,17 +12,11 @@ stdout-path = "serial2:115200n8"; }; - keys { + keys: keys { compatible = "gpio-keys"; - pinctrl-0 = <©_button_pin>, <&reset_button_pin>; + pinctrl-0 = <&reset_button_pin>; pinctrl-names = "default"; - key-copy { - label = "copy"; - gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - key-reset { label = "reset"; gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; From ae2208dfa2ac3872f2a0d4c72f1a29fcce7b56a8 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 4 Jan 2026 20:14:47 +0100 Subject: [PATCH 509/757] dt-bindings: arm: rockchip: add TS133 to RK356x-based QNAP NAS devices QNAP builds a number of variants of the RK356x-based NAS design. Add the 1-bay TS133 variant. This one is a tiny bit special as it is based around the RK3566 variant of the mostly similar RK3566/RK3568 SoCs. Acked-by: Rob Herring (Arm) Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260104191448.2693309-5-heiko@sntech.de --- .../devicetree/bindings/arm/rockchip.yaml | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index c9b078be3a90..670d743aa9da 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -894,11 +894,15 @@ properties: - const: rockchip,rk3568 - description: QNAP TS-x33 NAS devices - items: - - enum: - - qnap,ts233 - - qnap,ts433 - - const: rockchip,rk3568 + oneOf: + - items: + - const: qnap,ts133 + - const: rockchip,rk3566 + - items: + - enum: + - qnap,ts233 + - qnap,ts433 + - const: rockchip,rk3568 - description: Radxa Compute Module 3 (CM3) items: From 26cfaee2972c95a6d3ad85549df089a4ee93a551 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sun, 4 Jan 2026 20:14:48 +0100 Subject: [PATCH 510/757] arm64: dts: rockchip: Add TS133 variant of the QNAP NAS series The TS133 is a one-bay NAS mostly similar to the other devices in the series. The main difference is that it is build around the RK3566 SoC instead of the RK3568 variant. The RK3566/RK3568 are mostly similar with only slight variants in both speed and some specific peripherals - the RK3568 has more. The specific for the NAS series stay the same though. Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260104191448.2693309-6-heiko@sntech.de --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-qnap-ts133.dts | 71 +++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index a02510bb9c48..1bb97cd6e4b0 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -114,6 +114,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb20sx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb30.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rk2023.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts new file mode 100644 index 000000000000..d605a712de5b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Heiko Stuebner + */ + +/dts-v1/; + +#include "rk3566.dtsi" +#include "rk3568-qnap-tsx33.dtsi" + +/ { + model = "Qnap TS-133-2G NAS System 1-Bay"; + compatible = "qnap,ts133", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&mcu { + compatible = "qnap,ts133-mcu"; +}; + +&mdio1 { + rgmii_phy0: ethernet-phy@3 { + /* Motorcomm YT8521 phy */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac1 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +/* connected to usb_host1_xhci */ +&usb2phy0_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +/* USB3 port on backside */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; From 4ad1a7548080e9e9ac1a1e78672ce2acb25e69d8 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Thu, 8 Jan 2026 03:42:52 +0000 Subject: [PATCH 511/757] arm64: dts: rockchip: Make eeprom read-only for Radxa ROCK 3C/5A/5C The BL24C16 EEPROM implemented on the Radxa ROCK 3C, 5A, and 5C [1] [2] [3] is designed to have data written during factory programming (regardless of whether data is actually written or not), and we at Radxa permit users to read the data but not write to it. [4] Therefore, we will add a read-only property to the eeprom node. [1] https://dl.radxa.com/rock3/docs/hw/3c/v1400/radxa_rock_3c_v1400_schematic.pdf p.13 [2] https://dl.radxa.com/rock5/5a/docs/hw/radxa_rock5a_V1.1_sch.pdf p.19 [3] https://dl.radxa.com/rock5/5c/docs/hw/v1100/radxa_rock_5c_schematic_v1100.pdf p.18 [4] https://github.com/radxa/u-boot/blob/next-dev-v2024.10/drivers/misc/radxa-i2c-eeprom.c Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20260108034252.2713-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 + arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts index 80ac40555e02..fa28b32f6910 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts @@ -466,6 +466,7 @@ compatible = "belling,bl24c16a", "atmel,24c16"; reg = <0x50>; pagesize = <16>; + read-only; vcc-supply = <&vcca1v8_pmu>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 045a853d39ec..0991f6a21190 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -233,6 +233,7 @@ compatible = "belling,bl24c16a", "atmel,24c16"; reg = <0x50>; pagesize = <16>; + read-only; vcc-supply = <&vcc_3v3_pmu>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts index b837c4e08cec..7fe42f4ff827 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts @@ -325,6 +325,7 @@ compatible = "belling,bl24c16a", "atmel,24c16"; reg = <0x50>; pagesize = <16>; + read-only; vcc-supply = <&vcc_3v3_pmu>; }; }; From 90d88da849393c8353c98bee443410bb32838828 Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Thu, 8 Jan 2026 11:33:39 +0000 Subject: [PATCH 512/757] dt-bindings: arm: rockchip: Add Radxa CM3J on RPi CM4 IO Board The Radxa CM3J is a feature rich industrial compute module developed by Radxa, based on the Rockchip RK3568 SoC. [1] Add devicetree binding documentation for the Radxa CM3J on RPi CM4 IO Board. [1] https://dl.radxa.com/cm3j/docs/hw/radxa_cm3j_product_brief_Revision_1.0.pdf Signed-off-by: FUKAUMI Naoki Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260108113341.14037-1-naoki@radxa.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 670d743aa9da..a494494a6202 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -918,6 +918,13 @@ properties: - const: radxa,cm3i - const: rockchip,rk3568 + - description: Radxa CM3J + items: + - enum: + - radxa,cm3j-rpi-cm4 + - const: radxa,cm3j + - const: rockchip,rk3568 + - description: Radxa CM5 items: - enum: From 9103e21ee45f8cdeaa86b2c356a3ad451c140c9f Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Thu, 8 Jan 2026 11:33:40 +0000 Subject: [PATCH 513/757] arm64: dts: rockchip: Add Radxa CM3J The Radxa CM3J is a feature rich industrial compute module based on the Rockchip RK3568J SoC. [1] Specification: - Quad-core Cortex-A55 CPU - Mali-G52 2EE GPU - 1TOPS NPU - Up to 8GB LPDDR4x RAM - Up to 32GB eMMC (optional) - 16MB SPI flash (optional) - Wi-Fi 5 / BT 5.0 with external antenna connector - Gigabit Ethernet PHY - RK809 PMIC - Green (power) LED [1] https://dl.radxa.com/cm3j/docs/hw/radxa_cm3j_schematic_v1.2_20250115.pdf Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20260108113341.14037-2-naoki@radxa.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3568-radxa-cm3j.dtsi | 558 ++++++++++++++++++ 1 file changed, 558 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi new file mode 100644 index 000000000000..f21e84955948 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j.dtsi @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc2 = &sdmmc2; + }; + + gmac1_clkin: clock-125m { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds-0 { + compatible = "gpio-leds"; + + led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&gpio0_b4_led>; + }; + }; + + vcc3v3_sys: regulator-3v3-0 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc5v>; + }; + + vcc_3v3_1: regulator-3v3-1 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_1"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h_gpio3_d4>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3_1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_clkinout + &gmac1m1_rx_bus2 + &gmac1m1_tx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + #clock-cells = <1>; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dc1v8: vccio_flash: vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dc3v3: vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + vin-supply = <&dc5v>; + }; +}; + +&i2c2 { + status = "okay"; + + eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <&gpio_vref>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_rstn_gpio3_b0>; // GPIO4_C3 + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h_gpio4_b2: bt-reg-on-h-gpio4-b2 { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h_gpio4_b4: bt-wake-host-h-gpio4-b4 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h_gpio4_b5: host-wake-bt-h-gpio4-b5 { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet { + gmac1_rstn_gpio3_b0: gmac1-rstn-gpio3-b0 { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + gpio0_b4_led: gpio0-b4-led { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_clkreqnm2: pcie20_clkreqnm2 { + rockchip,pins = <1 RK_PB0 4 &pcfg_pull_none>; + }; + + pcie_nrst: pcie-nrst { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_reg_on_h_gpio3_d4: wifi-reg-on-h-gpio3-d4 { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_clkreqnm2 &pcie_nrst>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + supports-clkreq; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vccio_flash>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + max-frequency = <200000000>; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&sdmmc2 { + #address-cells = <1>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <200000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; + sd-uhs-sdr104; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + }; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <&vccio_flash>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart8 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h_gpio4_b2 + &bt_wake_host_h_gpio4_b4 + &host_wake_bt_h_gpio4_b5>; + shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + vbat-supply = <&vcc_3v3_1>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; From d813ddc0b348febf32fc9d7737ba82d2955051ac Mon Sep 17 00:00:00 2001 From: FUKAUMI Naoki Date: Thu, 8 Jan 2026 11:33:41 +0000 Subject: [PATCH 514/757] arm64: dts: rockchip: Add Radxa CM3J on RPi CM4 IO Board The Raspberry Pi Compute Module 4 IO Board is an application board for the Compute Module 4. [1] This patch adds support for the Radxa CM3J mounted on the RPi CM4 IO Board. Specification: - 12V 5521 DC jack - 2x full-size HDMI 2.0 connectors (only HDMI0 is supported with CM3J) - Gigabit Ethernet RJ45 with PoE support - 2x USB 2.0 connectors, with header for two more connectors - Micro USB connector - microSD card socket - PCIe Gen 2 x1 socket - 12V 4-pin PWM fan connector - External power connector (+5V, +12V) - 2x MIPI DSI connectors - 2x MIPI CSI-2 connectors - 40-pin GPIO header - RTC with battery socket - Red (power) and green (heartbeat) LEDs [1] https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf Signed-off-by: FUKAUMI Naoki Link: https://patch.msgid.link/20260108113341.14037-3-naoki@radxa.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../rockchip/rk3568-radxa-cm3j-rpi-cm4.dts | 204 ++++++++++++++++++ 2 files changed, 205 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1bb97cd6e4b0..31a501a1717e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -149,6 +149,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts233.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-qnap-ts433.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-cm3j-rpi-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts new file mode 100644 index 000000000000..b91ac0ca854c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3j-rpi-cm4.dts @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3568-radxa-cm3j.dtsi" + +/ { + model = "Radxa CM3J on RPi CM4 IO Board"; + compatible = "radxa,cm3j-rpi-cm4", "radxa,cm3j", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac1; + mmc1 = &sdmmc0; + rtc0 = &pcf85063; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds-1 { + compatible = "gpio-leds"; + + led-1 { + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&npwr_led>; + }; + + led-2 { + color = ; + default-state = "on"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&pi_nled_activity>; + }; + }; + + dc12v: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "dc12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + dc3v3_pcie: regulator-3v3-2 { + compatible = "regulator-fixed"; + regulator-name = "dc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc12v>; + }; + + gpio_vref: regulator-3v3-3 { + compatible = "regulator-fixed"; + regulator-name = "gpio_vref"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc3v3>; + }; + + dc5v: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "dc5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc12v>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&gmac1 { + status = "okay"; +}; + +&gpio0 { + nextrst-hog { + gpio-hog; + /* + * GPIO_ACTIVE_LOW + output-low here means that the pin is set + * to high, because output-low decides the value pre-inversion. + */ + gpios = ; + line-name = "nEXTRST"; + output-low; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + emc2301: fan-controller@2f { + compatible = "microchip,emc2301", "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + + fan@0 { + reg = <0x0>; + pwms = <&emc2301 26000 0 1>; + #cooling-cells = <2>; + }; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&pinctrl { + leds { + npwr_led: npwr-led { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pi_nled_activity: pi-nled-activity { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie2x1 { + vpcie3v3-supply = <&dc3v3_pcie>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + broken-cd; + disable-wp; + no-mmc; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + vmmc-supply = <&dc3v3>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; From e7fc2fee4212714485d0efb12cdd9fbb51dde078 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Wed, 1 Oct 2025 13:03:44 +0530 Subject: [PATCH 515/757] arm64: dts: qcom: sa8775p: Add reg and clocks for QoS configuration Add register addresses and clocks which need to be enabled for configuring QoS on sa8775p SoC. Signed-off-by: Odelu Kukatla Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251001073344.6599-4-odelu.kukatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 163 +++++++++++++++------------ 1 file changed, 91 insertions(+), 72 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 7c46f493300c..6788e4d5b413 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -527,90 +527,18 @@ }; }; - aggre1_noc: interconnect-aggre1-noc { - compatible = "qcom,sa8775p-aggre1-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect-aggre2-noc { - compatible = "qcom,sa8775p-aggre2-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - clk_virt: interconnect-clk-virt { compatible = "qcom,sa8775p-clk-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - config_noc: interconnect-config-noc { - compatible = "qcom,sa8775p-config-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - dc_noc: interconnect-dc-noc { - compatible = "qcom,sa8775p-dc-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gem_noc: interconnect-gem-noc { - compatible = "qcom,sa8775p-gem-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - gpdsp_anoc: interconnect-gpdsp-anoc { - compatible = "qcom,sa8775p-gpdsp-anoc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect-lpass-ag-noc { - compatible = "qcom,sa8775p-lpass-ag-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - mc_virt: interconnect-mc-virt { compatible = "qcom,sa8775p-mc-virt"; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; }; - mmss_noc: interconnect-mmss-noc { - compatible = "qcom,sa8775p-mmss-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - nspa_noc: interconnect-nspa-noc { - compatible = "qcom,sa8775p-nspa-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - nspb_noc: interconnect-nspb-noc { - compatible = "qcom,sa8775p-nspb-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pcie_anoc: interconnect-pcie-anoc { - compatible = "qcom,sa8775p-pcie-anoc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect-system-noc { - compatible = "qcom,sa8775p-system-noc"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - /* Will be updated by the bootloader. */ memory@80000000 { device_type = "memory"; @@ -2710,6 +2638,62 @@ reg = <0 0x010d2000 0 0x1000>; }; + config_noc: interconnect@14c0000 { + compatible = "qcom,sa8775p-config-noc"; + reg = <0x0 0x014c0000 0x0 0x13080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sa8775p-system-noc"; + reg = <0x0 0x01680000 0x0 0x15080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16c0000 { + compatible = "qcom,sa8775p-aggre1-noc"; + reg = <0x0 0x016c0000 0x0 0x18080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sa8775p-aggre2-noc"; + reg = <0x0 0x01700000 0x0 0x1b080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + pcie_anoc: interconnect@1760000 { + compatible = "qcom,sa8775p-pcie-anoc"; + reg = <0x0 0x01760000 0x0 0xc080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect@1780000 { + compatible = "qcom,sa8775p-gpdsp-anoc"; + reg = <0x0 0x01780000 0x0 0xe080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect@17a0000 { + compatible = "qcom,sa8775p-mmss-noc"; + reg = <0x0 0x017a0000 0x0 0x40000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; @@ -2802,6 +2786,13 @@ interconnect-names = "memory"; }; + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,sa8775p-lpass-ag-noc"; + reg = <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + ctcu@4001000 { compatible = "qcom,sa8775p-ctcu"; reg = <0x0 0x04001000 0x0 0x1000>; @@ -4014,6 +4005,20 @@ reg = <0x0 0x0891c000 0x0 0x84>; }; + dc_noc: interconnect@90e0000 { + compatible = "qcom,sa8775p-dc-noc"; + reg = <0x0 0x090e0000 0x0 0x5080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect@9100000 { + compatible = "qcom,sa8775p-gem-noc"; + reg = <0x0 0x09100000 0x0 0xf6080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + usb_0: usb@a600000 { compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; reg = <0 0x0a600000 0 0xfc100>; @@ -7048,6 +7053,13 @@ status = "disabled"; }; + nspa_noc: interconnect@260c0000 { + compatible = "qcom,sa8775p-nspa-noc"; + reg = <0x0 0x260c0000 0x0 0x16080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + remoteproc_cdsp0: remoteproc@26300000 { compatible = "qcom,sa8775p-cdsp0-pas"; reg = <0x0 0x26300000 0x0 0x10000>; @@ -7180,6 +7192,13 @@ }; }; + nspb_noc: interconnect@2a0c0000 { + compatible = "qcom,sa8775p-nspb-noc"; + reg = <0x0 0x2a0c0000 0x0 0x16080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + remoteproc_cdsp1: remoteproc@2a300000 { compatible = "qcom,sa8775p-cdsp1-pas"; reg = <0x0 0x2a300000 0x0 0x10000>; From 4d9af1e12cd6462c53aa91b6a0b6af7861e1c0ce Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 29 Oct 2023 16:26:57 -0500 Subject: [PATCH 516/757] arm64: dts: allwinner: a100: Add LED controller node Allwinner A100 contains an LED controller. Add it to the devicetree. Acked-by: Guo Ren Reviewed-by: Jernej Skrabec Signed-off-by: Samuel Holland Link: https://patch.msgid.link/20231029212738.7871-4-samuel@sholland.org [wens@kernel.org: resolve conflict; move "status" to end of properties] Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index bb5f9e4f3d42..b3fb1e0ee796 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -420,6 +420,20 @@ #size-cells = <0>; }; + ledc: led-controller@5018000 { + compatible = "allwinner,sun50i-a100-ledc"; + reg = <0x5018000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + emac0: ethernet@5020000 { compatible = "allwinner,sun50i-a100-emac", "allwinner,sun50i-a64-emac"; From c8e75e0cecd277fb585d4491a6eeaaff64546f10 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 29 Oct 2023 16:26:58 -0500 Subject: [PATCH 517/757] riscv: dts: allwinner: d1: Add LED controller node Allwinner D1 contains an LED controller. Add its devicetree node, as well as the pinmux used by the reference board design. Acked-by: Guo Ren Reviewed-by: Jernej Skrabec Tested-by: Trevor Woerner Signed-off-by: Samuel Holland Link: https://patch.msgid.link/20231029212738.7871-5-samuel@sholland.org [wens@kernel.org: move "status" to end of properties] Signed-off-by: Chen-Yu Tsai --- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 6 ++++++ arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi index b18f368e06e0..b0fb0ea377bc 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi @@ -58,6 +58,12 @@ function = "i2c2"; }; + /omit-if-no-ref/ + ledc_pc0_pin: ledc-pc0-pin { + pins = "PC0"; + function = "ledc"; + }; + /omit-if-no-ref/ uart0_pb8_pins: uart0-pb8-pins { pins = "PB8", "PB9"; diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 63e252b44973..895b89a83e75 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -204,6 +204,21 @@ #reset-cells = <1>; }; + ledc: led-controller@2008000 { + compatible = "allwinner,sun20i-d1-ledc", + "allwinner,sun50i-a100-ledc"; + reg = <0x2008000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpadc: adc@2009000 { compatible = "allwinner,sun20i-d1-gpadc"; reg = <0x2009000 0x400>; From f8ad8bbb8827c5bfd83bdf5e1ab512d2dc5db643 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 29 Oct 2023 16:26:59 -0500 Subject: [PATCH 518/757] riscv: dts: allwinner: d1: Add RGB LEDs to boards Some D1-based boards feature an onboard RGB LED. Enable them. Acked-by: Guo Ren Acked-by: Jernej Skrabec Tested-by: Trevor Woerner Signed-off-by: Samuel Holland Link: https://patch.msgid.link/20231029212738.7871-6-samuel@sholland.org Signed-off-by: Chen-Yu Tsai --- .../boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts | 12 ++++++++++++ arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts | 13 +++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts index 08cf716328a0..feaa75d5aead 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts @@ -59,6 +59,18 @@ status = "okay"; }; +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_STATUS; + }; +}; + &mmc1 { bus-width = <4>; mmc-pwrseq = <&wifi_pwrseq>; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts index 8dbe717c79ce..73840ea300f0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts @@ -22,6 +22,7 @@ #include #include +#include /dts-v1/; @@ -121,6 +122,18 @@ }; }; +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_STATUS; + }; +}; + &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; From 96ea45304d786f6bcf4b553a05eb90675bc0f2f3 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Wed, 3 Sep 2025 12:49:55 +0530 Subject: [PATCH 519/757] arm64: dts: qcom: qcs8300: Add GPU cooling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Unlike the CPU, the GPU does not throttle its speed automatically when it reaches high temperatures. Set up GPU cooling by throttling the GPU speed when reaching 115°C. Signed-off-by: Gaurav Kohli Signed-off-by: Akhil P Oommen Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250903-a623-gpu-support-v5-4-5398585e2981@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/monaco.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 83780cd3dc8a..5d2df4305d1c 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -7262,12 +7262,25 @@ thermal-sensors = <&tsens0 5>; trips { + gpuss0_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + gpuss0-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; audio-thermal { @@ -7382,12 +7395,25 @@ thermal-sensors = <&tsens1 5>; trips { + gpuss1_alert0: trip-point0 { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + gpuss1-critical { temperature = <125000>; hysteresis = <1000>; type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; video-thermal { From fff010c776f715904ba0823bb347eac00dccffa2 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 25 Dec 2025 14:24:20 +0800 Subject: [PATCH 520/757] dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt The descriptions for h, svinval, svnapot, and svpbmt extensions currently reference the "20191213 version of the privileged ISA specification". While an Unprivileged ISA document exists with that date, there is no corresponding ratified Privileged ISA specification. These extensions were ratified in the RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 20211203. Update the descriptions to reference the correct specification version. RISC-V International hosts a website [1] for ratified specifications. Following the "Ratified ISA Specifications", historical versions of Volume II Privileged ISA can be found. Link: https://riscv.org/specifications/ratified/ [1] Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") Acked-by: Conor Dooley Signed-off-by: Guodong Xu Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 565cb2cbb49b..6a4697b36b8d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -117,8 +117,9 @@ properties: - const: h description: - The standard H extension for hypervisors as ratified in the 20191213 - version of the privileged ISA specification. + The standard H extension for hypervisors as ratified in the RISC-V + Instruction Set Manual, Volume II Privileged Architecture, + Document Version 20211203. # multi-letter extensions, sorted alphanumerically - const: smaia @@ -202,20 +203,22 @@ properties: - const: svinval description: The standard Svinval supervisor-level extension for fine-grained - address-translation cache invalidation as ratified in the 20191213 - version of the privileged ISA specification. + address-translation cache invalidation as ratified in the RISC-V + Instruction Set Manual, Volume II Privileged Architecture, + Document Version 20211203. - const: svnapot description: The standard Svnapot supervisor-level extensions for napot - translation contiguity as ratified in the 20191213 version of the - privileged ISA specification. + translation contiguity as ratified in the RISC-V Instruction Set + Manual, Volume II Privileged Architecture, Document Version + 20211203. - const: svpbmt description: The standard Svpbmt supervisor-level extensions for page-based - memory types as ratified in the 20191213 version of the privileged - ISA specification. + memory types as ratified in the RISC-V Instruction Set Manual, + Volume II Privileged Architecture, Document Version 20211203. - const: svrsw60t59b description: From 0cdb7fc1879b1b858463125630f4dd5af6b111ad Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:18 +0800 Subject: [PATCH 521/757] dt-bindings: riscv: Add B ISA extension description Add description of the single-letter B extension for Bit Manipulation. B is mandatory for RVA23U64. The B extension is ratified in the 20240411 version of the unprivileged ISA specification. According to the ratified spec, the B standard extension comprises instructions provided by the Zba, Zbb, and Zbs extensions. Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and when Zba/Zbb/Zbs (all of them) are specified, then B must be added too. The reason why B/Zba/Zbb/Zbs must coexist at the same time is that unlike other single-letter extensions, B was ratified (Apr/2024) much later than its component extensions Zba/Zbb/Zbs (Jun/2021). When "b" is specified, zba/zbb/zbs must be present to ensure backward compatibility with existing software and kernels that only look for the explicit component strings. When all three components zba/zbb/zbs are specified, "b" should also be present. Making "b" mandatory when all three components are present. Existing devicetrees with zba/zbb/zbs but without "b" will generate warnings that can be fixed in follow-up patches. Signed-off-by: Guodong Xu Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 6a4697b36b8d..beeb6612db31 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -109,6 +109,13 @@ properties: The standard C extension for compressed instructions, as ratified in the 20191213 version of the unprivileged ISA specification. + - const: b + description: + The standard B extension for bit manipulation instructions, as + ratified in the 20240411 version of the unprivileged ISA + specification. The B standard extension comprises instructions + provided by the Zba, Zbb, and Zbs extensions. + - const: v description: The standard V extension for vector operations, as ratified @@ -738,6 +745,30 @@ properties: then: contains: const: f + # B comprises Zba, Zbb, and Zbs + - if: + contains: + const: b + then: + allOf: + - contains: + const: zba + - contains: + const: zbb + - contains: + const: zbs + # Zba, Zbb, Zbs together require B + - if: + allOf: + - contains: + const: zba + - contains: + const: zbb + - contains: + const: zbs + then: + contains: + const: b # Zcb depends on Zca - if: contains: From b321256a4f36227e0c1ae54e8c6c48524dcba83d Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:19 +0800 Subject: [PATCH 522/757] dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are mandatory for the following profiles: - za64rs: Mandatory in RVA22U64, RVA23U64 - ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64 - ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64 - zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64 Ziccrse specifies the main memory must support "RsrvEventual", which is one (totally there are four) of the support level for Load-Reserved/ Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc. Ziccamoa specifies the main memory must support AMOArithmetic, among the four levels of PMA support defined for AMOs in the A extension. Thus it depends on Zaamo. Za64rs defines reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and Zawrs. Zawrs itself depends on Zalrsc too. Based on the relationship that "A" = Zaamo + Zalrsc, add the following dependencies checks: Za64rs -> Zalrsc or A Ziccrse -> Zalrsc or A Ziccamoa -> Zaamo or A Signed-off-by: Guodong Xu Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index beeb6612db31..e0bdd88bd24e 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -240,6 +240,12 @@ properties: as ratified at commit 4a69197e5617 ("Update to ratified state") of riscv-svvptc. + - const: za64rs + description: + The standard Za64rs extension for reservation set size of at most + 64 bytes, as ratified in RISC-V Profiles Version 1.0, with commit + b1d806605f87 ("Updated to ratified state.") + - const: zaamo description: | The standard Zaamo extension for atomic memory operations as @@ -381,6 +387,27 @@ properties: in commit 64074bc ("Update version numbers for Zfh/Zfinx") of riscv-isa-manual. + - const: ziccamoa + description: + The standard Ziccamoa extension for main memory (cacheability and + coherence) must support all atomics in A, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: ziccif + description: + The standard Ziccif extension for main memory (cacheability and + coherence) instruction fetch atomicity, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: zicclsm + description: + The standard Zicclsm extension for main memory (cacheability and + coherence) must support misaligned loads and stores, as ratified + in RISC-V Profiles Version 1.0, with commit b1d806605f87 ("Updated + to ratified state.") + - const: ziccrse description: The standard Ziccrse extension which provides forward progress @@ -769,6 +796,18 @@ properties: then: contains: const: b + # Za64rs and Ziccrse depend on Zalrsc or A + - if: + contains: + anyOf: + - const: za64rs + - const: ziccrse + then: + oneOf: + - contains: + const: zalrsc + - contains: + const: a # Zcb depends on Zca - if: contains: @@ -810,6 +849,16 @@ properties: then: contains: const: f + # Ziccamoa depends on Zaamo or A + - if: + contains: + const: ziccamoa + then: + oneOf: + - contains: + const: zaamo + - contains: + const: a # Zvfbfmin depends on V or Zve32f - if: contains: From c712413333f8e19cc3de4e9cd1a3ed8a53169cc9 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:20 +0800 Subject: [PATCH 523/757] dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their requirement status are: - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sscounterenw: Mandatory in RVA22S64, RVA23S64 - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index e0bdd88bd24e..31f1cc79fbd9 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -161,12 +161,26 @@ properties: behavioural changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: ssccptr + description: | + The standard Ssccptr extension for main memory (cacheability and + coherence) hardware page-table reads, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + - const: sscofpmf description: | The standard Sscofpmf supervisor-level extension for count overflow and mode-based filtering as ratified at commit 01d1df0 ("Add ability to manually trigger workflow. (#2)") of riscv-count-overflow. + - const: sscounterenw + description: | + The standard Sscounterenw extension for support writable enables + in scounteren for any supported counter, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + - const: ssnpm description: | The standard Ssnpm extension for next-mode pointer masking as @@ -179,6 +193,24 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: sstvala + description: | + The standard Sstvala extension for stval provides all needed values + as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + + - const: sstvecd + description: | + The standard Sstvecd extension for stvec supports Direct mode as + ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + + - const: ssu64xl + description: | + The standard Ssu64xl extension for UXLEN=64 must be supported, as + ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + - const: svade description: | The standard Svade supervisor-level extension for SW-managed PTE A/D From 89febd6a02768200fcfc86ee57f1ece632805bff Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Sat, 10 Jan 2026 13:18:21 +0800 Subject: [PATCH 524/757] dt-bindings: riscv: Add Sha and its comprised extensions Add descriptions for the Sha extension and the seven extensions it comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, and Ssstateen. Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6 "rva23/rvb23 ratified") as a new profile-defined extension that captures the full set of features that are mandated to be supported along with the H extension. Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state"). The requirement status for Sha and its comprised extension in RISC-V Profiles are: - Sha: Mandatory in RVA23S64 - H: Optional in RVA22S64; Mandatory in RVA23S64 - Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64 - Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64 - Shtvala: Optional in RVA22S64; Mandatory in RVA23S64 - Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64 - Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64 - Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64 - Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu Acked-by: Conor Dooley Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 31f1cc79fbd9..b43199764395 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -129,6 +129,57 @@ properties: Document Version 20211203. # multi-letter extensions, sorted alphanumerically + - const: sha + description: | + The standard Sha extension for augmented hypervisor extension as + ratified in RVA23 Profiles Version 1.0, with commit 0273f3c921b6 + ("rva23/rvb23 ratified"). + + Sha captures the full set of features that are mandated to be + supported along with the H extension. Sha comprises the following + extensions: H, Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, + Shvstvecd, and Ssstateen. + + - const: shcounterenw + description: | + The standard Shcounterenw extension for support writable enables + in hcounteren for any supported counter, as ratified in RISC-V + Profiles Version 1.0, with commit b1d806605f87 ("Updated to + ratified state.") + + - const: shgatpa + description: | + The standard Shgatpa extension indicates that for each supported + virtual memory scheme SvNN supported in satp, the corresponding + hgatp SvNNx4 mode must be supported. The hgatp mode Bare must + also be supported. It is ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + + - const: shtvala + description: | + The standard Shtvala extension for htval be written with the + faulting guest physical address in all circumstances permitted by + the ISA. It is ratified in RISC-V Profiles Version 1.0, with + commit b1d806605f87 ("Updated to ratified state.") + + - const: shvsatpa + description: | + The standard Shvsatpa extension for vsatp supporting all translation + modes supported in satp, as ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + + - const: shvstvala + description: | + The standard Shvstvala extension for vstval provides all needed + values as ratified in RISC-V Profiles Version 1.0, with commit + b1d806605f87 ("Updated to ratified state.") + + - const: shvstvecd + description: | + The standard Shvstvecd extension for vstvec supporting Direct mode, + as ratified in RISC-V Profiles Version 1.0, with commit b1d806605f87 + ("Updated to ratified state.") + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced @@ -187,6 +238,12 @@ properties: ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. + - const: ssstateen + description: | + The standard Ssstateen extension for supervisor-mode view of the + state-enable extension, as ratified in RISC-V Profiles Version 1.0, + with commit b1d806605f87 ("Updated to ratified state.") + - const: sstc description: | The standard Sstc supervisor-level extension for time compare as From a36b2aaae742dd2253063ee0cc447aa86f94b4fb Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Mon, 5 Jan 2026 15:29:09 -0600 Subject: [PATCH 525/757] dt-bindings: riscv: extensions: Drop unnecessary select schema The "select" schema is not necessary because this schema is referenced by riscv/cpus.yaml schema. Signed-off-by: Rob Herring (Arm) Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ------ 1 file changed, 6 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index b43199764395..89f520495c2a 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -24,12 +24,6 @@ description: | ratified states, with the exception of the I, Zicntr & Zihpm extensions. See the "i" property for more information. -select: - properties: - compatible: - contains: - const: riscv - properties: riscv,isa: description: From 178c08fd8ce53c77910fb16cc99e932049b6c6e8 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 13 Jan 2026 11:59:58 +0100 Subject: [PATCH 526/757] arm64: dts: mediatek: mt6331: Fix VCAM IO regulator name The ldo-vcamio regulator is named "vcam_io", however, the binding only allows "vcamio" as name: change it to the latter to resolve a dtbs_check warning. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6331.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6331.dtsi b/arch/arm64/boot/dts/mediatek/mt6331.dtsi index 243afbffa21f..7e7b96e8ca6f 100644 --- a/arch/arm64/boot/dts/mediatek/mt6331.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6331.dtsi @@ -217,7 +217,7 @@ }; mt6331_vcamio_reg: ldo-vcamio { - regulator-name = "vcam_io"; + regulator-name = "vcamio"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1800000>; regulator-ramp-delay = <0>; From aec5445dd7c8c6c84d46f2dbf07967ac54393595 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 13 Jan 2026 11:59:59 +0100 Subject: [PATCH 527/757] arm64: dts: mediatek: mt6795: Fix issues in SCPSYS node Add the "mediatek,mt6795-scpsys" compatible to the SCPSYS node and remove #power-domain-cells (retaining it only in the power controller subnode) to resolve dtbs_check warnings. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index 58833e5135c8..ae2aaa51c9ad 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -287,9 +287,8 @@ }; scpsys: syscon@10006000 { - compatible = "syscon", "simple-mfd"; + compatible = "mediatek,mt6795-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { From a40901fe6f5c27856b7112a6e635b13446ec4c7b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 13 Jan 2026 12:00:00 +0100 Subject: [PATCH 528/757] arm64: dts: mediatek: mt6795-xperia-m5: Rename PMIC leds node The MT6332 PMIC leds node was named "mt6332-led", however, the binding rightfully enforces using the generic node name "leds". Change it to the latter to resolve dtbs_check warnings. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index ecd13d089ceb..0e086dd487d9 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -507,7 +507,7 @@ */ interrupts = ; - mt6332-led { + leds { compatible = "mediatek,mt6332-led"; #address-cells = <1>; #size-cells = <0>; From 093d6e332259583a94d630897bdb07d6141bff57 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 13 Jan 2026 12:00:26 +0100 Subject: [PATCH 529/757] arm64: dts: mediatek: mt8173-evb: Add interrupts to DA9211 regulator Add the required pinmux and assign the right interrupts-extended to the DA9211 regulator (PIO pin 15). Reviewed-by: Matthias Brugger Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 51118a4149d8..1049877e6cda 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -117,6 +117,7 @@ buck: da9211@68 { compatible = "dlg,da9211"; reg = <0x68>; + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; regulators { da9211_vcpu_reg: BUCKA { @@ -179,6 +180,13 @@ }; }; + i2c1_pins_a: i2c1-pins { + pins-da9211 { + pinmux = ; + bias-pull-up; + }; + }; + mmc0_pins_default: mmc0-default-pins { pins-cmd-dat { pinmux = , From 32c5491a8d73713578560f515cccd4e9460d156d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 12 Jan 2026 15:55:58 +0100 Subject: [PATCH 530/757] arm64: dts: mediatek: mt7986a: Change compatible for SafeXcel crypto Following the changes in the binding for the SafeXcel crypto engine, add a SoC specific compatible to the existing crypto node and, while at it, also change the fallback compatible to inside-secure,safexcel-eip97ies as the eip97 one is deprecated. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 7790601586cc..9693f62fd013 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -231,7 +231,7 @@ }; crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; + compatible = "mediatek,mt7986-crypto", "inside-secure,safexcel-eip97ies"; reg = <0 0x10320000 0 0x40000>; interrupts = , , From d33d77044c37aa97f24e3e3adf2f781aba774db2 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 14 Jan 2026 17:26:04 +0800 Subject: [PATCH 531/757] arm64: dts: mediatek: mt8183-kukui: Clean up IT6505 regulator supply Align the name of the regulator with the design schematic. Also fix up the gpio property to the new "gpios" property name, and add the GPIO_ACTIVE_HIGH flag. The flag is actively ignored in Linux in favor of the old "enable-active-high" property; nevertheless it is the correct description. Signed-off-by: Chen-Yu Tsai Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 4b87d4940c8c..a8e257b21a88 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -44,10 +44,10 @@ clock-output-names = "clk32k"; }; - it6505_pp18_reg: regulator0 { + pp1800_it6505: regulator0 { compatible = "regulator-fixed"; - regulator-name = "it6505_pp18"; - gpio = <&pio 178 0>; + regulator-name = "pp1800_it6505"; + gpios = <&pio 178 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&pp1800_alw>; }; From 126058f8d80aa7176bb230ca03ec939a70435177 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 11:57:40 +0100 Subject: [PATCH 532/757] arm64: dts: amlogic: drop useless assigned-clock-parents Amlogic sound card assigned-clock-parents only have <0> and are useless. Remove them. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-parent-clock-cleanup-v1-1-31078b1e4a2c@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts | 1 - .../boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 1 - arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts | 1 - arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts | 1 - arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts | 1 - 51 files changed, 51 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 9611775b81ee..285c6ac1dd61 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -275,7 +275,6 @@ assigned-clocks = <&clkc CLKID_HIFI_PLL>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <589824000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts index abf6b63ea0d7..4c9cd0024efb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am.dts @@ -183,7 +183,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts index a85f383a1699..4bb1c2846c81 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts @@ -145,7 +145,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index 5b6716aeaae5..8ca7f6ec9adc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -208,7 +208,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index dd9da7a5ec5f..a1c5d10f2f54 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -245,7 +245,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index 015e3c7e3a91..c393954354d5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -165,7 +165,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts index 2d74456e685d..cdb522f5365a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts @@ -77,7 +77,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts index 0f48c32bec97..2d4071c51f3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-mnt-reform2.dts @@ -86,7 +86,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index 4321d08d11a6..7b5d78f97215 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -201,7 +201,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi index 8e3e3354ed67..a69d5531c540 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-dreambox.dtsi @@ -47,7 +47,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts index 369c5cf889b6..8758a68136ea 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts @@ -55,7 +55,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts index 654449afd3a4..a9478e2cce4d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts @@ -56,7 +56,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts index e20311386745..a2ff5040eadf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts @@ -44,7 +44,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index c81d7fdbe2f5..cac73c59a94f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -241,7 +241,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index 3bca8023638d..edb7ed6b0ec0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -102,7 +102,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts index 1b9097a30251..15795889cb53 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts @@ -46,7 +46,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index e95e193eaebc..794bde2db928 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -183,7 +183,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts index 4c1a75b926ee..dbd72fe0f53f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts @@ -39,7 +39,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index 2da49cfbde77..c2bf6f4cdfd2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -201,7 +201,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index b4f88ed6273b..8d216a594d7b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -136,7 +136,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts index 073b47ce8c3c..ff3ba97872ec 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-kii-pro.dts @@ -52,7 +52,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 2ecc6ebd5a43..5d9ddb814164 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -142,7 +142,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index c09da40ff7b0..ab8e06aa2b32 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -149,7 +149,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 12e26f99d4f0..5943bc810678 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -184,7 +184,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts index bfac00e76ba3..b5981c0b1494 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts @@ -75,7 +75,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts index c10f66031ecd..602777702984 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts @@ -24,7 +24,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 6ff567225fee..a4d354cc93a5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -115,7 +115,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts index ec281a9e9e77..a22a8a435427 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts @@ -23,7 +23,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts index 924414861b72..6a1b65bf84da 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts @@ -55,7 +55,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts index c6132fb71dfc..3a9a801f33d4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -130,7 +130,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index ca7c4e8e7cac..75db2a5c96b3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -135,7 +135,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts index cac15b89c573..9e571b96bde6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805y-xiaomi-aquaman.dts @@ -125,7 +125,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 4e89d6f6bb57..0a6664275bcb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -74,7 +74,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 6cbdfde00e12..277fb34981c7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -167,7 +167,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index 401064b0428d..fe1df108892c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -149,7 +149,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts index 8b41e340f919..9da495cca787 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dts @@ -57,7 +57,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts index a9c5881c9783..1e4d3fdd0b22 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-vero4k.dts @@ -98,7 +98,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 2a09b3d550e2..5b1aafe16d5c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -157,7 +157,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts index 773107cc47dd..81f5eb3da5dc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -93,7 +93,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts index 9d5a481b309f..9626a2621a3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts @@ -108,7 +108,6 @@ assigned-clocks = <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>, <&clkc CLKID_MPLL2>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 7daa9b122d5c..73aa6b5a5de7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -189,7 +189,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi index ac9c4c2673b1..cb8b0f98beb4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-libretech-cottonwood.dtsi @@ -207,7 +207,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts index 3c43d3490e14..7c67e459c602 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts index 445c1671ede7..e841c44c69de 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts index eeaff22edade..8d12bd1702d3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m2-pro.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts index 697855fec476..0cd306569312 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi-m5.dts @@ -64,7 +64,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts index 7b3a014d4cde..3c671676e453 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index ad886d446e96..db9124779b87 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -181,7 +181,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index e275b0f36b09..18b830a233a6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -246,7 +246,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts index e4a3a2a8ad06..ecb6aa79302d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts index fff92e0d6dd5..24a6a679b377 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts @@ -29,7 +29,6 @@ assigned-clocks = <&clkc CLKID_MPLL2>, <&clkc CLKID_MPLL0>, <&clkc CLKID_MPLL1>; - assigned-clock-parents = <0>, <0>, <0>; assigned-clock-rates = <294912000>, <270950400>, <393216000>; From 86124a8becb43eed3103f2459399daee8af2c99d Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 11:43:11 +0100 Subject: [PATCH 533/757] arm64: dts: amlogic: s4: assign mmc b clock to 24MHz The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. This assumption did hold true until but it now, but it is apparently not the case with s4. The clock has been reported to provide 1GHz instead. This is most likely due to how the bootloader is using the MMC clock on this platform. Regardless of why the MMC clock rate is 1GHz, if the MMC driver expects 24MHz, the clock should be properly assigned, so assign it. Reported-by: Nick Xie Closes: https://lore.kernel.org/linux-amlogic/20260113011931.40424-1-nick@khadas.com/ Fixes: 3ab9d54b5d84 ("arm64: dts: amlogic: enable some device nodes for S4") Tested-by: Nick Xie Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-s4-mmc-fixup-v3-1-a4d3e136b3f2@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index 9d99ed2994df..f314f07062ab 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -838,6 +838,9 @@ clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B>; + assigned-clock-rates = <24000000>; }; emmc: mmc@fe08c000 { From 3a115d42922cffc91b303992eadf220111d66c31 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 11:43:12 +0100 Subject: [PATCH 534/757] arm64: dts: amlogic: s4: fix mmc clock assignment MMC A and C are mis-represented as having their "clkin0" input connected to xtal while it is actually connected to the MMC clock, probably in an attempt to provide 24MHz to the device on this input. Fix this and assign the clock to 24MHz to actually provide the required rate. Fixes: 3ab9d54b5d84 ("arm64: dts: amlogic: enable some device nodes for S4") Tested-by: Nick Xie Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-s4-mmc-fixup-v3-2-a4d3e136b3f2@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index f314f07062ab..dfc0a30a6e61 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -819,13 +819,16 @@ reg = <0x0 0xfe088000 0x0 0x800>; interrupts = ; clocks = <&clkc_periphs CLKID_SDEMMC_A>, - <&xtal>, + <&clkc_periphs CLKID_SD_EMMC_A>, <&clkc_pll CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; cap-sdio-irq; keep-power-in-suspend; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>; + assigned-clock-rates = <24000000>; }; sd: mmc@fe08a000 { @@ -848,13 +851,16 @@ reg = <0x0 0xfe08c000 0x0 0x800>; interrupts = ; clocks = <&clkc_periphs CLKID_NAND>, - <&xtal>, + <&clkc_periphs CLKID_SD_EMMC_C>, <&clkc_pll CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_NAND_EMMC>; no-sdio; no-sd; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C>; + assigned-clock-rates = <24000000>; }; }; }; From 78a123f45a7e9ac2a59f0eff8a37d31773e7a021 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Mon, 12 Jan 2026 17:53:46 +0000 Subject: [PATCH 535/757] arm64: dts: ti: k3-am69-aquila: Change main_spi0/2 CS to GPIO mode Hardware chip select does not work correctly on main_spi0 and main_spi2 controllers. Testing shows main_spi2 loses CS state during runtime PM suspend, while main_spi0 cannot drive CS HIGH when bus is idle. Use GPIO-based chip select for both controllers. Fixes: 39ac6623b1d8 ("arm64: dts: ti: Add Aquila AM69 Support") Cc: stable@vger.kernel.org Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260112175350.79270-2-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi b/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi index 0866eb8a6f34..5119baf62a4c 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila.dtsi @@ -479,7 +479,7 @@ /* Aquila SPI_2 CS */ pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */ + J784S4_IOPAD(0x0cc, PIN_OUTPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ /* AQUILA D16 */ >; }; @@ -495,7 +495,7 @@ /* Aquila SPI_1 CS */ pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins { pinctrl-single,pins = < - J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */ + J784S4_IOPAD(0x09c, PIN_OUTPUT, 7) /* (AF35) MCASP0_AXR11.GPIO0_39 */ /* AQUILA D9 */ >; }; @@ -1204,6 +1204,7 @@ &main_spi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>; + cs-gpios = <&main_gpio0 51 GPIO_ACTIVE_LOW>; status = "disabled"; }; @@ -1211,6 +1212,7 @@ &main_spi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>; + cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>; status = "disabled"; }; From 319fff9c7d620af83d8ab67050a54f63f16ae4e8 Mon Sep 17 00:00:00 2001 From: Vitor Soares Date: Mon, 12 Jan 2026 17:53:47 +0000 Subject: [PATCH 536/757] arm64: dts: ti: k3-am69-aquila-clover: Change main_spi2 CS0 to GPIO mode Change CS0 from hardware chip select to GPIO-based chip select to align with the base aquila device tree configuration. Fixes: 9f748a6177e1 ("arm64: dts: ti: am69-aquila: Add Clover") Cc: stable@vger.kernel.org Signed-off-by: Vitor Soares Reviewed-by: Francesco Dolcini Link: https://patch.msgid.link/20260112175350.79270-3-ivitro@gmail.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts index c816ba3bfbdf..ec8ff4587715 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-aquila-clover.dts @@ -208,7 +208,8 @@ pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>, <&pinctrl_gpio_05>; - cs-gpios = <0>, <&wkup_gpio0 29 GPIO_ACTIVE_LOW>; + cs-gpios = <&main_gpio0 39 GPIO_ACTIVE_LOW>, + <&wkup_gpio0 29 GPIO_ACTIVE_LOW>; status = "okay"; tpm@1 { From 24c9d5fb8bbf5e8c9e6fc2beffeb80ac2da83de4 Mon Sep 17 00:00:00 2001 From: Abhash Kumar Jha Date: Mon, 12 Jan 2026 14:21:12 +0530 Subject: [PATCH 537/757] arm64: dts: ti: k3-j784s4-main.dtsi: Move c71_3 node to appropriate order The device tree nodes should be ordered by unit addresses in ascending order. Correct the order by moving the c71_3 DSP node at the end as it has a higher unit address. Signed-off-by: Abhash Kumar Jha Reviewed-by: Udit Kumar Link: https://patch.msgid.link/20260112085113.3476193-2-a-kumar2@ti.com Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 26 +++++++++++----------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 0160fe0da983..5b7830a3c097 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,19 +6,6 @@ */ &cbass_main { - c71_3: dsp@67800000 { - compatible = "ti,j721s2-c71-dsp"; - reg = <0x00 0x67800000 0x00 0x00080000>, - <0x00 0x67e00000 0x00 0x0000c000>; - reg-names = "l2sram", "l1dram"; - resets = <&k3_reset 40 1>; - firmware-name = "j784s4-c71_3-fw"; - ti,sci = <&sms>; - ti,sci-dev-id = <40>; - ti,sci-proc-ids = <0x33 0xff>; - status = "disabled"; - }; - pcie2_rc: pcie@2920000 { compatible = "ti,j784s4-pcie-host"; reg = <0x00 0x02920000 0x00 0x1000>, @@ -113,6 +100,19 @@ status = "disabled"; }; }; + + c71_3: dsp@67800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x67800000 0x00 0x00080000>, + <0x00 0x67e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + resets = <&k3_reset 40 1>; + firmware-name = "j784s4-c71_3-fw"; + ti,sci = <&sms>; + ti,sci-dev-id = <40>; + ti,sci-proc-ids = <0x33 0xff>; + status = "disabled"; + }; }; &scm_conf { From 61acc4428a7f52e0a13e226ba76f2ce2ca66c065 Mon Sep 17 00:00:00 2001 From: Abhash Kumar Jha Date: Mon, 12 Jan 2026 14:21:13 +0530 Subject: [PATCH 538/757] arm64: dts: ti: k3-j784s4-j742s2-main-common.dtsi: Refactor watchdog instances for j784s4 Each A72 core has one watchdog instance associated with it. Since j742s2 has 4 A72 cores, the common file should not define 8 watchdog instances. Refactor the last 4 extra watchdogs from the common file to j784s4 specific file, as j784s4 has 8 A72 cores and thus hardware description requires 8 watchdog instances. Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file") Signed-off-by: Abhash Kumar Jha Reviewed-by: Udit Kumar Link: https://patch.msgid.link/20260112085113.3476193-3-a-kumar2@ti.com Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 36 ------------------- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 36 +++++++++++++++++++ 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 9cc0901d58fb..c2636e624f18 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -2378,42 +2378,6 @@ assigned-clock-parents = <&k3_clks 351 4>; }; - watchdog4: watchdog@2240000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2240000 0x00 0x100>; - clocks = <&k3_clks 352 0>; - power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 352 0>; - assigned-clock-parents = <&k3_clks 352 4>; - }; - - watchdog5: watchdog@2250000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2250000 0x00 0x100>; - clocks = <&k3_clks 353 0>; - power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 353 0>; - assigned-clock-parents = <&k3_clks 353 4>; - }; - - watchdog6: watchdog@2260000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2260000 0x00 0x100>; - clocks = <&k3_clks 354 0>; - power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 354 0>; - assigned-clock-parents = <&k3_clks 354 4>; - }; - - watchdog7: watchdog@2270000 { - compatible = "ti,j7-rti-wdt"; - reg = <0x00 0x2270000 0x00 0x100>; - clocks = <&k3_clks 355 0>; - power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; - assigned-clocks = <&k3_clks 355 0>; - assigned-clock-parents = <&k3_clks 355 4>; - }; - /* * The following RTI instances are coupled with MCU R5Fs, c7x and * GPU so keeping them reserved as these will be used by their diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 5b7830a3c097..78fcd0c40abc 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -6,6 +6,42 @@ */ &cbass_main { + watchdog4: watchdog@2240000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2240000 0x00 0x100>; + clocks = <&k3_clks 352 0>; + power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 352 0>; + assigned-clock-parents = <&k3_clks 352 4>; + }; + + watchdog5: watchdog@2250000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2250000 0x00 0x100>; + clocks = <&k3_clks 353 0>; + power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 353 0>; + assigned-clock-parents = <&k3_clks 353 4>; + }; + + watchdog6: watchdog@2260000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2260000 0x00 0x100>; + clocks = <&k3_clks 354 0>; + power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 354 0>; + assigned-clock-parents = <&k3_clks 354 4>; + }; + + watchdog7: watchdog@2270000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2270000 0x00 0x100>; + clocks = <&k3_clks 355 0>; + power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 355 0>; + assigned-clock-parents = <&k3_clks 355 4>; + }; + pcie2_rc: pcie@2920000 { compatible = "ti,j784s4-pcie-host"; reg = <0x00 0x02920000 0x00 0x1000>, From 2c3b8260d1a0d9a388f2d30e3bbe50d93edfa2aa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 29 Dec 2025 15:28:07 +0100 Subject: [PATCH 539/757] arm64: dts: qcom: sm6125-ginkgo: Fix missing msm-id subtype qcom,msm-id property must consist of two numbers, where the second number is the subtype, as reported by dtbs_check: sm6125-xiaomi-ginkgo.dtb: / (xiaomi,ginkgo): qcom,msm-id:0: [394] is too short Xiaomi vendor DTS for Trinket IDP and QRD boards uses value of 0x10000, so put it here as well. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251229142806.241088-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts index 68a237215bd1..6b68e391cf3e 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-ginkgo.dts @@ -19,7 +19,7 @@ chassis-type = "handset"; /* required for bootloader to select correct board */ - qcom,msm-id = ; + qcom,msm-id = ; qcom,board-id = <22 0>; chosen { From 9e81c522680db5998c872fb91ff7877cf3d8ff42 Mon Sep 17 00:00:00 2001 From: Michael Orlitzky Date: Wed, 7 Jan 2026 06:29:22 -0500 Subject: [PATCH 540/757] riscv: dts: sophgo: enable hardware clock (RTC) on the Milk-V Pioneer These boards have a working hardware clock if you put a CR-1220 battery in them. We enable it using information from a 6.1.x vendor kernel. Reviewed-by: Chen Wang Signed-off-by: Michael Orlitzky Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 54d8386bf9c0..ecf8c1e29079 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -52,6 +52,17 @@ status = "okay"; }; +&i2c0 { + pinctrl-0 = <&i2c0_cfg>; + pinctrl-names = "default"; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_cfg>; pinctrl-names = "default"; @@ -89,6 +100,16 @@ }; }; + i2c0_cfg: i2c0-cfg { + i2c0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; + i2c1_cfg: i2c1-cfg { i2c1-pins { pinmux = , From 69330fd2368371c4eb47d60ace6bca09763d24a0 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 18:08:48 +0100 Subject: [PATCH 541/757] arm64: dts: amlogic: c3: assign the MMC signal clocks The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. Assign the clocks to make sure they are properly configured Fixes: 520b792e8317 ("arm64: dts: amlogic: add some device nodes for C3") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-1-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index 11e5323f95b7..4e6757a57fb9 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -969,6 +969,10 @@ no-sd; resets = <&reset RESET_SD_EMMC_A>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A>; + assigned-clock-rates = <24000000>; + }; sd: mmc@8a000 { @@ -984,6 +988,9 @@ no-sdio; resets = <&reset RESET_SD_EMMC_B>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B>; + assigned-clock-rates = <24000000>; }; nand: nand-controller@8d000 { From c6ccd0d9a253b59125e5c625139799b41f0de3e0 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 18:08:49 +0100 Subject: [PATCH 542/757] arm64: dts: amlogic: a1: align the mmc clock setup The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. A1 is particular in the way that is already has the mmc clock set to 24MHz by forcing the mux to select the board crystal. It works too, it is just slightly less readable. Align with what is being done with the other Amlogic platforms. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-2-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 27b68ed85c4c..348411411f3d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -674,11 +674,12 @@ clock-names = "core", "clkin0", "clkin1"; - assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>; - assigned-clock-parents = <&xtal>; resets = <&reset RESET_SD_EMMC_A>; power-domains = <&pwrc PWRC_SD_EMMC_ID>; status = "disabled"; + + assigned-clocks = <&clkc_periphs CLKID_SD_EMMC>; + assigned-clock-rates = <24000000>; }; }; From 13d3fe2318ef6e46d6fcfe13bc373827fdf2aeac Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 18:08:50 +0100 Subject: [PATCH 543/757] arm64: dts: amlogic: axg: assign the MMC signal clocks The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. Assign the clocks to make sure they are properly configured Fixes: 221cf34bac54 ("ARM64: dts: meson-axg: enable the eMMC controller") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-3-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index e95c91894968..cc72491eaf6f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -1960,6 +1960,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; sd_emmc_c: mmc@7000 { @@ -1972,6 +1975,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; nfc: nand-controller@7800 { From 406706559046eebc09a31e8ae5e78620bfd746fe Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 18:08:51 +0100 Subject: [PATCH 544/757] arm64: dts: amlogic: gx: assign the MMC signal clocks The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. Assign the clocks to make sure they are properly configured Fixes: 50662499f911 ("ARM64: dts: meson-gx: Use correct mmc clock source 0") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-4-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index f69923da07fe..a9c830a570cc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -824,6 +824,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -832,6 +835,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -840,6 +846,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index ba535010a3c9..e202d84f0672 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -894,6 +894,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_b { @@ -902,6 +905,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; &sd_emmc_c { @@ -910,6 +916,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; &simplefb_hdmi { From be2ff5fdb0e83e32d4ec4e68a69875cec0d14621 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 18:08:52 +0100 Subject: [PATCH 545/757] arm64: dts: amlogic: g12: assign the MMC B and C signal clocks The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. Assign the clocks to make sure they are properly configured Fixes: 4759fd87b928 ("arm64: dts: meson: g12a: add mmc nodes") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-5-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index ca455f634834..0085612cf735 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2443,6 +2443,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_B>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_B_CLK0>; + assigned-clock-rates = <24000000>; }; sd_emmc_c: mmc@ffe07000 { @@ -2455,6 +2458,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_C>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_C_CLK0>; + assigned-clock-rates = <24000000>; }; usb: usb@ffe09000 { From 3c941feaa363f1573a501452391ddf513394c84b Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Jan 2026 18:08:53 +0100 Subject: [PATCH 546/757] arm64: dts: amlogic: g12: assign the MMC A signal clock The amlogic MMC driver operate with the assumption that MMC clock is configured to provide 24MHz. It uses this path for low rates such as 400kHz. Assign the clock to make sure it is properly configured Fixes: 8a6b3ca2d361 ("arm64: dts: meson: g12a: add SDIO controller") Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-amlogic-mmc-clocks-followup-v1-6-a999fafbe0aa@baylibre.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 0085612cf735..00609d2da674 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -2431,6 +2431,9 @@ <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; resets = <&reset RESET_SD_EMMC_A>; + + assigned-clocks = <&clkc CLKID_SD_EMMC_A_CLK0>; + assigned-clock-rates = <24000000>; }; sd_emmc_b: mmc@ffe05000 { From 29deec49146162d06b17739c627d062191e03814 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Wed, 14 Jan 2026 23:48:36 +0100 Subject: [PATCH 547/757] arm64: dts: amlogic: Enable the npu node on Radxa Zero 2 The Zero2 is also an A311D just like the VIM3, enable its npu. Signed-off-by: Ricardo Pardini Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260114-arm64-dts-amlogic-radxa-zero2-additions-v1-1-8b5cdf328fde@pardini.net Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index 794bde2db928..0591331f61e5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -381,6 +381,10 @@ status = "okay"; }; +&npu { + status = "okay"; +}; + &saradc { status = "okay"; vref-supply = <&vddao_1v8>; From e9858fba558ced73133a685c8e76c04cb66d8244 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 11:41:12 +0100 Subject: [PATCH 548/757] arm64: dts: mediatek: mt7981b-openwrt-one: Add address/size cells to eth The ethernet node has two MAC subnodes and cannot use the default address/size cells: set address cells to 1 and size cells to 0. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts index 48b80af90438..b7ff7b8e1375 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -90,6 +90,8 @@ }; ð { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; /* WAN interface */ From f3b795d298a280687ed70211d51043ed5fc7a96a Mon Sep 17 00:00:00 2001 From: "Herve Codina (Schneider Electric)" Date: Wed, 14 Jan 2026 10:39:35 +0100 Subject: [PATCH 549/757] dt-bindings: soc: renesas: Document RZ/N1 GPIO Interrupt Multiplexer On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Wolfram Sang Reviewed-by: Rob Herring (Arm) Reviewed-by: Linus Walleij Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260114093938.1089936-7-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- .../soc/renesas/renesas,rzn1-gpioirqmux.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml new file mode 100644 index 000000000000..1a31c11bc3b4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer + +description: | + The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt + lines to the interrupt controller available in the SoC. + + It selects up to 8 of the 96 GPIO interrupt lines available and connect them + to 8 output interrupt lines. + +maintainers: + - Herve Codina + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-gpioirqmux + - const: renesas,rzn1-gpioirqmux + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: | + Specifies the mapping from external GPIO interrupt lines to the output + interrupts. The array has up to 8 items defining the mapping related to + the output line 0 (GIC 103) up to the output line 7 (GIC 110). + + The child interrupt number set in arrays items is computed using the + following formula: + gpio_bank * 32 + gpio_number + with: + - gpio_bank: The GPIO bank number + - 0 for GPIO0A, + - 1 for GPIO1A, + - 2 for GPIO2A + - gpio_number: Number of the gpio in the bank (0..31) + minItems: 1 + maxItems: 8 + +required: + - compatible + - reg + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + #include + + gic: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <3>; + }; + + interrupt-controller@51000480 { + compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux"; + reg = <0x51000480 0x20>; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0x7f>; + interrupt-map = + <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* line 0, GPIO1A.0 */ + <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* line 1, GPIO2A.25 */ + <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* line 3, GPIO0A.9 */ + }; From 4ef81dcac8f6e08b29c359ab147dd87a488d178c Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Thu, 20 Nov 2025 12:51:39 +0100 Subject: [PATCH 550/757] arm64: dts: renesas: rzg3e-smarc-som: Enable I3C support Enable I3C on RZ/G3E SMARC SoM. Signed-off-by: Tommaso Merciai Reviewed-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/9d1cf2cdb1c11f24378404142e4c8aff680c6961.1763638659.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index eb0de21d6716..3b571c096752 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -126,6 +126,14 @@ }; }; +&i3c { + pinctrl-0 = <&i3c_pins>; + pinctrl-names = "default"; + i2c-scl-hz = <400000>; + i3c-scl-hz = <12500000>; + status = "okay"; +}; + &mdio0 { phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", @@ -223,6 +231,12 @@ ; /* SDA2 */ }; + i3c_pins: i3c { + pinmux = , /* I3C0_SCL */ + ; /* I3C0_SDA */ + drive-push-pull; + }; + rtc_irq_pin: rtc-irq { pins = "PS1"; bias-pull-up; From ca91def749cea0cd8916f289c550c341b2d774dd Mon Sep 17 00:00:00 2001 From: "Herve Codina (Schneider Electric)" Date: Wed, 14 Jan 2026 10:39:34 +0100 Subject: [PATCH 551/757] ARM: dts: r9a06g032: Add GPIO controllers Add GPIO controllers (Synopsys DesignWare IPs) available in the r9a06g032 (RZ/N1D) SoC. Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Reviewed-by: Bartosz Golaszewski Reviewed-by: Geert Uytterhoeven Reviewed-by: Linus Walleij Link: https://patch.msgid.link/20260114093938.1089936-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 118 +++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 7c143bd5d7c9..932e39c3ddaf 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -515,6 +515,124 @@ ; }; + /* + * The GPIO mapping to the corresponding pins is not obvious. + * See the hardware documentation for details. + */ + gpio0: gpio@5000b000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000b000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO0>; + clock-names = "bus"; + + /* GPIO0a[0] connected to pin GPIO0 */ + /* GPIO0a[1..2] connected to pins GPIO3..4 */ + /* GPIO0a[3..4] connected to pins GPIO9..10 */ + /* GPIO0a[5] connected to pin GPIO12 */ + /* GPIO0a[6..7] connected to pins GPIO15..16 */ + /* GPIO0a[8..9] connected to pins GPIO21..22 */ + /* GPIO0a[10] connected to pin GPIO24 */ + /* GPIO0a[11..12] connected to pins GPIO27..28 */ + /* GPIO0a[13..14] connected to pins GPIO33..34 */ + /* GPIO0a[15] connected to pin GPIO36 */ + /* GPIO0a[16..17] connected to pins GPIO39..40 */ + /* GPIO0a[18..19] connected to pins GPIO45..46 */ + /* GPIO0a[20] connected to pin GPIO48 */ + /* GPIO0a[21..22] connected to pins GPIO51..52 */ + /* GPIO0a[23..24] connected to pins GPIO57..58 */ + /* GPIO0a[25..31] connected to pins GPIO62..68 */ + gpio0a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + + /* GPIO0b[0..1] connected to pins GPIO1..2 */ + /* GPIO0b[2..5] connected to pins GPIO5..8 */ + /* GPIO0b[6] connected to pin GPIO11 */ + /* GPIO0b[7..8] connected to pins GPIO13..14 */ + /* GPIO0b[9..12] connected to pins GPIO17..20 */ + /* GPIO0b[13] connected to pin GPIO23 */ + /* GPIO0b[14..15] connected to pins GPIO25..26 */ + /* GPIO0b[16..19] connected to pins GPIO29..32 */ + /* GPIO0b[20] connected to pin GPIO35 */ + /* GPIO0b[21..22] connected to pins GPIO37..38 */ + /* GPIO0b[23..26] connected to pins GPIO41..44 */ + /* GPIO0b[27] connected to pin GPIO47 */ + /* GPIO0b[28..29] connected to pins GPIO49..50 */ + /* GPIO0b[30..31] connected to pins GPIO53..54 */ + gpio0b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + }; + + gpio1: gpio@5000c000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000c000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO1>; + clock-names = "bus"; + + /* GPIO1a[0..4] connected to pins GPIO69..73 */ + /* GPIO1a[5..31] connected to pins GPIO95..121 */ + gpio1a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + + /* GPIO1b[0..1] connected to pins GPIO55..56 */ + /* GPIO1b[2..4] connected to pins GPIO59..61 */ + /* GPIO1b[5..25] connected to pins GPIO74..94 */ + /* GPIO1b[26..31] connected to pins GPIO150..155 */ + gpio1b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + }; + + gpio2: gpio@5000d000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5000d000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&sysctrl R9A06G032_HCLK_GPIO2>; + clock-names = "bus"; + + /* GPIO2a[0..27] connected to pins GPIO122..149 */ + /* GPIO2a[28..31] connected to pins GPIO156..159 */ + gpio2a: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + }; + + /* GPIO2b[0..9] connected to pins GPIO160..169 */ + gpio2b: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <10>; + }; + }; + can0: can@52104000 { compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg = <0x52104000 0x800>; From a684fa4d2270a6465b0c6e165ac28bd36614c9cf Mon Sep 17 00:00:00 2001 From: "Herve Codina (Schneider Electric)" Date: Wed, 14 Jan 2026 10:39:37 +0100 Subject: [PATCH 552/757] ARM: dts: r9a06g032: Add support for GPIO interrupts In the RZ/N1 SoC, the GPIO interrupts are multiplexed using the GPIO Interrupt Multiplexer. Add the multiplexer node and connect GPIO interrupt lines to the multiplexer. The interrupt-map available in the multiplexer node has to be updated in dts files depending on the GPIO usage. Indeed, the usage of an interrupt for a GPIO is board dependent. Up to 8 GPIOs can be used as an interrupt line (one per multiplexer output interrupt). Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Bartosz Golaszewski Reviewed-by: Linus Walleij Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Link: https://patch.msgid.link/20260114093938.1089936-9-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 932e39c3ddaf..f4f760aff28b 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -549,6 +549,14 @@ gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31>; + #interrupt-cells = <2>; }; /* GPIO0b[0..1] connected to pins GPIO1..2 */ @@ -590,6 +598,14 @@ gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = <32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63>; + #interrupt-cells = <2>; }; /* GPIO1b[0..1] connected to pins GPIO55..56 */ @@ -621,6 +637,14 @@ gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <32>; + + interrupt-controller; + interrupt-parent = <&gpioirqmux>; + interrupts = <64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95>; + #interrupt-cells = <2>; }; /* GPIO2b[0..9] connected to pins GPIO160..169 */ @@ -633,6 +657,23 @@ }; }; + gpioirqmux: interrupt-controller@51000480 { + compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux"; + reg = <0x51000480 0x20>; + #interrupt-cells = <1>; + #address-cells = <0>; + interrupt-map-mask = <0x7f>; + + /* + * Example mapping entry. Board DTs need to overwrite + * 'interrupt-map' with their specific mapping. Check + * the irqmux binding documentation for details. + */ + interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + can0: can@52104000 { compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; reg = <0x52104000 0x800>; From 615962473ba6ecde7da61d89adf85062972c2c4c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 12:36:08 +0100 Subject: [PATCH 553/757] arm64: dts: mediatek: mt8186-evb: Add vproc fixed regulator This board at the moment has no support for PMIC regulators, but the CCI requires a vproc regulator in order to both stop giving dtbs_check warnings and to actually probe. Since vproc is a system-critical regulator and the bootloader enables it at max voltage, model it (at least temporarily) as a regulator-fixed and assign it to CCI. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts index 2667a7424200..a941a931a07c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts @@ -22,6 +22,19 @@ device_type = "memory"; reg = <0 0x40000000 0 0x80000000>; }; + + vproc: regulator-vproc12 { + compatible = "regulator-fixed"; + regulator-name = "vproc12"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; +}; + +&cci { + proc-supply = <&vproc>; }; &i2c0 { From 10a46a7f6ecc243fb9f745c4ec5e1955b49d77b4 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Thu, 15 Jan 2026 11:00:13 +0800 Subject: [PATCH 554/757] dt-bindings: arm: amlogic: introduce specific compatibles for S4 family The Amlogic S4 SoC family includes multiple variants, such as the S805X2 and S905Y4. Currently, the bindings only define the generic "amlogic,s4" compatible. This patch introduces specific compatibles "amlogic,s805x2" and "amlogic,s905y4" to properly differentiate these SoCs while keeping "amlogic,s4" as the family fallback. This allows for more precise hardware description and future-proofing if SoC-specific quirks arise. Signed-off-by: Nick Xie Reviewed-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260115030015.1334517-2-nick@khadas.com Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/arm/amlogic.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 08d9963fe925..a885278bc4e2 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -245,6 +245,14 @@ properties: items: - enum: - amlogic,aq222 + - const: amlogic,s805x2 + - const: amlogic,s4 + + - description: Boards with the Amlogic Meson S4 S905Y4 SoC + items: + - enum: + - khadas,vim1s + - const: amlogic,s905y4 - const: amlogic,s4 - description: Boards with the Amlogic S6 S905X5 SoC From 31b72cc32c48205b4f9cf4b0531055be6a028607 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Thu, 15 Jan 2026 11:00:14 +0800 Subject: [PATCH 555/757] arm64: dts: meson-s4-aq222: update compatible string with s805x2 Update the compatible string for the Amlogic AQ222 board to include the specific SoC compatible "amlogic,s805x2". This aligns the device tree with the updated bindings which now differentiate between S4 family members (S805X2 vs S905Y4). Signed-off-by: Nick Xie Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260115030015.1334517-3-nick@khadas.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts index 6730c44642d2..0a3f81ea0fb0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts @@ -9,7 +9,7 @@ / { model = "Amlogic Meson S4 AQ222 Development Board"; - compatible = "amlogic,aq222", "amlogic,s4"; + compatible = "amlogic,aq222", "amlogic,s805x2", "amlogic,s4"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; From 44e3f867fd3f75123b0e8e460f723a115b0d8cd4 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Thu, 15 Jan 2026 11:00:15 +0800 Subject: [PATCH 556/757] arm64: dts: meson-s4-s905y4-khadas-vim1s: add initial device tree The Khadas VIM1S uses the Amlogic S905Y4 SoC, based on the Amlogic S4 SoC family, on a board with the same form factor as the VIM/VIM2/VIM3/VIM4 models. Serial debug console, ethernet, SD card work with this initial device tree. It features: - 2GB LPDDR4 RAM - 16GB eMMC 5.1 storage - 32MB SPI flash - 100M Ethernet - AP6256 Wireless (802.11 a/b/g/n/ac, BT5.0) - HDMI 2.1 video - 2x USB 2.0 ports - 1x USB-C (power) with USB 2.0 OTG - 2x LED's (1x red, 1x white) - 3x buttons (power, function, reset) - IR receiver - 40pin GPIO Header - 1x micro SD card slot Signed-off-by: Nick Xie Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260115030015.1334517-4-nick@khadas.com Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../amlogic/meson-s4-s905y4-khadas-vim1s.dts | 190 ++++++++++++++++++ 2 files changed, 191 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 219fb088c704..15f9c817e502 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-ugoos-am3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s905y4-khadas-vim1s.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m2-pro.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts new file mode 100644 index 000000000000..79ffc703a2e9 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2026 Khadas Technology Co., Ltd. + */ + +/dts-v1/; + +#include "meson-s4.dtsi" + +/ { + model = "Khadas VIM1S"; + compatible = "khadas,vim1s", "amlogic,s905y4", "amlogic,s4"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc0 = &emmc; /* eMMC */ + mmc1 = &sd; /* SD card */ + mmc2 = &sdio; /* SDIO */ + serial0 = &uart_b; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 52 MiB reserved for ARM Trusted Firmware */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x3400000>; + no-map; + }; + }; + + sdio_32k: sdio-32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&sdio_32k>; + clock-names = "ext_clock"; + }; + + main_5v: regulator-main-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sd_3v3: regulator-sd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "SD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio GPIOD_4 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + vddio_sd: regulator-vddio-sd { + compatible = "regulator-gpio"; + regulator-name = "VDDIO_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <1800000 1 + 3300000 0>; + }; + + /* SY8120B1ABC DC/DC Regulator. */ + vddcpu: regulator-vddcpu { + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <689000>; + regulator-max-microvolt = <1049000>; + + vin-supply = <&main_5v>; + + pwms = <&pwm_ij 1 1500 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + /* Voltage Duty-Cycle */ + voltage-table = <1049000 0>, + <1039000 3>, + <1029000 6>, + <1019000 9>, + <1009000 12>, + <999000 14>, + <989000 17>, + <979000 20>, + <969000 23>, + <959000 26>, + <949000 29>, + <939000 31>, + <929000 34>, + <919000 37>, + <909000 40>, + <899000 43>, + <889000 45>, + <879000 48>, + <869000 51>, + <859000 54>, + <849000 56>, + <839000 59>, + <829000 62>, + <819000 65>, + <809000 68>, + <799000 70>, + <789000 73>, + <779000 76>, + <769000 79>, + <759000 81>, + <749000 84>, + <739000 87>, + <729000 89>, + <719000 92>, + <709000 95>, + <699000 98>, + <689000 100>; + }; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_pins>; + pinctrl-names = "default"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins1>; + pinctrl-names = "default"; +}; + +&pwm_ij { + status = "okay"; +}; + +&sd { + status = "okay"; + pinctrl-0 = <&sdcard_pins>; + pinctrl-1 = <&sdcard_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&sd_3v3>; + vqmmc-supply = <&vddio_sd>; +}; + +&spicc0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spicc0_pins_x>; + cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>; +}; + +&uart_b { + status = "okay"; +}; From e1c9223adf1c2b7d84f29f2e7e6d9a4f749da2c0 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 14:10:35 +0100 Subject: [PATCH 557/757] arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address The PCIe and USB TPHYs are under the soc bus, which provides MMIO, and all nodes under that must use the bus, otherwise those would clearly be out of place. Add ranges to both the tphy(s) and assign the address to the main node to silence a dtbs_check warning, and fix the children to use the MMIO range of t-phy. Fixes: ("f693e6ba55ae arm64: dts: mediatek: mt7988: Add t-phy for ssusb1") Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 28 +++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index bec590d26659..8c9a5aba2579 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -629,20 +629,20 @@ tphy: t-phy@11c50000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x1000>; status = "disabled"; - tphyu2port0: usb-phy@11c50000 { - reg = <0 0x11c50000 0 0x700>; + tphyu2port0: usb-phy@0 { + reg = <0 0x700>; clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; clock-names = "ref"; #phy-cells = <1>; }; - tphyu3port0: usb-phy@11c50700 { - reg = <0 0x11c50700 0 0x900>; + tphyu3port0: usb-phy@700 { + reg = <0x700 0x900>; clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; clock-names = "ref"; #phy-cells = <1>; @@ -659,20 +659,20 @@ xsphy: xs-phy@11e10000 { compatible = "mediatek,mt7988-xsphy", "mediatek,xsphy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e10000 0x3900>; status = "disabled"; - xphyu2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x400>; + xphyu2port0: usb-phy@0 { + reg = <0 0x400>; clocks = <&infracfg CLK_INFRA_USB_UTMI>; clock-names = "ref"; #phy-cells = <1>; }; - xphyu3port0: usb-phy@11e13000 { - reg = <0 0x11e13400 0 0x500>; + xphyu3port0: usb-phy@3400 { + reg = <0x3400 0x500>; clocks = <&infracfg CLK_INFRA_USB_PIPE>; clock-names = "ref"; #phy-cells = <1>; From c5dc4812f6bf397b82290c540085e9ec98b47b30 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 6 Jan 2026 03:01:16 +0200 Subject: [PATCH 558/757] arm64: dts: qcom: qrb4210-rb2: Fix UART3 wakeup IRQ storm Follow commit 9c92d36b0b1e ("arm64: dts: qcom: qrb2210-rb1: Fix UART3 wakeup IRQ storm") and apply the similar fix to the RB2 platform. Having RX / TX pins as pull up and wakup interrupt as high-level triggered generates an interrupt storm when trying to suspend the device. Avoid the storm by using the falling edge trigger (as all other platforms do). Fixes: cab60b166575 ("arm64: dts: qcom: qrb4210-rb2: Enable bluetooth") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-6-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index 0cd36c54632f..5f8613150bdd 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -694,7 +694,7 @@ &uart3 { interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>; + <&tlmm 11 IRQ_TYPE_EDGE_FALLING>; pinctrl-0 = <&uart3_default>; pinctrl-1 = <&uart3_sleep>; pinctrl-names = "default", "sleep"; From 8bfb696ccdc5bcfad7a45b84c2c8a36757070e19 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 6 Jan 2026 03:01:17 +0200 Subject: [PATCH 559/757] arm64: dts: qcom: sdm845-db845c: drop CS from SPIO0 On SDM845 SPI uses hardware-provided chip select, while specifying cs-gpio makes the driver request GPIO pin, which on DB845c conflicts with the normal host controllers pinctrl entry. Drop the cs-gpios property to restore SPI functionality. Fixes: cb29e7106d4e ("arm64: dts: qcom: db845c: Add support for MCP2517FD") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-7-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index ce23f87e0316..ad283a79bcdb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -850,7 +850,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_default>; - cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; can@0 { compatible = "microchip,mcp2517fd"; From c303e89f7f17c29981d09f8beaaf60937ae8b1f2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 6 Jan 2026 03:01:18 +0200 Subject: [PATCH 560/757] arm64: dts: qcom: sdm845-db845c: specify power for WiFi CH1 Specify power supply for the second chain / antenna output of the onboard WiFi chip. Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-8-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index ad283a79bcdb..5118b776a9bb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -379,6 +379,12 @@ regulator-initial-mode = ; }; + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + vreg_l24a_3p075: ldo24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; @@ -1155,6 +1161,7 @@ vdd-1.8-xo-supply = <&vreg_l7a_1p8>; vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,snoc-host-cap-8bit-quirk; qcom,calibration-variant = "Thundercomm_DB845C"; From 0404b98c6bbca7a3b1e59a20d173fa149ac20194 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 6 Jan 2026 03:01:19 +0200 Subject: [PATCH 561/757] arm64: dts: qcom: sm8150: add uart13 Add UART13, typically used for Bluetooth connection on SM8150. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260106-wcn3990-pwrctl-v2-9-0386204328be@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index d36a3d214db4..97ca5275d740 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1693,6 +1693,15 @@ status = "disabled"; }; + uart13: serial@c8c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00c8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + status = "disabled"; + }; + i2c14: i2c@c90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00c90000 0 0x4000>; From d27267558fd25acb07d7ff28a7ff44eacf799eaf Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 5 Jan 2026 18:53:02 +0530 Subject: [PATCH 562/757] arm64: dts: qcom: lemans; Add EL2 overlay All the Lemans IOT variants boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Lemans IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-developer-touchpoints.html#uefi Signed-off-by: Mukesh Ojha Link: https://lore.kernel.org/r/20260105-kvmrprocv10-v10-14-022e96815380@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 10 +++++++ arch/arm64/boot/dts/qcom/lemans-el2.dtso | 35 ++++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/lemans-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index a5d6f451f85c..f80b5d9cf1e8 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -39,6 +39,10 @@ lemans-evk-camera-dtbs := lemans-evk.dtb lemans-evk-camera.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera-csi1-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-camera.dtb + +lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8216-samsung-fortuna3g.dtb @@ -146,6 +150,12 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb + +qcs9100-ride-el2-dtbs := qcs9100-ride.dtb lemans-el2.dtbo +qcs9100-ride-r3-el2-dtbs := qcs9100-ride-r3.dtb lemans-el2.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-el2.dtb +dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-arduino-imola.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb diff --git a/arch/arm64/boot/dts/qcom/lemans-el2.dtso b/arch/arm64/boot/dts/qcom/lemans-el2.dtso new file mode 100644 index 000000000000..ed615dce6c78 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/lemans-el2.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* + * Lemans specific modifications required to boot in EL2. + */ + +/dts-v1/; +/plugin/; + +&iris { + status = "disabled"; +}; + +&remoteproc_adsp { + iommus = <&apps_smmu 0x3000 0x0>; +}; + +&remoteproc_cdsp0 { + iommus = <&apps_smmu 0x21c0 0x0400>; +}; + +&remoteproc_cdsp1 { + iommus = <&apps_smmu 0x29c0 0x0400>; +}; + +&remoteproc_gpdsp0 { + iommus = <&apps_smmu 0x38a0 0x0>; +}; + +&remoteproc_gpdsp1 { + iommus = <&apps_smmu 0x38c0 0x0>; +}; From 5979010bcc665e9bcf41b22f111b3fe7fc4eadb1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 15 Jan 2026 12:22:10 +0000 Subject: [PATCH 563/757] arm64: dts: renesas: rzt2h-rzn2h-evk: Reorder ADC nodes Reorder the ADC nodes in the dts/i files so they follow the same alphabetical ordering used elsewhere in these files. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260115122210.3971063-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 55 +++--- .../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 127 +++++++------- .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 157 +++++++++--------- 3 files changed, 171 insertions(+), 168 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts index eedea1ce57e6..e9639bbb2d70 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts @@ -171,6 +171,34 @@ }; }; +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; +}; + &canfd { pinctrl-0 = <&can0_pins>; pinctrl-names = "default"; @@ -310,30 +338,3 @@ }; }; -&adc2 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; - - channel@4 { - reg = <0x4>; - }; - - channel@5 { - reg = <0x5>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts index 5d1da4de8af6..19f0a2c06753 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts @@ -210,6 +210,70 @@ }; }; +&adc2 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; + + channel@4 { + reg = <0x4>; + }; + + channel@5 { + reg = <0x5>; + }; + + channel@6 { + reg = <0x6>; + }; + + channel@7 { + reg = <0x7>; + }; + + channel@8 { + reg = <0x8>; + }; + + channel@9 { + reg = <0x9>; + }; + + channel@a { + reg = <0xa>; + }; + + channel@b { + reg = <0xb>; + }; + + channel@c { + reg = <0xc>; + }; + + channel@d { + reg = <0xd>; + }; + + channel@e { + reg = <0xe>; + }; +}; + #if CANFD_ENABLE &canfd { pinctrl-0 = <&can1_pins>; @@ -368,66 +432,3 @@ }; }; -&adc2 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; - - channel@4 { - reg = <0x4>; - }; - - channel@5 { - reg = <0x5>; - }; - - channel@6 { - reg = <0x6>; - }; - - channel@7 { - reg = <0x7>; - }; - - channel@8 { - reg = <0x8>; - }; - - channel@9 { - reg = <0x9>; - }; - - channel@a { - reg = <0xa>; - }; - - channel@b { - reg = <0xb>; - }; - - channel@c { - reg = <0xc>; - }; - - channel@d { - reg = <0xd>; - }; - - channel@e { - reg = <0xe>; - }; -}; diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index 63bd91690b54..510399febf29 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -69,6 +69,85 @@ #endif }; +/* + * ADC0 AN000 can be connected to a potentiometer on the board or + * exposed on ADC header. + * + * T2H: + * SW17[1] = ON, SW17[2] = OFF - Potentiometer + * SW17[1] = OFF, SW17[2] = ON - CN41 header + * N2H: + * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer + * DSW6[1] = ON, DSW6[2] = OFF - CN3 header + */ +&adc0 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; +}; + +/* + * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. + * + * T2H: + * SW18[1] = ON, SW18[2] = OFF - CN42 header + * SW18[1] = OFF, SW18[2] = ON - mikroBUS + * N2H: + * DSW6[3] = ON, DSW6[4] = OFF - CN4 header + * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS + * + * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[3] = ON, SW18[4] = OFF - CN42 header + * SW18[3] = OFF, SW18[4] = ON - Grove2 + * N2H: + * DSW6[5] = ON, DSW6[6] = OFF - CN4 header + * DSW6[5] = OFF, DSW6[6] = ON - Grove2 + * + * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. + * + * T2H: + * SW18[5] = ON, SW18[6] = OFF - CN42 header + * SW18[5] = OFF, SW18[6] = ON - Grove2 + * N2H: + * DSW6[7] = ON, DSW6[8] = OFF - CN4 header + * DSW6[7] = OFF, DSW6[8] = ON - Grove2 + */ +&adc1 { + status = "okay"; + + channel@0 { + reg = <0x0>; + }; + + channel@1 { + reg = <0x1>; + }; + + channel@2 { + reg = <0x2>; + }; + + channel@3 { + reg = <0x3>; + }; +}; + &ehci { dr_mode = "otg"; status = "okay"; @@ -315,81 +394,3 @@ timeout-sec = <60>; }; -/* - * ADC0 AN000 can be connected to a potentiometer on the board or - * exposed on ADC header. - * - * T2H: - * SW17[1] = ON, SW17[2] = OFF - Potentiometer - * SW17[1] = OFF, SW17[2] = ON - CN41 header - * N2H: - * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer - * DSW6[1] = ON, DSW6[2] = OFF - CN3 header - */ -&adc0 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; -}; - -/* - * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector. - * - * T2H: - * SW18[1] = ON, SW18[2] = OFF - CN42 header - * SW18[1] = OFF, SW18[2] = ON - mikroBUS - * N2H: - * DSW6[3] = ON, DSW6[4] = OFF - CN4 header - * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS - * - * ADC1 AN101 can be exposed on ADC header or on Grove2 connector. - * - * T2H: - * SW18[3] = ON, SW18[4] = OFF - CN42 header - * SW18[3] = OFF, SW18[4] = ON - Grove2 - * N2H: - * DSW6[5] = ON, DSW6[6] = OFF - CN4 header - * DSW6[5] = OFF, DSW6[6] = ON - Grove2 - * - * ADC1 AN102 can be exposed on ADC header or on Grove2 connector. - * - * T2H: - * SW18[5] = ON, SW18[6] = OFF - CN42 header - * SW18[5] = OFF, SW18[6] = ON - Grove2 - * N2H: - * DSW6[7] = ON, DSW6[8] = OFF - CN4 header - * DSW6[7] = OFF, DSW6[8] = ON - Grove2 - */ -&adc1 { - status = "okay"; - - channel@0 { - reg = <0x0>; - }; - - channel@1 { - reg = <0x1>; - }; - - channel@2 { - reg = <0x2>; - }; - - channel@3 { - reg = <0x3>; - }; -}; From 474530ef050b77482365de8c595b491f1d4ba683 Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Wed, 14 Jan 2026 23:05:50 +0530 Subject: [PATCH 564/757] arm64: dts: ti: k3-{j784s4-j742s2/j721s2}-mcu-wakeup: Add HSM M4F node The TI K3 J721S2, J784S4 and J742S2 SoCs have a HSM (High Security Module) M4F core in the Wakeup Voltage Domain which could be used to run secure services like Authentication. Add Device Tree Node definitions for the HSM core in the respective SoC wakeup dtsi files. The HSM node is reserved to be loaded and booted by the early-stage bootloader. The firmware-name property is defined at the SoC level since the HSM is not a general-purpose remote core and boards are unlikely to use separate firmware. If needed in exceptional cases, board-specific device trees can override this property. Signed-off-by: Beleswar Padhi Reviewed-by: Bryan Brattlof Link: https://patch.msgid.link/20260114173551.2545088-2-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 17 +++++++++++++++++ .../arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi | 4 ++++ .../ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 17 +++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index fd01437726ab..32ee8031cfcb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -766,4 +766,21 @@ /* reserved for MCU_R5F0_1 */ status = "reserved"; }; + + hsm: remoteproc@43c00000 { + compatible = "ti,hsm-m4fss"; + /* contiguous regions but instantiated separately in HW */ + reg = <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names = "sram0_0", "sram0_1", "sram1"; + resets = <&k3_reset 304 1>; + firmware-name = "j721s2-hsm-m4f-fw"; + bootph-pre-ram; + ti,sci = <&sms>; + ti,sci-dev-id = <304>; + ti,sci-proc-ids = <0x80 0xff>; + /* reserved for early-stage bootloader */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi index 61db2348d6a4..2f40afcfa67c 100644 --- a/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi @@ -15,3 +15,7 @@ &mcu_r5fss0_core1 { firmware-name = "j742s2-mcu-r5f0_1-fw"; }; + +&hsm { + firmware-name = "j742s2-hsm-m4f-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index cc22bfb5f599..df37902c963f 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -762,4 +762,21 @@ /* reserved for MCU_R5F0_1 */ status = "reserved"; }; + + hsm: remoteproc@43c00000 { + compatible = "ti,hsm-m4fss"; + /* contiguous regions but instantiated separately in HW */ + reg = <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names = "sram0_0", "sram0_1", "sram1"; + resets = <&k3_reset 371 1>; + firmware-name = "j784s4-hsm-m4f-fw"; + bootph-pre-ram; + ti,sci = <&sms>; + ti,sci-dev-id = <371>; + ti,sci-proc-ids = <0x80 0xff>; + /* reserved for early-stage bootloader */ + status = "reserved"; + }; }; From ac838e45b46f33ae8ab7195892f4dcf1143a161b Mon Sep 17 00:00:00 2001 From: Beleswar Padhi Date: Wed, 14 Jan 2026 23:05:51 +0530 Subject: [PATCH 565/757] arm64: dts: ti: k3-am62p-j722s-common-main: Add HSM M4F node The TI K3 AM62P and J722S SoCs have a HSM (High Security Module) M4F core in the MAIN Voltage Domain which could be used to run secure services like Authentication. Add Device Tree Node definitions for the HSM core in the respective SoC common main dtsi file. The HSM node is reserved to be loaded and booted by the early-stage bootloader. The firmware-name property is defined at the SoC level since the HSM is not a general-purpose remote core and boards are unlikely to use separate firmware. If needed in exceptional cases, board-specific device trees can override this property. The corresponding reg ranges of HSM node has also been added to its parent node's (cbass_main bus) ranges property. Signed-off-by: Beleswar Padhi Reviewed-by: Udit Kumar Reviewed-by: Bryan Brattlof Link: https://patch.msgid.link/20260114173551.2545088-3-b-padhi@ti.com Signed-off-by: Nishanth Menon --- .../boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 1 + 4 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 3cf7c2b3ce2d..0e1af2a69ca2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -1117,4 +1117,21 @@ clocks = <&k3_clks 204 2>; power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; + + hsm: remoteproc@43c00000 { + compatible = "ti,hsm-m4fss"; + /* contiguous regions but instantiated separately in HW */ + reg = <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names = "sram0_0", "sram0_1", "sram1"; + resets = <&k3_reset 225 1>; + firmware-name = "am62p-hsm-m4f-fw"; + bootph-pre-ram; + ti,sci = <&dmsc>; + ti,sci-dev-id = <225>; + ti,sci-proc-ids = <0x80 0xff>; + /* reserved for early-stage bootloader */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi index e2c01328eb29..9d6266d6ddb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -96,6 +96,7 @@ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi index 873415ec4fa3..9ee5d0c8ffd1 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -429,6 +429,11 @@ firmware-name = "j722s-wkup-r5f0_0-fw"; }; +/* MAIN domain overrides */ +&hsm { + firmware-name = "j722s-hsm-m4f-fw"; +}; + &main_conf { serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi index c8b634c34677..059c65ece183 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -173,6 +173,7 @@ <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ From 11a6a5bb72ce271de24330fd859e83f7bc281609 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 15 Jan 2026 14:14:18 +0100 Subject: [PATCH 566/757] arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix CMA node Fix the size of the CMA node by making it a 64bit size. This was probably a copy&paste mistake. Also drop the unneeded alignment. Fixes: 1c3c4df06f9d ("arm64: dts: ti: Add support for Kontron SMARC-sAM67") Signed-off-by: Michael Walle Link: https://patch.msgid.link/20260115131431.1521102-2-mwalle@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts index 7169d934adac..3be6c6d19def 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -85,8 +85,7 @@ linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0x10000000>; - alignment = <0x2000>; + size = <0x00 0x10000000>; linux,cma-default; }; From 53289af62b66812d07a7b0f5f9d62f429c94d317 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 15 Jan 2026 14:14:19 +0100 Subject: [PATCH 567/757] arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix SD card regulator The property "enable-active-high" was missing, as the default is active-low. Add it. Fixes: 1c3c4df06f9d ("arm64: dts: ti: Add support for Kontron SMARC-sAM67") Signed-off-by: Michael Walle Link: https://patch.msgid.link/20260115131431.1521102-3-mwalle@kernel.org Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts index 3be6c6d19def..95234c8460ed 100644 --- a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -173,6 +173,7 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc_3p3_s0>; regulator-boot-on; + enable-active-high; enable-gpios = <&main_gpio0 7 GPIO_ACTIVE_HIGH>; gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; states = <3300000 0x0>, From a3ceeadb287ce35eedc4cf0f55e1295d69617354 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 19 Nov 2025 09:37:28 +0000 Subject: [PATCH 568/757] dt-bindings: tegra: pmc: Update aotag as an optional aperture Not all Tegra SoCs or all versions of a particular Tegra SoC may include the AOTAG aperture. This change makes "aotag" as an optional aperture for Tegra234 and Tegra264. Co-developed-by: Prathamesh Shete Signed-off-by: Prathamesh Shete Signed-off-by: Jon Hunter Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- .../bindings/arm/tegra/nvidia,tegra186-pmc.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml index be70819020c5..dcd1c5376507 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -19,15 +19,15 @@ properties: - nvidia,tegra264-pmc reg: - minItems: 4 + minItems: 3 maxItems: 5 reg-names: - minItems: 4 + minItems: 3 items: - const: pmc - const: wake - - const: aotag + - enum: [ aotag, scratch, misc ] - enum: [ scratch, misc ] - const: misc @@ -51,6 +51,7 @@ allOf: then: properties: reg: + minItems: 4 maxItems: 4 reg-names: maxItems: 4 @@ -73,7 +74,9 @@ allOf: properties: compatible: contains: - const: nvidia,tegra234-pmc + enum: + - nvidia,tegra234-pmc + - nvidia,tegra264-pmc then: properties: reg-names: From d3b9e6d5b4da3961d8cc4fce1d867f89621420cb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 5 Nov 2025 20:53:40 +0100 Subject: [PATCH 569/757] dt-bindings: memory: tegra: Document DBB clock for Tegra264 Accesses to external memory are routed through the data backbone (DBB) on Tegra264. A separate clock feeds this path and needs to be enabled whenever an IP block makes an access to external memory. The external memory controller driver is the best place to control this clock since it knows how many devices are actively accessing memory. Document the presence of this clock on Tegra264 only. Acked-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- .../memory-controllers/nvidia,tegra186-mc.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index b901f1b3e0fc..7b03b589168b 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -92,10 +92,14 @@ patternProperties: clocks: items: - description: external memory clock + - description: data backbone clock + minItems: 1 clock-names: items: - const: emc + - const: dbb + minItems: 1 "#interconnect-cells": const: 0 @@ -115,6 +119,9 @@ patternProperties: reg: maxItems: 1 + clocks: + maxItems: 1 + - if: properties: compatible: @@ -124,6 +131,9 @@ patternProperties: reg: minItems: 2 + clocks: + maxItems: 1 + - if: properties: compatible: @@ -133,6 +143,9 @@ patternProperties: reg: minItems: 2 + clocks: + maxItems: 1 + - if: properties: compatible: From 8a59954192eba2d9dd2248dcc7b1f458c082eff2 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Tue, 13 Jan 2026 05:49:34 +0000 Subject: [PATCH 570/757] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add a new device tree binding document for nvidia,tegra264-cmdqv. Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv property. This property is a phandle to the CMDQV device node, allowing the SMMU driver to associate with its corresponding CMDQV instance. Restrict this property usage to Nvidia Tegra264 only. Reviewed-by: Rob Herring (Arm) Acked-by: Nicolin Chen Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- .../bindings/iommu/arm,smmu-v3.yaml | 27 +++++++++++- .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 +++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..82957334bea2 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -20,7 +20,12 @@ properties: $nodename: pattern: "^iommu@[0-9a-f]*" compatible: - const: arm,smmu-v3 + oneOf: + - const: arm,smmu-v3 + - items: + - enum: + - nvidia,tegra264-smmu + - const: arm,smmu-v3 reg: maxItems: 1 @@ -58,6 +63,15 @@ properties: msi-parent: true + nvidia,cmdqv: + description: | + A phandle to its pairing CMDQV extension for an implementation on NVIDIA + Tegra SoC. + + If this property is absent, CMDQ-Virtualization won't be used and SMMU + will only use its own CMDQ. + $ref: /schemas/types.yaml#/definitions/phandle + hisilicon,broken-prefetch-cmd: type: boolean description: Avoid sending CMD_PREFETCH_* commands to the SMMU. @@ -69,6 +83,17 @@ properties: register access with page 0 offsets. Set for Cavium ThunderX2 silicon that doesn't support SMMU page1 register space. +allOf: + - if: + not: + properties: + compatible: + contains: + const: nvidia,tegra264-smmu + then: + properties: + nvidia,cmdqv: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml new file mode 100644 index 000000000000..3f5006a59805 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 CMDQV + +description: + The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation + on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU. + +maintainers: + - Nicolin Chen + +properties: + compatible: + const: nvidia,tegra264-cmdqv + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + cmdqv@5200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x5200000 0x830000>; + interrupts = ; + }; From 7226664bf952c4cfddccd74b154a7d994608d153 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 16 Jan 2026 08:55:31 +0800 Subject: [PATCH 571/757] arm64: dts: rockchip: Fix SD card support for RK3576 EVB1 When runtime suspend is enabled, the associated power domain is powered off, which resets the registers, including the power control bit. As a result, the card loses power during runtime suspend. The card should still be able to process I/O with the help of mmc_blk_mq_rw_recovery(), which is suboptimal. To address this issue, we must use vmmc-supply with a GPIO based method to maintain power to the card. Also, add cd-gpios method to make hot-plug work correctly during idle periods. Fixes: f135a1a07352 ("arm64: dts: rockchip: Add rk3576 evb1 board") Cc: stable@vger.kernel.org Signed-off-by: Shawn Lin Link: https://patch.msgid.link/1768524932-163929-5-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-evb1-v10.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts index 0789733c2073..f5746bc2970b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-evb1-v10.dts @@ -223,6 +223,18 @@ vin-supply = <&vcc_3v3_s3>; }; + vcc3v3_sd: regulator-vcc-3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s0>; + }; + vcc_ufs_s0: regulator-vcc-ufs-s0 { compatible = "regulator-fixed"; regulator-name = "vcc_ufs_s0"; @@ -904,6 +916,12 @@ }; }; + sdmmc { + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { usb_host_pwren: usb-host-pwren { rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; @@ -958,11 +976,15 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; max-frequency = <200000000>; no-sdio; no-mmc; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vccio_sd_s0>; status = "okay"; }; From a9c1acebfe0484343a443d082e039ca77186ed22 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Fri, 16 Jan 2026 08:55:32 +0800 Subject: [PATCH 572/757] arm64: dts: rockchip: Fix SD card support for RK3576 Nanopi R76s When runtime suspend is enabled, the associated power domain is powered off, which resets the registers, including the power control bit. As a result, the card loses power during runtime suspend. The card should still be able to process I/O with the help of mmc_blk_mq_rw_recovery(), which is suboptimal. To address this issue, we must use vmmc-supply with a GPIO based method to maintain power to the card and store valid tuning phases. Also, add cd-gpios method to make hot-plug work correctly during idle periods. Fixes: 7fee88882704 ("arm64: dts: rockchip: Add devicetree for the FriendlyElec NanoPi R76S") Cc: stable@vger.kernel.org Signed-off-by: Shawn Lin Tested-by: Marco Schirrmeister Link: https://patch.msgid.link/1768524932-163929-6-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3576-nanopi-r76s.dts | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts index 31fbefaeceab..7ec27b05ff10 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts +++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts @@ -192,6 +192,18 @@ regulator-name = "vcc_3v3_s0"; vin-supply = <&vcc_3v3_s3>; }; + + vcc3v3_sd: regulator-vcc-3v3-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwren>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s0>; + }; }; &combphy0_ps { @@ -726,6 +738,12 @@ }; }; + sdmmc { + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + usb { usb_otg0_pwren_h: usb-otg0-pwren-h { rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; @@ -751,11 +769,14 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; disable-wp; no-mmc; no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>; sd-uhs-sdr104; - vmmc-supply = <&vcc_3v3_s3>; + vmmc-supply = <&vcc3v3_sd>; vqmmc-supply = <&vccio_sd_s0>; status = "okay"; }; From 4f3df9abf44bd92ecd5d8c3018ddefa7f5bf74d0 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 15 Jan 2026 00:07:03 +0100 Subject: [PATCH 573/757] arm64: dts: rockchip: Use phandle for i2c_lvds_blc on rk3368-lion haikou i2c@0 on i2cmux2 does already have a phandle i2c_lvds_blc defined. Use this one instead of replicating the hierarchy again, as this might result in strange errors if the lion dtsi is changed at some point in the future. Reviewed-by: Quentin Schulz Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260114230707.4175162-2-heiko@sntech.de Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3368-lion-haikou.dts | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts index ab70ee5f561a..abd1af97456a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts @@ -18,16 +18,6 @@ stdout-path = "serial0:115200n8"; }; - i2cmux2 { - i2c@0 { - eeprom: eeprom@50 { - compatible = "atmel,24c01"; - pagesize = <8>; - reg = <0x50>; - }; - }; - }; - leds { pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>; @@ -68,6 +58,14 @@ }; }; +&i2c_lvds_blc { + eeprom: eeprom@50 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x50>; + }; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; From 6d60168c6d2f76917b3f71d2a6807c6d8dd24363 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 15 Jan 2026 00:07:04 +0100 Subject: [PATCH 574/757] arm64: dts: rockchip: Add HDMI node to RK3368 Add the HDMI controller node to the main SoC devicetree and hook it into the VOP. Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260114230707.4175162-3-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368.dtsi | 43 ++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index f9e24b25274b..98d350768fd2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -883,6 +883,11 @@ reg = <0>; remote-endpoint = <&dsi_in_vop>; }; + + vop_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_vop>; + }; }; }; @@ -941,6 +946,37 @@ status = "disabled"; }; + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3368-dw-hdmi"; + reg = <0x0 0xff980000 0x0 0x20000>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; + clock-names = "iahb", "isfr", "cec"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>; + power-domains = <&power RK3368_PD_VIO>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + + hdmi_in_vop: endpoint { + remote-endpoint = <&vop_out_hdmi>; + }; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + hevc_mmu: iommu@ff9a0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9a0440 0x0 0x40>, @@ -1204,6 +1240,13 @@ }; }; + hdmi { + hdmi_i2c_xfer: hdmi-i2c-xfer { + rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, From 385430244e85e245f071ab158f7e4c7b2b5d99cb Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 15 Jan 2026 00:07:05 +0100 Subject: [PATCH 575/757] arm64: dts: rockchip: Enable HDMI output on RK3368-Lion-Haikou Enable the VOP and HDMI controller on the Lion-Haikou board. Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20260114230707.4175162-4-heiko@sntech.de Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3368-lion-haikou.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 5 +++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts index abd1af97456a..ec843a1b0266 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts @@ -58,6 +58,14 @@ }; }; +&display_subsystem { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + &i2c_lvds_blc { eeprom: eeprom@50 { compatible = "atmel,24c01"; @@ -101,6 +109,14 @@ status = "disabled"; }; +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&haikou_pin_hog>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi index 61c52bd91784..4b4305b90055 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -164,6 +164,11 @@ status = "okay"; }; +&hdmi { + avdd-0v9-supply = <&vdd10_video>; + avdd-1v8-supply = <&vcc18_video>; +}; + &i2c0 { status = "okay"; From f03f3e0a77a72f6f6284aff0da6d21d6508e57ac Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 15 Jan 2026 00:07:06 +0100 Subject: [PATCH 576/757] arm64: dts: rockchip: Enable pwm1 on rk3368-lion-haikou The pwm1 is exposed as BLT_CTRL signal on the MISC I/O pin header of the haikou baseboard and the Qseven standard specifies this signal is only for PWM (either for a panel backlight or generic PWM). So enable it in the Haikou baseboard for Lion. Suggested-by: Quentin Schulz Signed-off-by: Heiko Stuebner Reviewed-by: Quentin Schulz Link: https://patch.msgid.link/20260114230707.4175162-5-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts index ec843a1b0266..1b3a498d3624 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou.dts @@ -74,6 +74,10 @@ }; }; +&pwm1 { + status = "okay"; +}; + &sdmmc { bus-width = <4>; cap-mmc-highspeed; From 7f43ac104af7d3d4158ec306d4ca1c897ecce78c Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 15 Jan 2026 00:07:07 +0100 Subject: [PATCH 577/757] arm64: dts: rockchip: Add the Video-Demo overlay for Lion Haikou The video-demo adapter also works on the Lion SoM when running on a Haikou baseboard, so add an overlay for it. Tested-by: Quentin Schulz Signed-off-by: Heiko Stuebner Link: https://patch.msgid.link/20260114230707.4175162-6-heiko@sntech.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../rk3368-lion-haikou-video-demo.dtso | 170 ++++++++++++++++++ 2 files changed, 175 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 31a501a1717e..5417f7d6ad98 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lba3368.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou-video-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb @@ -243,6 +244,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou-haikou-video-demo.dtb px30-ringneck-haikou-haikou-video-demo-dtbs := px30-ringneck-haikou.dtb \ px30-ringneck-haikou-video-demo.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou-haikou-video-demo.dtb +rk3368-lion-haikou-haikou-video-demo-dtbs := rk3368-lion-haikou.dtb \ + rk3368-lion-haikou-video-demo.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou-haikou-video-demo.dtb rk3399-puma-haikou-haikou-video-demo-dtbs := rk3399-puma-haikou.dtb \ rk3399-puma-haikou-video-demo.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso new file mode 100644 index 000000000000..2db0f3d9495b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion-haikou-video-demo.dtso @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Lion system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm1 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = ; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&dphy { + status = "okay"; +}; + +&i2c_gp2 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = ; + irq-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; From b38dd256e11a4c8bd5a893e11fc42d493939c907 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Thu, 27 Nov 2025 16:29:42 -0500 Subject: [PATCH 578/757] arm64: dts: qcom: x1e: bus is 40-bits (fix 64GB models) Unlike the phone SoCs this was copied from, x1e has a 40-bit physical bus. The upper address space is used to support more than 32GB of memory. This fixes issues when DMA buffers are allocated outside the 36-bit range. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Jonathan Marek Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251127212943.24480-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index f464ff3b89cb..01434f8a5300 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -791,8 +791,8 @@ #address-cells = <2>; #size-cells = <2>; - dma-ranges = <0 0 0 0 0x10 0>; - ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x100 0>; + ranges = <0 0 0 0 0x100 0>; gcc: clock-controller@100000 { compatible = "qcom,x1e80100-gcc"; From a1338b39c14ddf50b841e891833786037dec6de4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Wed, 19 Nov 2025 09:45:42 +0100 Subject: [PATCH 579/757] arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodes The Thinkpad T14s embeds a transparent 4lanes DP->HDMI transceiver connected to the third QMP Combo PHY 4 lanes. Add all the data routing, disable mode switching and specify the QMP Combo PHY should be in DP-Only mode to route the 4 lanes to the underlying DP phy. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20251119-topic-x1e80100-hdmi-v7-3-2bee0e66cc1b@linaro.org Signed-off-by: Bjorn Andersson --- .../qcom/x1e78100-lenovo-thinkpad-t14s.dtsi | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi index b45e377a22c6..4d7fd51f370b 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dtsi @@ -62,6 +62,45 @@ }; }; + hdmi-bridge { + compatible = "realtek,rtd2171"; + + pinctrl-0 = <&hdmi_hpd_default>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_bridge_dp_in: endpoint { + remote-endpoint = <&usb_1_ss2_qmpphy_out_dp>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_bridge_tmds_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&hdmi_bridge_tmds_out>; + }; + }; + }; + pmic-glink { compatible = "qcom,x1e80100-pmic-glink", "qcom,sm8550-pmic-glink", @@ -1076,6 +1115,14 @@ link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; }; +&mdss_dp2 { + status = "okay"; +}; + +&mdss_dp2_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; +}; + &mdss_dp3 { /delete-property/ #sound-dai-cells; @@ -1371,6 +1418,12 @@ output-low; }; + hdmi_hpd_default: hdmi-hpd-default-state { + pins = "gpio126"; + function = "usb2_dp"; + bias-disable; + }; + tpad_default: tpad-default-state { pins = "gpio3"; function = "gpio"; @@ -1602,6 +1655,34 @@ remote-endpoint = <&retimer_ss1_ss_in>; }; +&usb_1_ss2_qmpphy { + vdda-phy-supply = <&vreg_l2j_1p2>; + vdda-pll-supply = <&vreg_l2d_0p9>; + + /delete-property/ mode-switch; + /delete-property/ orientation-switch; + + status = "okay"; + + ports { + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + /delete-node/ endpoint; + + usb_1_ss2_qmpphy_out_dp: endpoint@0 { + reg = <0>; + + data-lanes = <3 2 1 0>; + remote-endpoint = <&hdmi_bridge_dp_in>; + }; + + /* No USB3 lanes connected */ + }; + }; +}; + &usb_2 { status = "okay"; }; From 90a58ffa9c55831b557ae4819adbe280ea04d3e8 Mon Sep 17 00:00:00 2001 From: Jianping Li Date: Mon, 17 Nov 2025 15:08:19 +0800 Subject: [PATCH 580/757] arm64: dts: qcom: kodiak: Add memory region for audiopd Add reserved memory region for audio PD dynamic loading and remote heap requirement. Also add LPASS and ADSP_HEAP VMIDs. Signed-off-by: Jianping Li Link: https://lore.kernel.org/r/20251117070819.492-1-jianping.li@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index f478c5e1d2d5..6079e67ea829 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -190,6 +190,11 @@ qcom,client-id = <1>; qcom,vmid = ; }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 { + reg = <0x0 0x9cb80000 0x0 0x800000>; + no-map; + }; }; cpus { @@ -4436,6 +4441,9 @@ qcom,glink-channels = "fastrpcglink-apps-dsp"; label = "adsp"; qcom,non-secure-domain; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = ; #address-cells = <1>; #size-cells = <0>; From a91b64f55d0697cfa554a1c112479d66db6b0ed4 Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Tue, 28 Oct 2025 18:11:42 +0800 Subject: [PATCH 581/757] arm64: dts: qcom: lemans: enable static TPDM Enable static TPDM device for lemans. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan Acked-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20251028-add_static_tpdm_support-v4-3-84e21b98e727@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/lemans.dtsi | 105 +++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 6788e4d5b413..808827b83553 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2985,6 +2985,14 @@ <&apss_funnel1_out>; }; }; + + port@5 { + reg = <5>; + + funnel1_in5: endpoint { + remote-endpoint = <&dlct0_funnel_out>; + }; + }; }; }; @@ -3142,6 +3150,60 @@ }; }; + tpda@4ad3000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x4ad3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@10 { + reg = <16>; + dlct0_tpda_in16: endpoint { + remote-endpoint = <&turing0_funnel_out>; + }; + }; + }; + + out-ports { + port { + dlct0_tpda_out: endpoint { + remote-endpoint = + <&dlct0_funnel_in0>; + }; + }; + }; + + }; + + funnel@4ad4000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4ad4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + dlct0_funnel_in0: endpoint { + remote-endpoint = <&dlct0_tpda_out>; + }; + }; + }; + + out-ports { + port { + dlct0_funnel_out: endpoint { + remote-endpoint = <&funnel1_in5>; + }; + }; + }; + }; + funnel@4b04000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x0 0x4b04000 0x0 0x1000>; @@ -3414,6 +3476,35 @@ clock-names = "apb_pclk"; }; + funnel@4b83000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x4b83000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + turing0_funnel_in1: endpoint { + remote-endpoint = <&turing_llm_tpdm_out>; + }; + }; + }; + + out-ports { + port { + turing0_funnel_out: endpoint { + remote-endpoint = <&dlct0_tpda_in16>; + }; + }; + }; + }; + etm@6040000 { compatible = "arm,primecell"; reg = <0x0 0x6040000 0x0 0x1000>; @@ -8490,6 +8581,20 @@ ; }; + turing-llm-tpdm { + compatible = "qcom,coresight-static-tpdm"; + + qcom,cmb-element-bits = <32>; + + out-ports { + port { + turing_llm_tpdm_out: endpoint { + remote-endpoint = <&turing0_funnel_in1>; + }; + }; + }; + }; + pcie0: pcie@1c00000 { compatible = "qcom,pcie-sa8775p"; reg = <0x0 0x01c00000 0x0 0x3000>, From 919f6cd469c605f1de2269d46d04ebf80a1af568 Mon Sep 17 00:00:00 2001 From: sheetal Date: Mon, 29 Sep 2025 16:29:27 +0530 Subject: [PATCH 582/757] dt-bindings: dma: Update ADMA bindings for tegra264 - Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal Reviewed-by: Rob Herring (Arm) Acked-by: Thierry Reding Signed-off-by: Thierry Reding --- .../bindings/dma/nvidia,tegra210-adma.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index da0235e451d6..269a1f7ebdbb 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -46,7 +46,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 32 + maxItems: 64 clocks: description: Must contain one entry for the ADMA module clock @@ -86,6 +86,19 @@ allOf: reg: items: - description: Full address space range of DMA registers. + interrupts: + maxItems: 22 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + properties: + interrupts: + maxItems: 32 - if: properties: From dff8af7c5220c691661ca4b3e2348b58d050092c Mon Sep 17 00:00:00 2001 From: Charan Pedumuru Date: Sun, 4 Jan 2026 11:23:04 +0000 Subject: [PATCH 583/757] dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema Convert NVIDIA Tegra NAND Flash Controller binding to YAML format. Changes during Conversion: - Define new properties `power-domains` and `operating-points-v2` because the existing in tree DTS uses them. - Modify MAINTAINERS references to point the created YAML file. Signed-off-by: Charan Pedumuru Reviewed-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- .../bindings/mtd/nvidia,tegra20-nand.yaml | 102 ++++++++++++++++++ .../bindings/mtd/nvidia-tegra20-nand.txt | 64 ----------- MAINTAINERS | 2 +- 3 files changed, 103 insertions(+), 65 deletions(-) create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml delete mode 100644 Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml new file mode 100644 index 000000000000..b417d72fa0de --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/nvidia,tegra20-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra NAND Flash Controller + +maintainers: + - Jonathan Hunter + +allOf: + - $ref: nand-controller.yaml + +description: + The NVIDIA NAND controller provides an interface between NVIDIA SoCs + and raw NAND flash devices. It supports standard NAND operations, + hardware-assisted ECC, OOB data access, and DMA transfers, and + integrates with the Linux MTD NAND subsystem for reliable flash management. + +properties: + compatible: + const: nvidia,tegra20-nand + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: nand + + resets: + maxItems: 1 + + reset-names: + items: + - const: nand + + power-domains: + maxItems: 1 + + operating-points-v2: + maxItems: 1 + +patternProperties: + '^nand@': + type: object + description: Individual NAND chip connected to the NAND controller + $ref: raw-nand-chip.yaml# + + properties: + reg: + maximum: 5 + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-bus-width = <8>; + nand-on-flash-bbt; + nand-ecc-algo = "bch"; + nand-ecc-strength = <8>; + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt deleted file mode 100644 index 4a00ec2b2540..000000000000 --- a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +++ /dev/null @@ -1,64 +0,0 @@ -NVIDIA Tegra NAND Flash controller - -Required properties: -- compatible: Must be one of: - - "nvidia,tegra20-nand" -- reg: MMIO address range -- interrupts: interrupt output of the NFC controller -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - nand -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - nand - -Optional children nodes: -Individual NAND chips are children of the NAND controller node. Currently -only one NAND chip supported. - -Required children node properties: -- reg: An integer ranging from 1 to 6 representing the CS line to use. - -Optional children node properties: -- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only - "hw" is supported. -- nand-ecc-algo: string, algorithm of NAND ECC. - Supported values with "hw" ECC mode are: "rs", "bch". -- nand-bus-width : See nand-controller.yaml -- nand-on-flash-bbt: See nand-controller.yaml -- nand-ecc-strength: integer representing the number of bits to correct - per ECC step (always 512). Supported strength using HW ECC - modes are: - - RS: 4, 6, 8 - - BCH: 4, 8, 14, 16 -- nand-ecc-maximize: See nand-controller.yaml -- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM - are chosen. -- wp-gpios: GPIO specifier for the write protect pin. - -Optional child node of NAND chip nodes: -Partitions: see mtd.yaml - - Example: - nand-controller@70008000 { - compatible = "nvidia,tegra20-nand"; - reg = <0x70008000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; - clock-names = "nand"; - resets = <&tegra_car 13>; - reset-names = "nand"; - - nand@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - nand-bus-width = <8>; - nand-on-flash-bbt; - nand-ecc-algo = "bch"; - nand-ecc-strength = <8>; - wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; - }; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..c856aed83bb0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25678,7 +25678,7 @@ TEGRA NAND DRIVER M: Stefan Agner M: Lucas Stach S: Maintained -F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt +F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.yaml F: drivers/mtd/nand/raw/tegra_nand.c TEGRA PWM DRIVER From 58e69e8f9c9a4df948dfc554c26b8f4adf505636 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Tue, 21 Oct 2025 23:32:30 -0700 Subject: [PATCH 584/757] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm Kaanapali, which is compatible with X1E80100, use fallback to indicate this. Signed-off-by: Jingyi Wang Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20251021-knp-cpufreq-v2-1-95391d66c84e@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 9d99af46e531..90bfde66cc4a 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - qcom,glymur-cpucp-mbox + - qcom,kaanapali-cpucp-mbox - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: From ea2b1a4f192d8e3a435a03d8e8ae21cf9ab7e112 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:43 -0600 Subject: [PATCH 585/757] arm64: dts: broadcom: Remove unused and undocumented nodes The "silabs,si3226x" and "brcm,bdc-v0.16" nodes have no documentation and no driver in the kernel, so remove them. They can be added back with proper documentation if there is a need for them. Note that if both USB ports have similar memory maps in relationship to their USB PHY nodes, it looks like the device controller should have been at 0x12000, not 0x21000? Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-4-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- .../boot/dts/broadcom/northstar2/ns2-svk.dts | 16 ---------------- .../dts/broadcom/stingray/stingray-usb.dtsi | 19 ------------------- 2 files changed, 35 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index 5939d342aec7..f06472edd4a1 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -106,22 +106,6 @@ &ssp0 { status = "okay"; - - slic@0 { - compatible = "silabs,si3226x"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - pl022,interface = <0>; - pl022,slave-tx-disable = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - }; }; &ssp1 { diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi index ac4f7b8f9273..3fa9e57185b2 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi @@ -31,16 +31,6 @@ status = "disabled"; }; - bdc0: usb@2000 { - compatible = "brcm,bdc-v0.16"; - reg = <0x0 0x00002000 0x0 0x1000>; - interrupts = ; - phys = <&usbphy0 0>, <&usbphy0 1>; - phy-names = "phy0", "phy1"; - dma-coherent; - status = "disabled"; - }; - usbphy1: usb-phy@10000 { compatible = "brcm,sr-usb-combo-phy"; reg = <0x0 0x00010000 0x0 0x100>; @@ -65,13 +55,4 @@ status = "disabled"; }; - bdc1: usb@21000 { - compatible = "brcm,bdc-v0.16"; - reg = <0x0 0x00021000 0x0 0x1000>; - interrupts = ; - phys = <&usbphy2>; - phy-names = "phy0"; - dma-coherent; - status = "disabled"; - }; }; From dd19c37519aa82d615fee53b7f68adc726ab4ae6 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:44 -0600 Subject: [PATCH 586/757] arm64: dts: broadcom: stingray: Rework clock nodes The stringray-clocks.dtsi is oddly included in the middle of a bus node and is only included in one place, so collapse it into stingray.dtsi. Move the fixed and fixed-factor clock nodes to the root as they are not part of the bus. Rename the node names to use preferred names. Drop the unnecessary 1:1 fixed-factor clock providers. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-5-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- .../dts/broadcom/stingray/stingray-clock.dtsi | 182 ------------------ .../boot/dts/broadcom/stingray/stingray.dtsi | 124 +++++++++++- 2 files changed, 120 insertions(+), 186 deletions(-) delete mode 100644 arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi deleted file mode 100644 index 10a106aca229..000000000000 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-clock.dtsi +++ /dev/null @@ -1,182 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2016-2017 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - crmu_ref25m: crmu_ref25m { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&osc>; - clock-div = <2>; - clock-mult = <1>; - }; - - genpll0: genpll0@1d104 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll0"; - reg = <0x0001d104 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll0", "clk_125m", "clk_scr", - "clk_250", "clk_pcie_axi", - "clk_paxc_axi_x2", - "clk_paxc_axi"; - }; - - genpll2: genpll2@1d1ac { - #clock-cells = <1>; - compatible = "brcm,sr-genpll2"; - reg = <0x0001d1ac 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll2", "clk_nic", - "clk_ts_500_ref", "clk_125_nitro", - "clk_chimp", "clk_nic_flash", - "clk_fs"; - }; - - genpll3: genpll3@1d1e0 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll3"; - reg = <0x0001d1e0 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll3", "clk_hsls", - "clk_sdio"; - }; - - genpll4: genpll4@1d214 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll4"; - reg = <0x0001d214 0x32>, - <0x0001c854 0x4>; - clocks = <&osc>; - clock-output-names = "genpll4", "clk_ccn", - "clk_tpiu_pll", "clk_noc", - "clk_chclk_fs4", - "clk_bridge_fscpu"; - }; - - genpll5: genpll5@1d248 { - #clock-cells = <1>; - compatible = "brcm,sr-genpll5"; - reg = <0x0001d248 0x32>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "genpll5", "clk_fs4_hf", - "clk_crypto_ae", "clk_raid_ae"; - }; - - lcpll0: lcpll0@1d0c4 { - #clock-cells = <1>; - compatible = "brcm,sr-lcpll0"; - reg = <0x0001d0c4 0x3c>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll0", "clk_sata_refp", - "clk_sata_refn", "clk_sata_350", - "clk_sata_500"; - }; - - lcpll1: lcpll1@1d138 { - #clock-cells = <1>; - compatible = "brcm,sr-lcpll1"; - reg = <0x0001d138 0x3c>, - <0x0001c870 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll1", "clk_wan", - "clk_usb_ref", - "clk_crmu_ts"; - }; - - hsls_clk: hsls_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 1>; - clock-div = <1>; - clock-mult = <1>; - }; - - hsls_div2_clk: hsls_div2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; - clock-div = <2>; - clock-mult = <1>; - - }; - - hsls_div4_clk: hsls_div4_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - hsls_25m_clk: hsls_25m_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&crmu_ref25m>; - clock-div = <1>; - clock-mult = <1>; - }; - - hsls_25m_div2_clk: hsls_25m_div2_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&hsls_25m_clk>; - clock-div = <2>; - clock-mult = <1>; - }; - - sdio0_clk: sdio0_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; - clock-div = <1>; - clock-mult = <1>; - }; - - sdio1_clk: sdio1_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; - clock-div = <1>; - clock-mult = <1>; - }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 857fa427e195..9b015b8e1bb1 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -30,6 +30,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include #include / { @@ -159,6 +160,45 @@ reg = <0 0x60401000 0 0x38c>; }; + osc: clock-50000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + crmu_ref25m: hsls_25m_clk: clock-25000000 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&osc>; + clock-div = <2>; + clock-mult = <1>; + }; + + hsls_div2_clk: hsls_div2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; + clock-div = <2>; + clock-mult = <1>; + + }; + + hsls_div4_clk: hsls_div4_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll3 BCM_SR_GENPLL3_HSLS_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsls_25m_div2_clk: clock-12500000 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hsls_25m_clk>; + clock-div = <2>; + clock-mult = <1>; + }; + scr { compatible = "simple-bus"; #address-cells = <1>; @@ -269,8 +309,6 @@ #size-cells = <1>; ranges = <0x0 0x0 0x66400000 0x100000>; - #include "stingray-clock.dtsi" - otp: otp@1c400 { compatible = "brcm,ocotp-v2"; reg = <0x0001c400 0x68>; @@ -283,6 +321,84 @@ reg = <0x0001d000 0x400>; }; + lcpll0: clock-controller@1d0c4 { + #clock-cells = <1>; + compatible = "brcm,sr-lcpll0"; + reg = <0x0001d0c4 0x3c>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll0", "clk_sata_refp", + "clk_sata_refn", "clk_sata_350", + "clk_sata_500"; + }; + + genpll0: clock-controller@1d104 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll0"; + reg = <0x0001d104 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll0", "clk_125m", "clk_scr", + "clk_250", "clk_pcie_axi", + "clk_paxc_axi_x2", + "clk_paxc_axi"; + }; + + lcpll1: clock-controller@1d138 { + #clock-cells = <1>; + compatible = "brcm,sr-lcpll1"; + reg = <0x0001d138 0x3c>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll1", "clk_wan", + "clk_usb_ref", + "clk_crmu_ts"; + }; + + genpll2: clock-controller@1d1ac { + #clock-cells = <1>; + compatible = "brcm,sr-genpll2"; + reg = <0x0001d1ac 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll2", "clk_nic", + "clk_ts_500_ref", "clk_125_nitro", + "clk_chimp", "clk_nic_flash", + "clk_fs"; + }; + + genpll3: clock-controller@1d1e0 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll3"; + reg = <0x0001d1e0 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll3", "clk_hsls", + "clk_sdio"; + }; + + genpll4: clock-controller@1d214 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll4"; + reg = <0x0001d214 0x32>, + <0x0001c854 0x4>; + clocks = <&osc>; + clock-output-names = "genpll4", "clk_ccn", + "clk_tpiu_pll", "clk_noc", + "clk_chclk_fs4", + "clk_bridge_fscpu"; + }; + + genpll5: clock-controller@1d248 { + #clock-cells = <1>; + compatible = "brcm,sr-genpll5"; + reg = <0x0001d248 0x32>, + <0x0001c870 0x4>; + clocks = <&osc>; + clock-output-names = "genpll5", "clk_fs4_hf", + "clk_crypto_ae", "clk_raid_ae"; + }; + gpio_crmu: gpio@24800 { compatible = "brcm,iproc-gpio"; reg = <0x00024800 0x4c>; @@ -593,7 +709,7 @@ reg = <0x003f1000 0x100>; interrupts = ; bus-width = <8>; - clocks = <&sdio0_clk>; + clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; iommus = <&smmu 0x6002 0x0000>; status = "disabled"; }; @@ -603,7 +719,7 @@ reg = <0x003f2000 0x100>; interrupts = ; bus-width = <8>; - clocks = <&sdio1_clk>; + clocks = <&genpll3 BCM_SR_GENPLL3_SDIO_CLK>; iommus = <&smmu 0x6003 0x0000>; status = "disabled"; }; From 71220e15f38823dcc21b7297fc9161fd42d08d96 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:45 -0600 Subject: [PATCH 587/757] arm64: dts: broadcom: stingray: Fix 'simple-bus' node names Fix 'simple-bus' node names to follow the defined pattern. Nodes with 'reg' or 'ranges' addresses should also have a unit-address. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-6-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- .../dts/broadcom/stingray/stingray-fs4.dtsi | 2 +- .../dts/broadcom/stingray/stingray-pcie.dtsi | 2 +- .../dts/broadcom/stingray/stingray-usb.dtsi | 2 +- .../boot/dts/broadcom/stingray/stingray.dtsi | 18 +++++++++--------- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi index 9666969c8c88..cf3cb9199ce4 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi @@ -30,7 +30,7 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - fs4: fs4 { + fs4: fs4-bus@67000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi index 663e51756746..fbb2621d1b29 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi @@ -38,7 +38,7 @@ pcie8: pcie@60400000 { phy-names = "pcie-phy"; }; -pcie-ss { +pcie-ss-bus@40000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi index 3fa9e57185b2..850988287e48 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi @@ -2,7 +2,7 @@ /* *Copyright(c) 2018 Broadcom */ - usb { + usb-bus@68500000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 9b015b8e1bb1..f9f77b2639c5 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -199,7 +199,7 @@ clock-mult = <1>; }; - scr { + scr-bus@61000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -303,7 +303,7 @@ }; }; - crmu: crmu { + crmu: crmu-bus@66400000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -412,7 +412,7 @@ #include "stingray-pcie.dtsi" #include "stingray-usb.dtsi" - hsls { + hsls-bus@68900000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -725,7 +725,7 @@ }; }; - tmons { + tmons-bus@8f100000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -814,18 +814,18 @@ }; }; - nic-hsls { + nic-hsls-bus@60800000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x7fffffff>; + ranges = <0x0 0x0 0x60800000 0x6fffff>; - nic_i2c0: i2c@60826100 { + nic_i2c0: i2c@26100 { compatible = "brcm,iproc-nic-i2c"; #address-cells = <1>; #size-cells = <0>; - reg = <0x60826100 0x100>, - <0x60e00408 0x1000>; + reg = <0x026100 0x100>, + <0x600408 0x1000>; brcm,ape-hsls-addr-mask = <0x03400000>; clock-frequency = <100000>; status = "disabled"; From 8a4cac07eaf243a33e1256671a1864cdd994138f Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:46 -0600 Subject: [PATCH 588/757] arm64: dts: broadcom: stingray: Move raid nodes out of bus The 'raid' nodes are not MMIO devices and are not part of a bus, so move them to the root level. Drop the unit-addresses as they don't have any address. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-7-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- .../dts/broadcom/stingray/stingray-fs4.dtsi | 128 +++++++++--------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi index cf3cb9199ce4..d704c4ab2147 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-fs4.dtsi @@ -51,68 +51,68 @@ msi-parent = <&gic_its 0x4300>; #mbox-cells = <3>; }; - - raid0: raid@0 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 0 0x1 0xff00>, - <&raid_mbox 1 0x1 0xff00>, - <&raid_mbox 2 0x1 0xff00>, - <&raid_mbox 3 0x1 0xff00>; - }; - - raid1: raid@1 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 4 0x1 0xff00>, - <&raid_mbox 5 0x1 0xff00>, - <&raid_mbox 6 0x1 0xff00>, - <&raid_mbox 7 0x1 0xff00>; - }; - - raid2: raid@2 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 8 0x1 0xff00>, - <&raid_mbox 9 0x1 0xff00>, - <&raid_mbox 10 0x1 0xff00>, - <&raid_mbox 11 0x1 0xff00>; - }; - - raid3: raid@3 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 12 0x1 0xff00>, - <&raid_mbox 13 0x1 0xff00>, - <&raid_mbox 14 0x1 0xff00>, - <&raid_mbox 15 0x1 0xff00>; - }; - - raid4: raid@4 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 16 0x1 0xff00>, - <&raid_mbox 17 0x1 0xff00>, - <&raid_mbox 18 0x1 0xff00>, - <&raid_mbox 19 0x1 0xff00>; - }; - - raid5: raid@5 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 20 0x1 0xff00>, - <&raid_mbox 21 0x1 0xff00>, - <&raid_mbox 22 0x1 0xff00>, - <&raid_mbox 23 0x1 0xff00>; - }; - - raid6: raid@6 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 24 0x1 0xff00>, - <&raid_mbox 25 0x1 0xff00>, - <&raid_mbox 26 0x1 0xff00>, - <&raid_mbox 27 0x1 0xff00>; - }; - - raid7: raid@7 { - compatible = "brcm,iproc-sba-v2"; - mboxes = <&raid_mbox 28 0x1 0xff00>, - <&raid_mbox 29 0x1 0xff00>, - <&raid_mbox 30 0x1 0xff00>, - <&raid_mbox 31 0x1 0xff00>; - }; + }; + + raid0: raid-0 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 0 0x1 0xff00>, + <&raid_mbox 1 0x1 0xff00>, + <&raid_mbox 2 0x1 0xff00>, + <&raid_mbox 3 0x1 0xff00>; + }; + + raid1: raid-1 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 4 0x1 0xff00>, + <&raid_mbox 5 0x1 0xff00>, + <&raid_mbox 6 0x1 0xff00>, + <&raid_mbox 7 0x1 0xff00>; + }; + + raid2: raid-2 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 8 0x1 0xff00>, + <&raid_mbox 9 0x1 0xff00>, + <&raid_mbox 10 0x1 0xff00>, + <&raid_mbox 11 0x1 0xff00>; + }; + + raid3: raid-3 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 12 0x1 0xff00>, + <&raid_mbox 13 0x1 0xff00>, + <&raid_mbox 14 0x1 0xff00>, + <&raid_mbox 15 0x1 0xff00>; + }; + + raid4: raid-4 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 16 0x1 0xff00>, + <&raid_mbox 17 0x1 0xff00>, + <&raid_mbox 18 0x1 0xff00>, + <&raid_mbox 19 0x1 0xff00>; + }; + + raid5: raid-5 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 20 0x1 0xff00>, + <&raid_mbox 21 0x1 0xff00>, + <&raid_mbox 22 0x1 0xff00>, + <&raid_mbox 23 0x1 0xff00>; + }; + + raid6: raid-6 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 24 0x1 0xff00>, + <&raid_mbox 25 0x1 0xff00>, + <&raid_mbox 26 0x1 0xff00>, + <&raid_mbox 27 0x1 0xff00>; + }; + + raid7: raid-7 { + compatible = "brcm,iproc-sba-v2"; + mboxes = <&raid_mbox 28 0x1 0xff00>, + <&raid_mbox 29 0x1 0xff00>, + <&raid_mbox 30 0x1 0xff00>, + <&raid_mbox 31 0x1 0xff00>; }; From fcaa61afdfcf3a5ee9a684ac8310b40b13c670b0 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:47 -0600 Subject: [PATCH 589/757] arm64: dts: broadcom: Use preferred node names Update various node names to use the documented preferred names. Node names/path aren't considered ABI, so changing them should be safe. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-8-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts | 4 ++-- arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 8 ++++---- arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi | 2 +- .../boot/dts/broadcom/stingray/stingray-pinctrl.dtsi | 2 +- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 6 +++--- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index f06472edd4a1..290759ee0078 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -111,7 +111,7 @@ &ssp1 { status = "okay"; - at25@0 { + eeprom@0 { compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <5000000>; @@ -151,7 +151,7 @@ }; &nand { - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-mode = "hw"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index 0e134a94e142..be0876648afd 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -74,7 +74,7 @@ }; &nand { - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-mode = "hw"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 9888a1fabd5c..0de9d6265701 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -657,7 +657,7 @@ reg = <0x66220000 0x28>; }; - sata_phy: sata_phy@663f0100 { + sata_phy: sata-phy@663f0100 { compatible = "brcm,iproc-ns2-sata-phy"; reg = <0x663f0100 0x1f00>, <0x663f004c 0x10>; @@ -701,7 +701,7 @@ }; }; - sdio0: sdhci@66420000 { + sdio0: mmc@66420000 { compatible = "brcm,sdhci-iproc-cygnus"; reg = <0x66420000 0x100>; interrupts = ; @@ -711,7 +711,7 @@ status = "disabled"; }; - sdio1: sdhci@66430000 { + sdio1: mmc@66430000 { compatible = "brcm,sdhci-iproc-cygnus"; reg = <0x66430000 0x100>; interrupts = ; @@ -721,7 +721,7 @@ status = "disabled"; }; - nand: nand@66460000 { + nand: nand-controller@66460000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x66460000 0x600>, <0x67015408 0x600>, diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi index 8fe7325cfbb2..18152b16cfed 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi @@ -88,7 +88,7 @@ &nand { status = "okay"; - nandcs@0 { + nand@0 { compatible = "brcm,nandcs"; reg = <0>; nand-ecc-mode = "hw"; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi index 46a827521921..b8da71463ad7 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi @@ -32,7 +32,7 @@ #include - pinconf: pinconf@140000 { + pinconf: pinctrl@140000 { compatible = "pinconf-single"; reg = <0x00140000 0x250>; pinctrl-single,register-width = <32>; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index f9f77b2639c5..05139bcb3184 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -691,7 +691,7 @@ status = "disabled"; }; - nand: nand@360000 { + nand: nand-controller@360000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x00360000 0x600>, <0x0050a408 0x600>, @@ -704,7 +704,7 @@ status = "disabled"; }; - sdio0: sdhci@3f1000 { + sdio0: mmc@3f1000 { compatible = "brcm,sdhci-iproc"; reg = <0x003f1000 0x100>; interrupts = ; @@ -714,7 +714,7 @@ status = "disabled"; }; - sdio1: sdhci@3f2000 { + sdio1: mmc@3f2000 { compatible = "brcm,sdhci-iproc"; reg = <0x003f2000 0x100>; interrupts = ; From b871ac873a82f0ca2b273e454e5e775f562ca021 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:48 -0600 Subject: [PATCH 590/757] arm64: dts: broadcom: ns2-svk: Use non-deprecated at25 properties The at25,* properties have been deprecated since 2012. This board wasn't upstream until 2014, so it should be safe to switch over to the "new" properties. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-9-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index 290759ee0078..de238a9b1845 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -115,9 +115,9 @@ compatible = "atmel,at25"; reg = <0>; spi-max-frequency = <5000000>; - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; + size = <0x8000>; + address-width = <16>; + pagesize = <64>; spi-cpha; spi-cpol; pl022,interface = <0>; From 407940f2578e9ab917eab0bf1f0c43200f48881a Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:49 -0600 Subject: [PATCH 591/757] arm64: dts: broadcom: northstar2: Rework clock nodes The nd2-clocks.dtsi is oddly included in the middle of a bus node and is only included in one place, so collapse it into ns2.dtsi. Move the fixed and fixed-factor clock nodes to the root as they are not part of the bus. Rename the node names to use preferred names. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-10-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- .../dts/broadcom/northstar2/ns2-clock.dtsi | 105 ------------------ .../boot/dts/broadcom/northstar2/ns2.dtsi | 73 +++++++++++- 2 files changed, 71 insertions(+), 107 deletions(-) delete mode 100644 arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi deleted file mode 100644 index 99009fdf10a4..000000000000 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-clock.dtsi +++ /dev/null @@ -1,105 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright (c) 2016 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - - osc: oscillator { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - }; - - lcpll_ddr: lcpll_ddr@6501d058 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ddr"; - reg = <0x6501d058 0x20>, - <0x6501c020 0x4>, - <0x6501d04c 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ddr", "pcie_sata_usb", - "ddr", "ddr_ch2_unused", - "ddr_ch3_unused", "ddr_ch4_unused", - "ddr_ch5_unused"; - }; - - lcpll_ports: lcpll_ports@6501d078 { - #clock-cells = <1>; - compatible = "brcm,ns2-lcpll-ports"; - reg = <0x6501d078 0x20>, - <0x6501c020 0x4>, - <0x6501d054 0x4>; - clocks = <&osc>; - clock-output-names = "lcpll_ports", "wan", "rgmii", - "ports_ch2_unused", - "ports_ch3_unused", - "ports_ch4_unused", - "ports_ch5_unused"; - }; - - genpll_scr: genpll_scr@6501d098 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-scr"; - reg = <0x6501d098 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_scr", "scr", "fs", - "audio_ref", "scr_ch3_unused", - "scr_ch4_unused", "scr_ch5_unused"; - }; - - iprocmed: iprocmed { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <2>; - clock-mult = <1>; - }; - - iprocslow: iprocslow { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; - clock-div = <4>; - clock-mult = <1>; - }; - - genpll_sw: genpll_sw@6501d0c4 { - #clock-cells = <1>; - compatible = "brcm,ns2-genpll-sw"; - reg = <0x6501d0c4 0x32>, - <0x6501c020 0x4>, - <0x6501d044 0x4>; - clocks = <&osc>; - clock-output-names = "genpll_sw", "rpe", "250", "nic", - "chimp", "port", "sdio"; - }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 0de9d6265701..c9bf77b3566e 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -113,6 +113,28 @@ <&A57_3>; }; + osc: clock-25000000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + }; + + iprocmed: iprocmed { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <2>; + clock-mult = <1>; + }; + + iprocslow: iprocslow { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&genpll_scr BCM_NS2_GENPLL_SCR_SCR_CLK>; + clock-div = <4>; + clock-mult = <1>; + }; + pcie0: pcie@20020000 { compatible = "brcm,iproc-pcie"; reg = <0 0x20020000 0 0x1000>; @@ -197,8 +219,6 @@ #size-cells = <1>; ranges = <0 0 0 0xffffffff>; - #include "ns2-clock.dtsi" - enet: ethernet@61000000 { compatible = "brcm,ns2-amac"; reg = <0x61000000 0x1000>, @@ -334,6 +354,55 @@ #iommu-cells = <1>; }; + lcpll_ddr: clock-controller@6501d058 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ddr"; + reg = <0x6501d058 0x20>, + <0x6501c020 0x4>, + <0x6501d04c 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ddr", "pcie_sata_usb", + "ddr", "ddr_ch2_unused", + "ddr_ch3_unused", "ddr_ch4_unused", + "ddr_ch5_unused"; + }; + + lcpll_ports: clock-controller@6501d078 { + #clock-cells = <1>; + compatible = "brcm,ns2-lcpll-ports"; + reg = <0x6501d078 0x20>, + <0x6501c020 0x4>, + <0x6501d054 0x4>; + clocks = <&osc>; + clock-output-names = "lcpll_ports", "wan", "rgmii", + "ports_ch2_unused", + "ports_ch3_unused", + "ports_ch4_unused", + "ports_ch5_unused"; + }; + + genpll_scr: clock-controller@6501d098 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-scr"; + reg = <0x6501d098 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_scr", "scr", "fs", + "audio_ref", "scr_ch3_unused", + "scr_ch4_unused", "scr_ch5_unused"; + }; + + genpll_sw: clock-controller@6501d0c4 { + #clock-cells = <1>; + compatible = "brcm,ns2-genpll-sw"; + reg = <0x6501d0c4 0x32>, + <0x6501c020 0x4>, + <0x6501d044 0x4>; + clocks = <&osc>; + clock-output-names = "genpll_sw", "rpe", "250", "nic", + "chimp", "port", "sdio"; + }; pinctrl: pinctrl@6501d130 { compatible = "brcm,ns2-pinmux"; reg = <0x6501d130 0x08>, From 9c316b5a097304cb65becf0201275fbb1f927e89 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:50 -0600 Subject: [PATCH 592/757] arm64: dts: broadcom: northstar2: Drop unused and undocumented "brcm,pcie-ob-oarr-size" properties The "brcm,pcie-ob-oarr-size" property is unused and undocumented, so drop them. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-11-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index c9bf77b3566e..a187c8e788dd 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -154,7 +154,6 @@ ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>; brcm,pcie-ob; - brcm,pcie-ob-oarr-size; brcm,pcie-ob-axi-offset = <0x00000000>; status = "disabled"; @@ -184,7 +183,6 @@ ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>; brcm,pcie-ob; - brcm,pcie-ob-oarr-size; brcm,pcie-ob-axi-offset = <0x30000000>; status = "disabled"; From 172711e80a70d2ee267958062428c471ed7e77f2 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:51 -0600 Subject: [PATCH 593/757] arm64: dts: broadcom: northstar2: Drop QSPI "clock-names" The "clock-names" property is not documented for the "brcm,spi-bcm-qspi" binding nor in use by the kernel driver, so drop it. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-12-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index a187c8e788dd..85d997ab57a1 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -813,7 +813,6 @@ interrupts = ; interrupt-names = "spi_l1_intr"; clocks = <&iprocmed>; - clock-names = "iprocmed"; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; From 9a19a2c7b2b065d2060a9d95c4cfcc4d4d31b925 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 6 Jan 2026 20:09:52 -0600 Subject: [PATCH 594/757] arm64: dts: broadcom: northstar2: Drop "arm,cci-400-pmu" fallback compatible The "arm,cci-400-pmu" compatible is not documented as a valid fallback nor is it used, so drop it. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260106-dt-dtbs-broadcom-fixes-v1-13-ba45874e4553@kernel.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 85d997ab57a1..f0374b90f6aa 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -505,8 +505,7 @@ ranges = <0 0x65590000 0x10000>; pmu@9000 { - compatible = "arm,cci-400-pmu,r1", - "arm,cci-400-pmu"; + compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x4000>; interrupts = , , From a95e1d848972dd7d5cbabd62921b9b85501d891e Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 8 Jan 2026 17:15:58 -0600 Subject: [PATCH 595/757] arm64: dts: broadcom: bcm4906-netgear-r8000p: Drop unnecessary "ranges" in partition node "ranges" is only valid for MMIO addresses as it is used for translating addresses to CPU address. Even if a partial translation was supported, the DT is incorrect here as the nvmem-layout node would also need "ranges". So drop "ranges" and the associated cell size properties. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260108231558.1422454-2-robh@kernel.org Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts index a5f9ec92bd5e..c6d76ba04903 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts @@ -146,9 +146,6 @@ partition@0 { label = "cferom"; reg = <0x0 0x100000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x100000>; nvmem-layout { compatible = "fixed-layout"; From fbde94c13bea40d3b7ac6416b93e4c00bb9b1880 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 5 Nov 2025 20:53:42 +0100 Subject: [PATCH 596/757] arm64: tegra: Add DBB clock to EMC on Tegra264 The DBB clock is used by the EMC to enable the data path from various IP blocks to external memory. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index f137565da804..732b86db301a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3428,8 +3428,9 @@ reg = <0x00 0x8800000 0x0 0x20000>, <0x00 0x8890000 0x0 0x20000>; interrupts = ; - clocks = <&bpmp TEGRA264_CLK_EMC>; - clock-names = "emc"; + clocks = <&bpmp TEGRA264_CLK_EMC>, + <&bpmp TEGRA264_CLK_DBB_UPHY0>; + clock-names = "emc", "dbb"; #interconnect-cells = <0>; nvidia,bpmp = <&bpmp>; From fe57d0ac48350be4b5c069c37665279e6c35d7b7 Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Tue, 13 Jan 2026 05:49:35 +0000 Subject: [PATCH 597/757] arm64: tegra: Add nodes for CMDQV The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Update SMMU compatible strings to use nvidia,tegra264-smmu to enable CMDQV support. Add device tree nodes for the CMDQV hardware and enable them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU instance is paired with its corresponding CMDQV instance via the nvidia,cmdqv property. Acked-by: Nicolin Chen Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 8 +++ arch/arm64/boot/dts/nvidia/tegra264.dtsi | 50 +++++++++++++++++-- 2 files changed, 53 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi index 06795c82427a..7e2c3e66c2ab 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -23,8 +23,16 @@ status = "okay"; }; + cmdqv@5200000 { + status = "okay"; + }; + iommu@6000000 { status = "okay"; }; + + cmdqv@6200000 { + status = "okay"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 732b86db301a..b8068ee52b32 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3361,7 +3361,7 @@ <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */ smmu1: iommu@5000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x5000000 0x0 0x200000>; interrupts = , ; @@ -3370,10 +3370,18 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv1>; + }; + + cmdqv1: cmdqv@5200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x5200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; smmu2: iommu@6000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x6000000 0x0 0x200000>; interrupts = , ; @@ -3382,6 +3390,14 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv2>; + }; + + cmdqv2: cmdqv@6200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x6200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; mc: memory-controller@8020000 { @@ -3438,7 +3454,7 @@ }; smmu0: iommu@a000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0xa000000 0x0 0x200000>; interrupts = , ; @@ -3447,10 +3463,18 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv0>; + }; + + cmdqv0: cmdqv@a200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0xa200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; smmu4: iommu@b000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0xb000000 0x0 0x200000>; interrupts = , ; @@ -3459,6 +3483,14 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv4>; + }; + + cmdqv4: cmdqv@b200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0xb200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; i2c14: i2c@c410000 { @@ -3691,7 +3723,7 @@ ranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>; smmu3: iommu@6000000 { - compatible = "arm,smmu-v3"; + compatible = "nvidia,tegra264-smmu", "arm,smmu-v3"; reg = <0x00 0x6000000 0x0 0x200000>; interrupts = , ; @@ -3700,6 +3732,14 @@ #iommu-cells = <1>; dma-coherent; + nvidia,cmdqv = <&cmdqv3>; + }; + + cmdqv3: cmdqv@6200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x00 0x6200000 0x0 0x830000>; + interrupts = ; + status = "disabled"; }; hda@90b0000 { From 6e71a4b88752a6dbab17d410bb10880fba2c890a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Jan 2026 19:48:41 +0100 Subject: [PATCH 598/757] arm64: tegra: Drop unneeded status=okay on Tegra186 Device nodes are enabled by default and this DTSI file does not include anything else, thus it is impossible that nodes were disabled before and need to be re-enabled. Adding redundant status=okay is just confusing and suggests some other code flow. Verified with dtx_diff. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index b00630451909..705af0373a09 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -120,7 +120,6 @@ iommus = <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; dma-channel-mask = <0xfffffffe>; - status = "okay"; }; aconnect@2900000 { @@ -608,7 +607,6 @@ , , ; - status = "okay"; }; uarta: serial@3100000 { From 9ff1e819b0a6056de68cd96760d21b0c68e1b7d3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Jan 2026 19:48:42 +0100 Subject: [PATCH 599/757] arm64: tegra: Drop unneeded status=okay on Tegra194 Device nodes are enabled by default and this DTSI file does not include anything else, thus it is impossible that nodes were disabled before and need to be re-enabled. Adding redundant status=okay is just confusing and suggests some other code flow. Verified with dtx_diff. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index b782f8db1288..849694f751d9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -97,7 +97,6 @@ ; nvidia,axi2apb = <&axi2apb>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; axi2apb: axi2apb@2390000 { @@ -108,13 +107,11 @@ <0x0 0x23c0000 0x0 0x1000>, <0x0 0x23d0000 0x0 0x1000>, <0x0 0x23e0000 0x0 0x1000>; - status = "okay"; }; pinmux: pinmux@2430000 { compatible = "nvidia,tegra194-pinmux"; reg = <0x0 0x2430000 0x0 0x17000>; - status = "okay"; pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { clkreq { @@ -208,7 +205,6 @@ iommus = <&smmu TEGRA194_SID_GPCDMA_0>; dma-coherent; dma-channel-mask = <0xfffffffe>; - status = "okay"; }; aconnect@2900000 { @@ -737,7 +733,6 @@ , , ; - status = "okay"; }; uarta: serial@3100000 { @@ -1359,7 +1354,6 @@ nvidia,int-threshold = <1>; nvidia,slices = <11>; #timestamp-cells = <1>; - status = "okay"; }; hsp_top0: hsp@3c00000 { @@ -1547,7 +1541,6 @@ ; nvidia,axi2apb = <&axi2apb>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; rce-noc@be00000 { @@ -1557,7 +1550,6 @@ ; nvidia,axi2apb = <&axi2apb>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; hsp_aon: hsp@c150000 { @@ -1582,7 +1574,6 @@ nvidia,int-threshold = <1>; nvidia,slices = <3>; #timestamp-cells = <1>; - status = "okay"; }; gen2_i2c: i2c@c240000 { @@ -1668,8 +1659,6 @@ pinmux_aon: pinmux@c300000 { compatible = "nvidia,tegra194-pinmux-aon"; reg = <0x0 0xc300000 0x0 0x4000>; - - status = "okay"; }; pwm4: pwm@c340000 { @@ -1722,7 +1711,6 @@ interrupts = , ; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; bpmp-noc@d600000 { @@ -1732,7 +1720,6 @@ ; nvidia,axi2apb = <&axi2apb>; nvidia,apbmisc = <&apbmisc>; - status = "okay"; }; iommu@10000000 { @@ -1886,7 +1873,6 @@ #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "okay"; }; host1x@13e00000 { @@ -3106,7 +3092,6 @@ psci { compatible = "arm,psci-1.0"; - status = "okay"; method = "smc"; }; From 8f9c967e8eb0d6f7053fa9b68f7dc51cee118872 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Jan 2026 19:48:43 +0100 Subject: [PATCH 600/757] arm64: tegra: Drop unneeded status=okay on Tegra234 Device nodes are enabled by default and this DTSI file does not include anything else, thus it is impossible that nodes were disabled before and need to be re-enabled. Adding redundant status=okay is just confusing and suggests some other code flow. Verified with dtx_diff. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 827dbb420826..850c473235e3 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -40,7 +40,6 @@ compatible = "nvidia,tegra234-misc"; reg = <0x0 0x00100000 0x0 0xf000>, <0x0 0x0010f000 0x0 0x1000>; - status = "okay"; }; timer@2080000 { @@ -62,7 +61,6 @@ , , ; - status = "okay"; }; gpio: gpio@2200000 { @@ -2780,7 +2778,6 @@ "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = ; #interconnect-cells = <1>; - status = "okay"; #address-cells = <2>; #size-cells = <2>; @@ -2812,7 +2809,6 @@ interrupts = ; clocks = <&bpmp TEGRA234_CLK_EMC>; clock-names = "emc"; - status = "okay"; #interconnect-cells = <0>; @@ -3888,7 +3884,6 @@ #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "okay"; }; sce-fabric@b600000 { @@ -3902,7 +3897,6 @@ compatible = "nvidia,tegra234-rce-fabric"; reg = <0x0 0xbe00000 0x0 0x40000>; interrupts = ; - status = "okay"; }; hsp_aon: hsp@c150000 { @@ -4064,28 +4058,24 @@ compatible = "nvidia,tegra234-aon-fabric"; reg = <0x0 0xc600000 0x0 0x40000>; interrupts = ; - status = "okay"; }; bpmp-fabric@d600000 { compatible = "nvidia,tegra234-bpmp-fabric"; reg = <0x0 0xd600000 0x0 0x40000>; interrupts = ; - status = "okay"; }; dce-fabric@de00000 { compatible = "nvidia,tegra234-dce-fabric"; reg = <0x0 0xde00000 0x0 0x40000>; interrupts = ; - status = "okay"; }; ccplex@e000000 { compatible = "nvidia,tegra234-ccplex-cluster"; reg = <0x0 0x0e000000 0x0 0x5ffff>; nvidia,bpmp = <&bpmp>; - status = "okay"; }; gic: interrupt-controller@f400000 { @@ -4239,7 +4229,6 @@ #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "okay"; }; smmu_niso0: iommu@12000000 { @@ -4381,14 +4370,12 @@ #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "okay"; }; cbb-fabric@13a00000 { compatible = "nvidia,tegra234-cbb-fabric"; reg = <0x0 0x13a00000 0x0 0x400000>; interrupts = ; - status = "okay"; }; host1x@13e00000 { @@ -5804,12 +5791,10 @@ pmu { compatible = "arm,cortex-a78-pmu"; interrupts = ; - status = "okay"; }; psci { compatible = "arm,psci-1.0"; - status = "okay"; method = "smc"; }; From 42cbac7dc900aca83878c1c35a1b60725ba327dc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Jan 2026 19:48:44 +0100 Subject: [PATCH 601/757] arm64: tegra: Drop unneeded status=okay on Tegra264 Device nodes are enabled by default and this DTSI file does not include anything else, thus it is impossible that nodes were disabled before and need to be re-enabled. Adding redundant status=okay is just confusing and suggests some other code flow. Verified with dtx_diff. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index b8068ee52b32..ef37b2a39cdb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3777,7 +3777,6 @@ compatible = "arm,armv8"; device_type = "cpu"; reg = <0x00000>; - status = "okay"; enable-method = "psci"; @@ -3793,7 +3792,6 @@ compatible = "arm,armv8"; device_type = "cpu"; reg = <0x10000>; - status = "okay"; enable-method = "psci"; @@ -3831,12 +3829,10 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; - status = "okay"; }; psci { compatible = "arm,psci-1.0"; - status = "okay"; method = "smc"; }; @@ -3863,6 +3859,5 @@ , , ; - status = "okay"; }; }; From 7263d6a8b8743e6022f44d9dc367213c7695a8f2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 15 Jan 2026 19:48:45 +0100 Subject: [PATCH 602/757] arm64: tegra: Correct CPU compatibles on Tegra264 "arm,armv8" CPU compatible is only for software models and must not be used in DTS for actual hardware. Replace them with Neoverse V3AE compatible, based what is written on Wikipedia [1]. Link: https://en.wikipedia.org/wiki/Tegra#Thor [1] Reported-by: Konrad Dybcio Closes: https://lore.kernel.org/all/59ae6b16-7866-413a-a1d2-4a735024c108@oss.qualcomm.com/ Signed-off-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index ef37b2a39cdb..7644a41d5f72 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3774,7 +3774,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,armv8"; + compatible = "arm,neoverse-v3ae"; device_type = "cpu"; reg = <0x00000>; @@ -3789,7 +3789,7 @@ }; cpu1: cpu@1 { - compatible = "arm,armv8"; + compatible = "arm,neoverse-v3ae"; device_type = "cpu"; reg = <0x10000>; From 8acdb94dcfd37ad974abbf3209ed49821e8a5686 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Fri, 26 Dec 2025 12:17:32 +0000 Subject: [PATCH 603/757] arm64: tegra: smaug: Enable DisplayPort via USB-C port Enable both SOR and DPAUX modules allowing the USB-C port to transmit video in DP altmode. Tested on several monitors with USB-C to HDMI adapter. Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 5aa6afd56cbc..e9e925cc5774 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -31,6 +31,11 @@ }; host1x@50000000 { + dpaux1: dpaux@54040000 { + vdd-supply = <&pp3300>; + status = "okay"; + }; + dsia: dsi@54300000 { avdd-dsi-csi-supply = <&vdd_dsi_csi>; status = "okay"; @@ -58,6 +63,13 @@ }; }; + sor1: sor@54580000 { + avdd-io-hdmi-dp-supply = <&pp1800>; + vdd-hdmi-dp-pll-supply = <&avddio_1v05>; + nvidia,dpaux = <&dpaux1>; + status = "okay"; + }; + dpaux: dpaux@545c0000 { status = "okay"; }; From c256740c4b1ff5f3e6cbad48d5d4081849672b76 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Thu, 4 Dec 2025 21:27:20 +0000 Subject: [PATCH 604/757] arm64: tegra: smaug: Complete and enable tegra-udc node Complete the missing properties in the tegra-udc node and enable it for Smaug. Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index e9e925cc5774..d2ed704a6d3b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1855,6 +1855,17 @@ status = "okay"; }; + usb@700d0000 { + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, + <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; + phy-names = "usb2-0", "usb3-0"; + + avddio-usb-supply = <&avddio_1v05>; + hvdd-usb-supply = <&pp3300>; + + status = "okay"; + }; + clock@70110000 { status = "okay"; nvidia,cf = <6>; From dfa93788dd8b2f9c59adf45ecf592082b1847b7b Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Thu, 4 Dec 2025 21:27:21 +0000 Subject: [PATCH 605/757] arm64: tegra: smaug: Add usb-role-switch support The USB2 port on Smaug is configured for OTG operation but lacked the required 'usb-role-switch' property, leading to a failed probe and a non-functioning USB port. Add the property along with setting the default role to host. Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index d2ed704a6d3b..b88428aa831e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1821,6 +1821,8 @@ status = "okay"; vbus-supply = <&usbc_vbus>; mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; }; usb3-0 { From 4d93678236678c4b6b0076fd11f4611a22b7e70b Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 4 Dec 2025 08:17:03 +0200 Subject: [PATCH 606/757] ARM: tegra: Adjust DSI nodes for Tegra20/Tegra30 Add missing nvidia,mipi-calibrate and cells properties to DSI nodes. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding --- arch/arm/boot/dts/nvidia/tegra20.dtsi | 4 ++++ arch/arm/boot/dts/nvidia/tegra30.dtsi | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi index c60fc1971188..e4be3b62a51f 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -230,7 +230,11 @@ reset-names = "dsi"; power-domains = <&pd_core>; operating-points-v2 = <&dsi_dvfs_opp_table>; + nvidia,mipi-calibrate = <&csi 3>; /* DSI pad */ status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi index 4c4e6097c916..ed1bbf86434c 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -343,7 +343,11 @@ reset-names = "dsi"; power-domains = <&pd_core>; operating-points-v2 = <&dsia_dvfs_opp_table>; + nvidia,mipi-calibrate = <&csi 3>; /* DSIA pad */ status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; dsi@54400000 { @@ -356,7 +360,11 @@ reset-names = "dsi"; power-domains = <&pd_core>; operating-points-v2 = <&dsib_dvfs_opp_table>; + nvidia,mipi-calibrate = <&csi 4>; /* DSIB pad */ status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; }; }; From d6e8b796d0d67699c74ee3cbc46601cf9ec925bb Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 22 Oct 2025 17:20:38 +0300 Subject: [PATCH 607/757] dt-bindings: display: tegra: document Tegra132 MIPI calibration device Document MIPI calibration device found in Tegra132. This compatible already exists in the Linux kernel, I have just documented it to satisfy warnings. Each Tegra SoC generation has unique set of registers which should be configured. They all differ, hence fallback is not suitable here. Signed-off-by: Svyatoslav Ryhel Acked-by: Conor Dooley Tested-by: Luca Ceresoli # tegra20, parallel camera Signed-off-by: Thierry Reding --- .../devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml index 193ddb105283..9a500f52f01d 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml @@ -18,6 +18,7 @@ properties: enum: - nvidia,tegra114-mipi - nvidia,tegra124-mipi + - nvidia,tegra132-mipi - nvidia,tegra210-mipi - nvidia,tegra186-mipi From d262d030baef287da33344a932639aab5f913c3a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 22 Oct 2025 17:20:32 +0300 Subject: [PATCH 608/757] dt-bindings: display: tegra: document Tegra30 VI and VIP Existing Parallel VI interface schema for Tegra20 is fully compatible with Tegra30; hence, lets reuse it by setting fallback for Tegra30. Adjust existing VI schema to reflect that Tegra20 VI is compatible with Tegra30 by setting a fallback for Tegra30. Additionally, switch to using an enum instead of list of const. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Rob Herring (Arm) Tested-by: Luca Ceresoli # tegra20, parallel camera Signed-off-by: Thierry Reding --- .../display/tegra/nvidia,tegra20-vi.yaml | 19 ++++++++++++------- .../display/tegra/nvidia,tegra20-vip.yaml | 9 +++++++-- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml index 644f42b942ad..bb138277d5e8 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -16,16 +16,21 @@ properties: compatible: oneOf: - - const: nvidia,tegra20-vi - - const: nvidia,tegra30-vi - - const: nvidia,tegra114-vi - - const: nvidia,tegra124-vi + - enum: + - nvidia,tegra20-vi + - nvidia,tegra114-vi + - nvidia,tegra124-vi + - nvidia,tegra210-vi + - nvidia,tegra186-vi + - nvidia,tegra194-vi + + - items: + - const: nvidia,tegra30-vi + - const: nvidia,tegra20-vi + - items: - const: nvidia,tegra132-vi - const: nvidia,tegra124-vi - - const: nvidia,tegra210-vi - - const: nvidia,tegra186-vi - - const: nvidia,tegra194-vi reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml index 14294edb8d8c..9104a36e16d9 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml @@ -11,8 +11,13 @@ maintainers: properties: compatible: - enum: - - nvidia,tegra20-vip + oneOf: + - enum: + - nvidia,tegra20-vip + + - items: + - const: nvidia,tegra30-vip + - const: nvidia,tegra20-vip ports: $ref: /schemas/graph.yaml#/properties/ports From f0ed0e84445245e56aa73c4df8d99936a2ce8549 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 20 Oct 2025 15:00:42 -0400 Subject: [PATCH 609/757] arm64: dts: imx91: Add thermal-sensor and thermal-zone support Add thermal-sensor and thermal-zone support. Signed-off-by: Frank Li Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx91.dtsi | 58 ++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx91.dtsi b/arch/arm64/boot/dts/freescale/imx91.dtsi index 4d8300b2a7bc..f075592bfc01 100644 --- a/arch/arm64/boot/dts/freescale/imx91.dtsi +++ b/arch/arm64/boot/dts/freescale/imx91.dtsi @@ -6,6 +6,54 @@ #include "imx91-pinfunc.h" #include "imx91_93_common.dtsi" +/{ + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&aips1 { + tmu: thermal-sensor@44482000 { + compatible = "fsl,imx91-tmu"; + reg = <0x44482000 0x1000>; + #thermal-sensor-cells = <0>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + interrupt-parent = <&gic>; + interrupts = , + , + ; + interrupt-names = "thr1", "thr2", "ready"; + nvmem-cells = <&tmu_trim1>, <&tmu_trim2>; + nvmem-cell-names = "trim1", "trim2"; + }; +}; + &clk { compatible = "fsl,imx91-ccm"; }; @@ -69,3 +117,13 @@ clock-names = "apb", "axi", "nic", "disp", "cam", "lcdif", "isi", "csi"; }; + +&ocotp { + tmu_trim1: tmu-trim@a0 { + reg = <0xa0 0x4>; + }; + + tmu_trim2: tmu-trim@a4 { + reg = <0xa4 0x4>; + }; +}; From 54397e9844a4d1231a2aa2a6042b9fab279772b7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 4 Nov 2025 17:27:12 -0500 Subject: [PATCH 610/757] ARM: dts: imx6qdl: add '#address-cells' and '#size-cells' for gpmi-nand Add '#address-cells' and '#size-cells' for gpmi-nand to below CHECK_DTBS warings: arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dtb: nand-controller@112000 (fsl,imx6q-gpmi-nand): '#address-cells' is a required property from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml# Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index 9793feee6394..76e6043e1f91 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -166,6 +166,8 @@ compatible = "fsl,imx6q-gpmi-nand"; reg = <0x00112000 0x2000>, <0x00114000 0x2000>; reg-names = "gpmi-nand", "bch"; + #address-cells = <1>; + #size-cells = <0>; interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "bch"; clocks = <&clks IMX6QDL_CLK_GPMI_IO>, From af6c4ea19df9a6612c15f7647d47397e4314d4e7 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 4 Nov 2025 17:27:13 -0500 Subject: [PATCH 611/757] ARM: dts: imx6sx: update gpmi #size-cells to 0 Update gpmi #size-cells to 0 to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dtb: nand-controller@1806000 (fsl,imx6sx-gpmi-nand): #size-cells: 0 was expected from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml# Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 5132b575b001..1426f357d474 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -224,7 +224,7 @@ gpmi: nand-controller@1806000 { compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x01806000 0x2000>, <0x01808000 0x4000>; reg-names = "gpmi-nand", "bch"; interrupts = ; From 8124b4a4a96b57d6cc3705a9df9623c52baa047b Mon Sep 17 00:00:00 2001 From: Frank Li Date: Tue, 4 Nov 2025 17:27:14 -0500 Subject: [PATCH 612/757] ARM: dts: imx: move nand related property under nand@0 Add child node nand@0 and move NAND related property under it to align modern nand-controller.yaml. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6ull-colibri-aster.dtb: nand-controller@1806000 (fsl,imx6q-gpmi-nand): Unevaluated properties are not allowed ('nand-ecc-mode', 'nand-ecc-step-size', 'nand-ecc-strength', 'nand-on-flash-bbt' were unexpected) from schema $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml# Since 2019 year, commit (212e496935929 dt-bindings: mtd: Add YAML schemas for the generic NAND options) NAND related property is preferred located under nand@ even though only one NAND chip supported. Signed-off-by: Frank Li Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi | 6 +++++- .../boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi | 6 +++++- .../boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi | 12 ++++++++---- .../boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi | 12 ++++++++---- arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi | 6 +++++- arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts | 6 +++++- arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi | 8 ++++++-- 15 files changed, 82 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi index 547fb141ec0c..f452764fae00 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6-logicpd-som.dtsi @@ -36,8 +36,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi index 9975b6ee433d..58ecdb87c6d4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-icore.dtsi @@ -172,8 +172,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi index aa9a442852f4..6f3becd33a5b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi @@ -102,8 +102,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi index 85e278eb2016..f2140dd8525f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi @@ -73,8 +73,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "disabled"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi index c93dbc595ef6..131a3428ddb8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-skov-cpu.dtsi @@ -260,10 +260,14 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; #address-cells = <1>; #size-cells = <0>; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi index 57297d6521cf..d29adfef5fdb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -252,9 +252,13 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; fsl,no-blockmark-swap; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts index 2a6bb5ff808a..40d530c1dc29 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts @@ -133,8 +133,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi index e34c8cbe36ae..776f6f78ee46 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-isiot.dtsi @@ -101,8 +101,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "disabled"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi index a3ea1b208462..27e4d2aec137 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-phytec-phycore-som.dtsi @@ -63,8 +63,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "disabled"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index 1992dfb53b45..dc53f9286ffe 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -296,9 +296,13 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; fsl,no-blockmark-swap; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &i2c2 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi index ec3c1e7301f4..eaed2cbf0c82 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi @@ -160,11 +160,15 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; fsl,use-minimum-ecc; - nand-on-flash-bbt; - nand-ecc-mode = "hw"; - nand-ecc-strength = <8>; - nand-ecc-step-size = <512>; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + }; }; /* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi index 43518bf07602..3dfd43b32055 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea.dtsi @@ -43,11 +43,15 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-ecc-mode = "hw"; - nand-ecc-strength = <0>; - nand-ecc-step-size = <0>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <0>; + nand-ecc-step-size = <0>; + nand-on-flash-bbt; + }; }; &iomuxc { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi index 83b9de17cee2..fc298f57bfff 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-myir-mys-6ulx.dtsi @@ -60,8 +60,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "disabled"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &uart1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts index 2d9f495660c9..8ec18eae98a4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ulz-bsh-smm-m2.dts @@ -25,8 +25,12 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + }; }; &snvs_poweroff { diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi index 8666dcd7fe97..a41dc4edfc0d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi @@ -375,10 +375,14 @@ /* NAND on such SKUs */ &gpmi { fsl,use-minimum-ecc; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + + nand@0 { + reg = <0>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + }; }; /* On-module Power I2C */ From fc61fdfdc4dd03fa5cea784e1969ed3df049c6c8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 Nov 2025 15:31:30 +0100 Subject: [PATCH 613/757] arm64: dts: imx95: Use GPU_CGC as core clock for GPU The i.MX95 imx-sm introduced new GPU_CGC clock since imx-sm commit ca5e078833fa ("SM-128: Add clock management via CCM LPCG direct control") which are downstream clock of GPU clock. These new GPU_CGC clock gate the existing GPU clock. Currently, without clk_ignore_unused on kernel command line, those new GPU_CGC clock are unused and the kernel will disable them. This has no impact on i.MX95 A0/A1, but does prevent GPU register access from working at all on i.MX95 B0. The GPU_CGC clock are present on both i.MX95 A0/A1/B0, therefore update the DT such, that the GPU core clock are the GPU_CGC clock. When the panthor driver enables the GPU core clock, it enables both the GPU_CGC as well as its parent GPU clock. Fixes: 67934f248e64 ("arm64: dts: imx95: Describe Mali G310 GPU") Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx95-clock.h | 1 + arch/arm64/boot/dts/freescale/imx95.dtsi | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx95-clock.h b/arch/arm64/boot/dts/freescale/imx95-clock.h index e1f91203e794..22311612e440 100644 --- a/arch/arm64/boot/dts/freescale/imx95-clock.h +++ b/arch/arm64/boot/dts/freescale/imx95-clock.h @@ -183,5 +183,6 @@ #define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + 7) #define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8) #define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9) +#define IMX95_CLK_GPU_CGC (IMX95_CCM_NUM_CLK_SRC + 123 + 10) #endif /* __CLOCK_IMX95_H */ diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi index e45014d50abe..93d53c3f9eab 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -2164,7 +2164,7 @@ gpu: gpu@4d900000 { compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; reg = <0 0x4d900000 0 0x480000>; - clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>; + clocks = <&scmi_clk IMX95_CLK_GPU_CGC>, <&scmi_clk IMX95_CLK_GPUAPB>; clock-names = "core", "coregroup"; interrupts = , , From 6f55fc60dc2c465b536cd69b71b82266d0da52c9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Jan 2026 20:00:37 +0100 Subject: [PATCH 614/757] dt-bindings: vendor-prefixes: Document ifm electronic gmbh ifm is a manufacturer of industrial sensors, control technology and automation solutions. Document their vendor prefix, which is already used for ifm,ac14xx and other powerpc devices. Acked-by: Rob Herring (Arm) Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a..c06d640bfcb0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -755,6 +755,8 @@ patternProperties: description: IEI Integration Corp. "^ifi,.*": description: Ingenieurburo Fur Ic-Technologie (I/F/I) + "^ifm,.*": + description: ifm electronic gmbh "^ilitek,.*": description: ILI Technology Corporation (ILITEK) "^imagis,.*": From a642165719daa8a1b5aef86dcf6d6454082ac1d1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Jan 2026 20:00:38 +0100 Subject: [PATCH 615/757] dt-bindings: arm: fsl: Document ifm VHIP4 EvalBoard v1 and v2 Document ifm i.MX8MN VHIP4 EvalBoard v1 and v2 reference design binding. This system exists in two generations, v1 and v2, which share a lot of commonality. The boards come with either single gigabit ethernet or an KSZ8794 fast-ethernet switch, boot from eMMC, and offer CAN interfaces via Microchip MCP25xx SPI CAN controllers, UART, and USB host. The GPU is not available in the SoC populated on these devices. Acked-by: Rob Herring (Arm) Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 433f555232e9..b45047c15ef1 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1071,6 +1071,15 @@ properties: - gw,imx8mn-gw7902 # i.MX8MM Gateworks Board - const: fsl,imx8mn + - description: ifm i.MX8MN VHIP4 based boards + items: + - enum: + - ifm,imx8mn-vhip4-evalboard-v1 + - ifm,imx8mn-vhip4-evalboard-v2 + - const: ifm,imx8mn-vhip4-evalboard + - const: ifm,imx8mn-vhip4 + - const: fsl,imx8mn + - description: Variscite VAR-SOM-MX8MN based boards items: - enum: From 3a2741fa31385348c5b501bdcbab6f6d7b4628ac Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 13 Jan 2026 10:58:58 +0000 Subject: [PATCH 616/757] dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ensure children of cmu_top have alphanumeric ordering. Top is special as it feeds all the other children CMUs. This ordering then matches the clk-gs101.c file. Reviewed-by: André Draszik Signed-off-by: Peter Griffin Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260113-dpu-clocks-v3-1-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/google,gs101-clock.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 31e106ef913d..82639863b1a4 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -29,9 +29,9 @@ properties: enum: - google,gs101-cmu-top - google,gs101-cmu-apm - - google,gs101-cmu-misc - google,gs101-cmu-hsi0 - google,gs101-cmu-hsi2 + - google,gs101-cmu-misc - google,gs101-cmu-peric0 - google,gs101-cmu-peric1 From 52300cd894b3167d6206e266e341a089e87124b9 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 13 Jan 2026 10:58:59 +0000 Subject: [PATCH 617/757] dt-bindings: clock: google,gs101-clock: Add DPU clock management unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add dt schema documentation and clock IDs for the Display Process Unit (DPU) clock management unit (CMU). This CMU feeds IPs such as image scaler, enhancer and compressor. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring (Arm) Reviewed-by: André Draszik Link: https://patch.msgid.link/20260113-dpu-clocks-v3-2-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/clock/google,gs101-clock.yaml | 19 ++++++++++ include/dt-bindings/clock/google,gs101.h | 36 +++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml index 82639863b1a4..6193c87511fa 100644 --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml @@ -29,6 +29,7 @@ properties: enum: - google,gs101-cmu-top - google,gs101-cmu-apm + - google,gs101-cmu-dpu - google,gs101-cmu-hsi0 - google,gs101-cmu-hsi2 - google,gs101-cmu-misc @@ -77,6 +78,24 @@ allOf: items: - const: oscclk + - if: + properties: + compatible: + contains: + const: google,gs101-cmu-dpu + + then: + properties: + clocks: + items: + - description: External reference clock (24.576 MHz) + - description: DPU bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - if: properties: compatible: diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h index 442f9e9037dc..7a14dcb9f17b 100644 --- a/include/dt-bindings/clock/google,gs101.h +++ b/include/dt-bindings/clock/google,gs101.h @@ -313,6 +313,42 @@ #define CLK_APM_PLL_DIV4_APM 70 #define CLK_APM_PLL_DIV16_APM 71 +/* CMU_DPU */ +#define CLK_MOUT_DPU_BUS_USER 1 +#define CLK_DOUT_DPU_BUSP 2 +#define CLK_GOUT_DPU_PCLK 3 +#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK 4 +#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM 5 +#define CLK_GOUT_DPU_DPUF_ACLK_DMA 6 +#define CLK_GOUT_DPU_DPUF_ACLK_DPP 7 +#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK 8 +#define CLK_GOUT_DPU_GPC_DPU_PCLK 9 +#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK 10 +#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK 11 +#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK 12 +#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK 13 +#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK 14 +#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK 15 +#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK 16 +#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK 17 +#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK 18 +#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK 19 +#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK 20 +#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK 21 +#define CLK_GOUT_DPU_SSMT_DPU0_ACLK 22 +#define CLK_GOUT_DPU_SSMT_DPU0_PCLK 23 +#define CLK_GOUT_DPU_SSMT_DPU1_ACLK 24 +#define CLK_GOUT_DPU_SSMT_DPU1_PCLK 25 +#define CLK_GOUT_DPU_SSMT_DPU2_ACLK 26 +#define CLK_GOUT_DPU_SSMT_DPU2_PCLK 27 +#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1 28 +#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2 29 +#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1 30 +#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2 31 +#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1 32 +#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2 33 +#define CLK_GOUT_DPU_SYSREG_DPU_PCLK 34 + /* CMU_HSI0 */ #define CLK_FOUT_USB_PLL 1 #define CLK_MOUT_PLL_USB 2 From 024d8f4aa35970c4563c6ef0c4170133719b2103 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Tue, 13 Jan 2026 10:59:02 +0000 Subject: [PATCH 618/757] arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the cmu_dpu clock management unit. It feeds some of the display IPs. Additionally add the sysreg_dpu node which contains the BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable dynamic root clock gating of bus components. Reviewed-by: André Draszik Signed-off-by: Peter Griffin Link: https://patch.msgid.link/20260113-dpu-clocks-v3-5-cb85424f2c72@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi index 48f3819590cf..d085f9fb0f62 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1815,6 +1815,23 @@ status = "disabled"; }; + cmu_dpu: clock-controller@1c000000 { + compatible = "google,gs101-cmu-dpu"; + reg = <0x1c000000 0x10000>; + #clock-cells = <1>; + + clocks = <&ext_24_5m>, + <&cmu_top CLK_DOUT_CMU_DPU_BUS>; + clock-names = "oscclk", "bus"; + samsung,sysreg = <&sysreg_dpu>; + }; + + sysreg_dpu: syscon@1c020000 { + compatible = "google,gs101-dpu-sysreg", "syscon"; + reg = <0x1c020000 0x10000>; + clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>; + }; + cmu_top: clock-controller@1e080000 { compatible = "google,gs101-cmu-top"; reg = <0x1e080000 0x10000>; From fc12767c19d49663b13ba2def6e4674df041c8a2 Mon Sep 17 00:00:00 2001 From: Jingyi Wang Date: Fri, 31 Oct 2025 00:41:44 -0700 Subject: [PATCH 619/757] dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms Document the Inter-Processor Communication Controller on the Qualcomm Kaanapali and Glymur Platforms, which will be used to route interrupts across various subsystems found on the SoC. Co-developed-by: Sibi Sankar Signed-off-by: Sibi Sankar Signed-off-by: Jingyi Wang Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-1-62ffb4168dff@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index e5c423130db6..7c4d6170491d 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,8 @@ properties: compatible: items: - enum: + - qcom,glymur-ipcc + - qcom,kaanapali-ipcc - qcom,milos-ipcc - qcom,qcs8300-ipcc - qcom,qdu1000-ipcc From 6429d40e519fed71e2bd2afd59f9a379f9740a9b Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:38 +0100 Subject: [PATCH 620/757] arm64: dts: imx8mq-librem5: Enable I2C recovery i2c-imx can perform bus recovery by temporarily switching I2C pins into GPIO mode. To do so, it needs GPIO and pinctrl handles to be provided in the device tree. Suggested-by: Denis Sergeevich Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mq-librem5.dtsi | 48 +++++++++++++++++-- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 2975e9451661..2bd25ef7f304 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -512,6 +512,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x26 + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x26 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000026 @@ -519,6 +526,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x26 + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x26 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000026 @@ -526,6 +540,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x26 + MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x26 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000026 @@ -533,6 +554,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4-gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x26 + MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x26 + >; + }; + pinctrl_keys: keysgrp { fsl,pins = < /* VOL- */ @@ -782,8 +810,11 @@ &i2c1 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; typec_pd: usb-pd@3f { @@ -982,8 +1013,11 @@ &i2c2 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; magnetometer: magnetometer@1e { @@ -1031,8 +1065,11 @@ &i2c3 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; codec: audio-codec@1a { @@ -1121,8 +1158,11 @@ &i2c4 { clock-frequency = <384000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; vcm@c { From bb01a42b1bc2ee4483a784ac6e8597d16227a04f Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:39 +0100 Subject: [PATCH 621/757] arm64: dts: imx8mq-librem5: Set vibrator's PWM frequency to 20kHz 1Hz as used previously was way too long. Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 2bd25ef7f304..bc3e103b2d6a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -287,7 +287,7 @@ vibrator { compatible = "pwm-vibrator"; - pwms = <&pwm1 0 1000000000 0>; + pwms = <&pwm1 0 50000 0>; pwm-names = "enable"; vcc-supply = <®_vdd_3v3>; }; From 1361bfee8d7b791288e585a3467330a5f5b699ed Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:40 +0100 Subject: [PATCH 622/757] arm64: dts: imx8mq-librem5: Enable SNVS RTC It has been disabled because it was being used for system clock instead of the discrete RTC. However, SNVS has some features that the discrete RTC does not, such as being able to turn the device on. Solve that issue with aliases instead and reenable SNVS RTC. Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index bc3e103b2d6a..5e0bf127e7e5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -17,6 +17,11 @@ compatible = "purism,librem5", "fsl,imx8mq"; chassis-type = "handset"; + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + backlight_dsi: backlight-dsi { compatible = "led-backlight"; leds = <&led_backlight>; @@ -1001,7 +1006,7 @@ }; }; - rtc@68 { + rtc: rtc@68 { compatible = "microcrystal,rv4162"; reg = <0x68>; pinctrl-names = "default"; @@ -1316,10 +1321,6 @@ status = "okay"; }; -&snvs_rtc { - status = "disabled"; -}; - &uart1 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; From f9774d6d4ba45cb345b17001861e5ecdf0b4c659 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:41 +0100 Subject: [PATCH 623/757] arm64: dts: imx8mq-librem5: Limit uSDHC2 frequency to 50MHz SparkLAN card has stability issues at 100MHz. It still appears to be able to max out its throughput this way, so limit the frequency to ensure stable operation. Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 5e0bf127e7e5..5bc9654cd436 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1424,7 +1424,7 @@ &usdhc2 { assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; - assigned-clock-rates = <200000000>; + assigned-clock-rates = <50000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>; @@ -1434,7 +1434,7 @@ mmc-pwrseq = <&usdhc2_pwrseq>; post-power-on-delay-ms = <20>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - max-frequency = <100000000>; + max-frequency = <50000000>; disable-wp; cap-sdio-irq; keep-power-in-suspend; From f8d3da15a96975646eb17b270753fdf639c37a65 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:42 +0100 Subject: [PATCH 624/757] arm64: dts: imx8mq-librem5: Set cap-power-off-card for usdhc2 This is needed for brcmfmac to turn the card off in suspend since 8c3170628a9ce24a59647bd24f897e666af919b8. Signed-off-by: Sebastian Krzyszkowiak Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 5bc9654cd436..068799cbedb2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1437,6 +1437,7 @@ max-frequency = <50000000>; disable-wp; cap-sdio-irq; + cap-power-off-card; keep-power-in-suspend; wakeup-source; status = "okay"; From 507d920800ea52388d89756eb168482e18bf0681 Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Mon, 5 Jan 2026 21:39:43 +0100 Subject: [PATCH 625/757] arm64: dts: imx8mq-librem5: Don't set mic-cfg for wm8962 The default values are fine, and MICDET_ENA is handled by the driver on its own anyway. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 068799cbedb2..eee390c27210 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1085,7 +1085,6 @@ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; assigned-clock-rates = <24576000>; #sound-dai-cells = <0>; - mic-cfg = <0x200>; DCVDD-supply = <®_aud_1v8>; DBVDD-supply = <®_aud_1v8>; AVDD-supply = <®_aud_1v8>; From 347e8b20acfeb2861e28892062b6dc3d9f579981 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Jan 2026 20:00:39 +0100 Subject: [PATCH 626/757] arm64: dts: imx8mn: Add SNVS LPGPR Add SNVS LPGPR bindings to MX8M Nano, the LPGPR is used to store boot counter. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b98b3d0ddf25..3199bc0966b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -628,6 +628,11 @@ wakeup-source; status = "disabled"; }; + + snvs_lpgpr: snvs-lpgpr { + compatible = "fsl,imx8mn-snvs-lpgpr", + "fsl,imx7d-snvs-lpgpr"; + }; }; clk: clock-controller@30380000 { From 5eb7405db99b171494f9aa3d37e2985ae74ee37f Mon Sep 17 00:00:00 2001 From: Fedor Ross Date: Tue, 6 Jan 2026 20:00:40 +0100 Subject: [PATCH 627/757] arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2 Add support for ifm i.MX8MN VHIP4 EvalBoard v1 and v2 reference design. This system exists in two generations, v1 and v2, which share a lot of commonality. The boards come with either single gigabit ethernet or an KSZ8794 fast-ethernet switch, boot from eMMC, and offer CAN interfaces via Microchip MCP25xx SPI CAN controllers, UART, and USB host. The GPU is not available in the SoC populated on these devices. Signed-off-by: Fedor Ross Signed-off-by: Marek Vasut Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 19 + .../imx8mn-vhip4-evalboard-common.dtsi | 396 ++++++++++++++++++ ...imx8mn-vhip4-evalboard-ksz8794-common.dtsi | 98 +++++ ...mn-vhip4-evalboard-v1-overlay-ksz8794.dtso | 24 ++ ...mn-vhip4-evalboard-v1-overlay-ksz9031.dtso | 48 +++ .../freescale/imx8mn-vhip4-evalboard-v1.dts | 258 ++++++++++++ ...n-vhip4-evalboard-v2-overlay-adin1300.dtso | 60 +++ ...mn-vhip4-evalboard-v2-overlay-ksz8794.dtso | 24 ++ .../freescale/imx8mn-vhip4-evalboard-v2.dts | 221 ++++++++++ 9 files changed, 1148 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ce8f937c2315..83df038701de 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -193,6 +193,25 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb +imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo +imx8mn-vhip4-evalboard-v1-overlay-ksz9031-dtbs := imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtbo +imx8mn-vhip4-evalboard-v2-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo +imx8mn-vhip4-evalboard-v2-overlay-adin1300-dtbs := imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mn-vhip4-evalboard-v1.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtbo \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtb \ + imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtbo \ + imx8mn-vhip4-evalboard-v2.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtbo \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtb \ + imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtbo + imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo imx8mn-tqma8mqnl-mba8mx-usbotg-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-usbotg.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi new file mode 100644 index 000000000000..aaf9761703aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-common.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2024 Fedor Ross + */ + +#include "imx8mn.dtsi" +#include + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board"; + compatible = "ifm,imx8mn-vhip4-evalboard", "ifm,imx8mn-vhip4", "fsl,imx8mn"; + + aliases { + mmc0 = &usdhc3; + mmc1 = &usdhc1; + mmc2 = &usdhc2; + rtc0 = &hw_rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200 rootwait"; + stdout-path = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x40000000>; + }; + + can_clk20m: can-clk20m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + can_clk40m: can-clk40m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio_button>; + pinctrl-names = "default"; + + button-2 { + label = "Button2"; + gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-3 { + label = "Button3"; + gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + ifm_led: led { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_gpio_led>; + pinctrl-names = "default", "extended"; + + led-0 { + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + color = ; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + color = ; + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_cs>; + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_ecspi3_cs>; + /delete-property/ dmas; + /delete-property/ dma-names; +}; + +&gpu { + /* SoC has GPU fused off. */ + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + hw_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + + ifm_pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <790000>; + regulator-max-microvolt = <860000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <840000>; + regulator-max-microvolt = <960000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + }; + + ldo5_reg: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x110 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x110 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x190 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + /* SPI3_CAN_CLK */ + MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x110 + /* SPI3_CAN_MOSI */ + MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x110 + /* SPI3_CAN_MISO */ + MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x190 + >; + }; + + pinctrl_gpio_button: gpiobutton-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x96 + MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x96 + >; + }; + + pinctrl_gpio_led: gpioled-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x116 + MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x116 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000110 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000114 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000116 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x150 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&pgc_gpumix { + /* SoC has GPU fused off. */ + status = "disabled"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi new file mode 100644 index 000000000000..c1a98ec2f438 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-ksz8794-common.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Fedor Ross + */ + +#include + +#include "imx8mn-pinfunc.h" + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ksz8794: ethernet-switch@1 { + compatible = "microchip,ksz8794"; + pinctrl-names = "default", "reset"; + pinctrl-0 = <&pinctrl_ks8794>; + pinctrl-1 = <&pinctrl_ks8794>; + reg = <1>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + spi-max-frequency = <5000000>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + fixed-link { + full-duplex; + speed = <1000>; + }; + }; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + status = "okay"; + + fixed-link { + full-duplex; + speed = <1000>; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x10 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; + + pinctrl_ks8794: ks8794-grp { + fsl,pins = < + /* KSZ8794 reset line */ + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso new file mode 100644 index 000000000000..20eb427f3dd6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz8794.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include + +#include "imx8mn-pinfunc.h" + +&pinctrl_ecspi1 { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x10 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x10 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x90 + /* KS8794 nCS */ + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; +}; + +#include "imx8mn-vhip4-evalboard-ksz8794-common.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso new file mode 100644 index 000000000000..de24206106b3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1-overlay-ksz9031.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include "imx8mn-pinfunc.h" + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts new file mode 100644 index 000000000000..5f37065bf43f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v1.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020-2024 Fedor Ross + */ + +/dts-v1/; + +#include "imx8mn-vhip4-evalboard-common.dtsi" + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board v1"; + compatible = "ifm,imx8mn-vhip4-evalboard-v1", "ifm,imx8mn-vhip4-evalboard", + "ifm,imx8mn-vhip4", "fsl,imx8mn"; +}; + +&ifm_led { + pinctrl-1 = <&pinctrl_gpio_led_v1>; + + led-2 { + function = LED_FUNCTION_STATUS; + function-enumerator = <3>; + color = ; + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + function-enumerator = <4>; + color = ; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio5 21 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeprom@0 { + compatible = "anvo,anv32c81w", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <32768>; + address-width = <16>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp25625"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp25625>; + reg = <0>; + clocks = <&can_clk20m>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + }; + + can1: can@1 { + compatible = "microchip,mcp2518fd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp2518>; + reg = <1>; + clocks = <&can_clk40m>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + spi-max-frequency = <20000000>; + }; +}; + +&i2c1 { + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + temperature-sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ifm_pmic { + interrupt-parent = <&gpio2>; + interrupts = <0 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + /* KS8794 nCS */ + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; + }; + + pinctrl_ecspi3_cs: ecspi3-cs-grp { + fsl,pins = < + /* MCP25625 nCS */ + MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x150 + /* MCP2518FD nCS */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x150 + >; + }; + + pinctrl_gpio_5: gpio5-grp { + fsl,pins = < + /* CFG_EEPROM_WP */ + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x140 + >; + }; + + pinctrl_gpio_led_v1: gpioled-v1-grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x116 + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x116 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000056 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000d6 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x56 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0xd6 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000056 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000d6 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x56 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0xd6 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x40000056 + MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x400000d6 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x56 + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0xd6 + >; + }; + + pinctrl_mcp2518: mcp2518-grp { + fsl,pins = < + /* MCP2518 nINT line */ + MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x116 + /* MCP2518 nINT1/GPIO1 line */ + MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x116 + >; + }; + + pinctrl_mcp25625: mcp25625-grp { + fsl,pins = < + /* MCP25625 nINT line */ + MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x156 + >; + }; + + pinctrl_pmic: pmic-irq-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x16 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x142 + MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x142 + >; + }; + + pinctrl_usb_nreset: usbnreset-grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x14a + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_5>; + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", + "ifm_device_info_eeprom_wp", + "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_nreset>; + #address-cells = <1>; + #size-cells = <0>; + + usb-hub@1 { + compatible = "usb424,2512", "usb424,2514"; + reg = <1>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso new file mode 100644 index 000000000000..6ad7434a1787 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-adin1300.dtso @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Fedor Ross + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mn-pinfunc.h" + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + + adi,rx-internal-delay-ps = <1800>; + adi,tx-internal-delay-ps = <2200>; + interrupts-extended = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + }; + }; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x16 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x96 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x96 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x96 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x96 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x96 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x96 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x96 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 + /* nRST */ + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x156 + /* nIRQ */ + MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1d6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso new file mode 100644 index 000000000000..ab1304ebd965 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2-overlay-ksz8794.dtso @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Marek Vasut + */ +/dts-v1/; +/plugin/; + +#include + +#include "imx8mn-pinfunc.h" + +&pinctrl_ecspi1 { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x10 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x10 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x90 + /* KS8794 nCS */ + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x150 + /* ANV32C81 nCS */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + >; +}; + +#include "imx8mn-vhip4-evalboard-ksz8794-common.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts new file mode 100644 index 000000000000..4dadfb7f78de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-vhip4-evalboard-v2.dts @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 Fedor Ross + */ + +/dts-v1/; + +#include "imx8mn-vhip4-evalboard-common.dtsi" + +/ { + model = "ifm i.MX8MNano VHIP4 Evaluation Board v2"; + compatible = "ifm,imx8mn-vhip4-evalboard-v2", "ifm,imx8mn-vhip4-evalboard", + "ifm,imx8mn-vhip4", "fsl,imx8mn"; + + multi-led { + compatible = "leds-group-multicolor"; + color = ; + function = LED_FUNCTION_INDICATOR; + leds = <&rgb_0>, <&rgb_1>, <&rgb_2>; + }; +}; + +&ifm_led { + pinctrl-1 = <&pinctrl_gpio_led_v2>; + + rgb_0: rgb-led-red { + color = ; + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rgb_1: rgb-led-green { + color = ; + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rgb_2: rgb-led-blue { + color = ; + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio1 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeprom@0 { + compatible = "fujitsu,mb85rs64", "atmel,at25"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpha; + spi-cpol; + pagesize = <1>; + size = <32768>; + address-width = <16>; + }; +}; + +&ecspi3 { + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + can0: can@0 { + compatible = "microchip,mcp2518fd"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcp2518>; + reg = <0>; + clocks = <&can_clk40m>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + microchip,rx-int-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + spi-max-frequency = <20000000>; + }; +}; + +&i2c1 { + scl-gpios = <&gpio2 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c3 { + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&ifm_pmic { + interrupt-parent = <&gpio5>; + interrupts = <17 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + /* KS8794 nCS */ + MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x150 + /* Retain memory nCS (FRAM or MRAM) */ + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x150 + /* RETAIN_nHOLD */ + MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x140 + >; + }; + + pinctrl_ecspi3_cs: ecspi3-cs-grp { + fsl,pins = < + /* MCP2518FD nCS */ + MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x150 + >; + }; + + pinctrl_gpio_led_v2: gpioled-v2-grp { + fsl,pins = < + /* LED_RGB_RED */ + MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x116 + /* LED_RGB_GREEN */ + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x116 + /* LED_RGB_BLUE */ + MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x116 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x40000056 + MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x400000d6 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x56 + MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0xd6 + /* CFG_EEPROM_WP */ + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 + /* RTC_nIRQ */ + MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x116 + /* LOG_EE_WP */ + MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x140 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000056 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000d6 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x56 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0xd6 + >; + }; + + pinctrl_mcp2518: mcp2518-grp { + fsl,pins = < + /* CAN0_CLKO */ + MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x116 + /* CAN0_nINT0 */ + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x116 + /* CAN0_nINT1 */ + MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x116 + /* CAN0_nINT */ + MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x116 + >; + }; + + pinctrl_pmic: pmic-irq-grp { + fsl,pins = < + /* PMIC_nIRQ */ + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1d6 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x142 + MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x142 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x64 + >; + }; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", + "ifm_device_info_eeprom_wp", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", + "ifm_logging_eeprom_wp", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; From 730f6b28cb877fdc75bb13bd4d82c270e3bcd3cd Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:07 +0800 Subject: [PATCH 628/757] arm64: dts: imx952: Add idle-states node Add idle-states node and refer it in A55 nodes to enable cpuidle. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi index 33bde271d394..91fe4916ac04 100644 --- a/arch/arm64/boot/dts/freescale/imx952.dtsi +++ b/arch/arm64/boot/dts/freescale/imx952.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR MIT) /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ #include @@ -50,12 +50,27 @@ #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + A55_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX952_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -73,6 +88,7 @@ reg = <0x100>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX952_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -90,6 +106,7 @@ reg = <0x200>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX952_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; @@ -107,6 +124,7 @@ reg = <0x300>; enable-method = "psci"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; power-domains = <&scmi_perf IMX952_PERF_A55>; power-domain-names = "perf"; i-cache-size = <32768>; From 570a0eb963274c6f5457e4ee24a18c0baa47058a Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Sun, 11 Jan 2026 20:40:08 +0800 Subject: [PATCH 629/757] arm64: dts: imx952-evk: Change the usdhc1_200mhz drive strength to DSE4 Set usdhc1_200mhz drive strength need to use DSE4, according to validation team's suggestion, Signed-off-by: Haibo Chen Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 2c753fcbae3c..e5d989bd7c7b 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -159,17 +159,17 @@ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x15fe - IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x13fe - IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x13fe - IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x13fe - IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x13fe - IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x13fe - IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x13fe - IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x13fe - IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x13fe - IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x13fe - IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x15fe + IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e + IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e + IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e + IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e + IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e + IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e + IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e + IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e + IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e + IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e + IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e >; }; From b7f274333167c9ba3343780d2621f7fa90904657 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:09 +0800 Subject: [PATCH 630/757] arm64: dts: imx952-evk: Enable I2C[2,3,4,6,7] bus Enable I2C bus[2,3,4,6,7] and the io-expanders connected to each I2C bus. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 166 +++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index e5d989bd7c7b..98f2f96a91cc 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -17,6 +17,14 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; @@ -79,6 +87,111 @@ }; }; +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + adp5585: io-expander@34 { + compatible = "adi,adp5585-00", "adi,adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + gpio-reserved-ranges = <5 1>; + #pwm-cells = <3>; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + i2c3_pcal6408: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_3p3v>; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c4>; + status = "okay"; + + i2c4_pcal6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_pcal6408>; + vcc-supply = <®_3p3v>; + }; +}; + +&lpi2c6 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c6>; + status = "okay"; + + pcal6416: gpio@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6416>; + vcc-supply = <®_3p3v>; + + pdm-can-sel-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + output-low; + }; + + mqs-en-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-low; + }; + }; +}; + +&lpi2c7 { + clock-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c7>; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio5>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &lpuart1 { /* console */ pinctrl-names = "default"; @@ -112,6 +225,59 @@ }; &scmi_iomuxc { + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x40000b9e + IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e + IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_i2c4_pcal6408: i2c4pcal6408grp { + fsl,pins = < + IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x31e + >; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = < + IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e + IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x40000b9e + IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6416: pcal6416grp { + fsl,pins = < + IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e From fc910b85b27147accce831da2e52a56f17987c3c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:10 +0800 Subject: [PATCH 631/757] arm64: dts: imx952-evk: Enable UART5 Enable UART5 for using Bluetooth. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 98f2f96a91cc..dcc339b766a2 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -28,6 +28,7 @@ mmc0 = &usdhc1; mmc1 = &usdhc2; serial0 = &lpuart1; + serial4 = &lpuart5; }; chosen { @@ -199,6 +200,17 @@ status = "okay"; }; +&lpuart5 { + /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -291,6 +303,15 @@ >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e + IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e + IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e + IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e From ba1d167451875caddb11502fcc26015bbb31d728 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:11 +0800 Subject: [PATCH 632/757] arm64: dts: imx952-evk: Enable SPI7 Enable SPI7 for i.MX952-EVK. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index dcc339b766a2..447aea3cfd07 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -29,6 +29,7 @@ mmc1 = &usdhc2; serial0 = &lpuart1; serial4 = &lpuart5; + spi6 = &lpspi7; }; chosen { @@ -211,6 +212,13 @@ }; }; +&lpspi7 { + cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi7>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -278,6 +286,15 @@ >; }; + pinctrl_lpspi7: lpspi7grp { + fsl,pins = < + IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x39e + IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x39e + IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x39e + IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x39e + >; + }; + pinctrl_pcal6416: pcal6416grp { fsl,pins = < IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e From 8e135b9d57f844da78db760bf22b68a151a0e710 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:12 +0800 Subject: [PATCH 633/757] arm64: dts: imx952-evk: Enable USB[1,2] Enable USB[1,2] and add ptn5110 connected to USB1. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 76 ++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 447aea3cfd07..0b6b28c24e46 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx952.dtsi" / { @@ -87,6 +88,16 @@ enable-active-high; off-on-delay-us = <12000>; }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-name = "USB_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; &lpi2c2 { @@ -192,6 +203,40 @@ interrupt-parent = <&gpio5>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ptn5110>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + }; + }; }; &lpuart1 { @@ -219,6 +264,31 @@ status = "okay"; }; +&usb1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + disable-over-current; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usb2 { + dr_mode = "host"; + disable-over-current; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -307,6 +377,12 @@ >; }; + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e From 1f563af57f255b26d4b788f9219ba17a748ccbe3 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:13 +0800 Subject: [PATCH 634/757] arm64: dts: imx952-evk: Enable wdog3 Enable wdog3 to allow System manager reset Linux. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 0b6b28c24e46..24a3468b1817 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -314,6 +314,11 @@ status = "okay"; }; +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + &scmi_iomuxc { pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < From 13b56cf38fcaf6320d84392c6b6ec783d6def5a1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:14 +0800 Subject: [PATCH 635/757] arm64: dts: imx952-evk: Enable TPM[3,6] Enable TPM[3,6] for PWM. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 34 +++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 24a3468b1817..21b951a21564 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -1,10 +1,11 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright 2025 NXP + * Copyright 2025-2026 NXP */ /dts-v1/; +#include #include #include "imx952.dtsi" @@ -42,6 +43,13 @@ reg = <0x0 0x80000000 0 0x80000000>; }; + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; + cooling-levels = <64 128 192 255>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -264,6 +272,18 @@ status = "okay"; }; +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm3>; + status = "okay"; +}; + +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; + status = "okay"; +}; + &usb1 { dr_mode = "otg"; hnp-disable; @@ -394,6 +414,18 @@ >; }; + pinctrl_tpm3: tpm3grp { + fsl,pins = < + IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x51e + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e From aef607803edda92d2fc853a2e5f3dba6d147d598 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Sun, 11 Jan 2026 20:40:15 +0800 Subject: [PATCH 636/757] arm64: dts: imx952-evk: Add flexcan support Add flexcan support, since flexcan1 share pins with PDM, default disable flexcan1. Signed-off-by: Haibo Chen Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 45 ++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index 21b951a21564..bae7b88f8229 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -64,6 +64,22 @@ }; }; + flexcan1_phy: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + max-bitrate = <8000000>; + enable-gpios = <&pcal6416 6 GPIO_ACTIVE_HIGH>; + standby-gpios = <&pcal6416 5 GPIO_ACTIVE_LOW>; + }; + + flexcan2_phy: can-phy1 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + max-bitrate = <8000000>; + enable-gpios = <&i2c4_pcal6408 4 GPIO_ACTIVE_HIGH>; + standby-gpios = <&i2c4_pcal6408 3 GPIO_ACTIVE_LOW>; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; @@ -108,6 +124,21 @@ }; +/* pin conflict with PDM */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + phys = <&flexcan1_phy>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + phys = <&flexcan2_phy>; + status = "okay"; +}; + &lpi2c2 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -340,6 +371,20 @@ }; &scmi_iomuxc { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e + IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e + IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e + >; + }; + pinctrl_lpi2c2: lpi2c2grp { fsl,pins = < IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e From 2da6336e94c223ee5b8535faf8138f0c8b8f1275 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 11 Jan 2026 20:40:16 +0800 Subject: [PATCH 637/757] arm64: dts: imx952-evk: Add nxp,ctrl-ids for scmi misc Add nxp,ctrl-ids in scmi_misc node for wakeup notification. Signed-off-by: Peng Fan Reviewed-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx952-evk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx952-evk.dts b/arch/arm64/boot/dts/freescale/imx952-evk.dts index bae7b88f8229..b838323468d4 100644 --- a/arch/arm64/boot/dts/freescale/imx952-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx952-evk.dts @@ -9,6 +9,15 @@ #include #include "imx952.dtsi" +#define FALLING_EDGE BIT(0) +#define RISING_EDGE BIT(1) + +#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_M2E_WAKE 0x8001U /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002U /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */ + / { model = "NXP i.MX952 EVK board"; compatible = "fsl,imx952-evk", "fsl,imx952"; @@ -303,6 +312,14 @@ status = "okay"; }; +&scmi_misc { + nxp,ctrl-ids = ; +}; + &tpm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm3>; From 8c898869809ddb3347a7cddcb3a8ceee42b38488 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Tue, 13 Jan 2026 09:50:02 +0200 Subject: [PATCH 638/757] arm64: dts: imx93-11x11-frdm: Add MQS audio support Enable Medium Quality Sound (MQS) output on the i.MX93 FRDM 11x11 board by adding sound card description and enabling sai1 and mqs1 dts nodes, together with necessary clocks and pinmux. This supports audio playback via SAI1 DAI which is connected to the MQS1 block. Co-developed-by: Tom Zheng Signed-off-by: Tom Zheng Signed-off-by: Daniel Baluta Tested-by: Francesco Valla Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-frdm.dts | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts index 066c5139842b..5bb6ae0d154a 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts @@ -81,6 +81,13 @@ no-map; }; }; + + sound-mqs { + compatible = "fsl,imx-audio-mqs"; + model = "mqs-audio"; + audio-cpu = <&sai1>; + audio-codec = <&mqs1>; + }; }; &adc1 { @@ -315,6 +322,27 @@ status = "okay"; }; +&mqs1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mqs1>; + clocks = <&clk IMX93_CLK_MQS1_GATE>; + clock-names = "mclk"; + status = "okay"; +}; + +&sai1 { + #sound-dai-cells = <0>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k"; + assigned-clocks = <&clk IMX93_CLK_SAI1>; + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &usbotg1 { adp-disable; disable-over-current; @@ -479,6 +507,13 @@ >; }; + pinctrl_mqs1: mqs1grp { + fsl,pins = < + MX93_PAD_PDM_CLK__MQS1_LEFT 0x31e + MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x31e + >; + }; + pinctrl_pcal6524: pcal6524grp { fsl,pins = < MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e From e9c48e558696addf692559a9ded4f0064b5e6db2 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Tue, 13 Jan 2026 16:31:34 +0100 Subject: [PATCH 639/757] ARM: dts: imx: tolino-shine2: add tps65185 Wire up the TPS65185 regulator needed for the display. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- .../dts/nxp/imx/imx6sl-tolino-shine2hd.dts | 55 ++++++++++++++++++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts index b6c336e3079e..4c655579f43e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine2hd.dts @@ -37,6 +37,16 @@ stdout-path = &uart1; }; + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; + gpio_keys: gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -147,8 +157,35 @@ touchscreen-inverted-x; }; - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + tps65185: pmic@68 { + compatible = "ti,tps65185"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tps65185_gpio>; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vin-supply = <&epd_pmic_supply>; + pwr-good-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + vcom-ctrl-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + regulators { + vcom_reg: vcom { + regulator-name = "vcom"; + }; + + vposneg_reg: vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + }; + + v3p3_reg: v3p3 { + regulator-name = "v3p3"; + }; + }; + }; }; &i2c3 { @@ -328,6 +365,12 @@ >; }; + pinctrl_epd_pmic_supply: epdc-pmic-supplygrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059 /* pwrall */ + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 @@ -425,6 +468,16 @@ >; }; + pinctrl_tps65185_gpio: tps65185-gpio-grp { + fsl,pins = < + MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */ + MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x40010059 /* wakeup */ + MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* enable */ + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x17059 /* nINT */ + MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* pwr-good */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 From 9fcca3e28533b8ee5a67c83be5defad3ed445e91 Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Tue, 13 Jan 2026 16:31:35 +0100 Subject: [PATCH 640/757] ARM: dts: imx50-kobo-aura: add epd pmic description Kobo Aura (N514) includes a TPS65185 PMIC for the epaper display. Add description for this pmic and its vin power-supply. Signed-off-by: Josua Mayer Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts | 60 ++++++++++++++++++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts index b1a6a9c58ac3..4725ee241cb1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts @@ -58,6 +58,16 @@ }; }; + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; + }; + sd2_pwrseq: pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -135,7 +145,34 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + pmic@68 { + compatible = "ti,tps65185"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic>; + pwr-good-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + vcom-ctrl-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + vin-supply = <&epd_pmic_supply>; + interrupts-extended = <&gpio4 15 IRQ_TYPE_LEVEL_LOW>; + + regulators { + vcom { + regulator-name = "vcom"; + }; + + vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + }; + + v3p3 { + regulator-name = "v3p3"; + }; + }; + }; }; &i2c3 { @@ -161,6 +198,27 @@ >; }; + pinctrl_epd_pmic: epd-pmic-grp { + fsl,pins = < + /* PWRUP */ + MX50_PAD_EPDC_PWRCTRL1__GPIO3_30 0x0 + /* WAKEUP */ + MX50_PAD_EPDC_PWRCTRL0__GPIO3_29 0x0 + /* VCOMCTRL */ + MX50_PAD_EPDC_VCOM0__GPIO4_21 0x0 + /* PWRGOOD: enable internal 100k pull-up */ + MX50_PAD_EPDC_PWRSTAT__GPIO3_28 0xe0 + /* INT: enable internal 100k pull-up */ + MX50_PAD_ECSPI1_SS0__GPIO4_15 0xe0 + >; + }; + + pinctrl_epd_pmic_supply: epd-pmic-supply-grp { + fsl,pins = < + MX50_PAD_EIM_CRE__GPIO1_27 0x0 + >; + }; + pinctrl_gpiokeys: gpiokeysgrp { fsl,pins = < MX50_PAD_CSPI_MISO__GPIO4_10 0x0 From f325a91895d8a9167a7f1268569c1877272f897c Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Tue, 13 Jan 2026 16:31:36 +0100 Subject: [PATCH 641/757] ARM: dts: imx: e60k02: add tps65185 Wire up the TPS65185 regulator needed for the display. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/nxp/imx/e60k02.dtsi | 35 ++++++++++++++++++- .../boot/dts/nxp/imx/imx6sl-tolino-shine3.dts | 26 ++++++++++++++ .../boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts | 26 ++++++++++++++ 3 files changed, 86 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi index 0029c12f16c8..aac7b9ef7627 100644 --- a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi @@ -23,6 +23,14 @@ stdout-path = &uart1; }; + epd_pmic_supply: regulator-epd-pmic-in { + compatible = "regulator-fixed"; + regulator-name = "epd_pmic_supply"; + gpio = <&gpio2 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <20000>; + }; + gpio_keys: gpio-keys { compatible = "gpio-keys"; @@ -119,8 +127,33 @@ vdd-supply = <&ldo5_reg>; }; - /* TODO: TPS65185 PMIC for E Ink at 0x68 */ + tps65185: pmic@68 { + compatible = "ti,tps65185"; + reg = <0x68>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + vin-supply = <&epd_pmic_supply>; + pwr-good-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + vcom-ctrl-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + regulators { + vcom_reg: vcom { + regulator-name = "vcom"; + }; + + vposneg_reg: vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + }; + + v3p3_reg: v3p3 { + regulator-name = "v3p3"; + }; + }; + }; }; &i2c3 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts index 5ba6f15e9ed5..58b9ccd9b605 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sl-tolino-shine3.dts @@ -26,6 +26,11 @@ compatible = "kobo,tolino-shine3", "fsl,imx6sl"; }; +&epd_pmic_supply { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; @@ -59,6 +64,12 @@ >; }; + pinctrl_epd_pmic_supply: epdc-pmic-supplygrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_SD1_DAT1__GPIO5_IO08 0x17059 /* PWR_SW */ @@ -159,6 +170,16 @@ >; }; + pinctrl_tps65185_gpio: tps65185-gpio-grp { + fsl,pins = < + MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */ + MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x40010059 /* wakeup */ + MX6SL_PAD_EPDC_PWRCTRL1__GPIO2_IO08 0x40010059 /* enable */ + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x17059 /* nINT */ + MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x17059 /* pwr-good */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 @@ -308,6 +329,11 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; }; +&tps65185 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tps65185_gpio>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts index 18c9ac8f7560..1000ee8b807a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sll-kobo-clarahd.dts @@ -36,6 +36,11 @@ soc-supply = <&dcdc1_reg>; }; +&epd_pmic_supply { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epd_pmic_supply>; +}; + &gpio_keys { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; @@ -69,6 +74,12 @@ >; }; + pinctrl_epd_pmic_supply: epdc-pmic-supplygrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x40010059 + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SLL_PAD_SD1_DATA1__GPIO5_IO08 0x17059 /* PWR_SW */ @@ -169,6 +180,16 @@ >; }; + pinctrl_tps65185_gpio: tps65185-gpio-grp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x40010059 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x40010059 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL1__GPIO2_IO08 0x40010059 /* enable */ + MX6SLL_PAD_EPDC_PWR_CTRL2__GPIO2_IO09 0x17059 /* nINT */ + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x17059 /* pwr-good */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 @@ -310,6 +331,11 @@ pinctrl-0 = <&pinctrl_ricoh_gpio>; }; +&tps65185 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tps65185_gpio>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; From 1a7d97c2d3868c7c7b74b26d4af210e22666171b Mon Sep 17 00:00:00 2001 From: Francesco Valla Date: Thu, 15 Jan 2026 18:11:34 +0100 Subject: [PATCH 642/757] arm64: dts: imx93-11x11-frdm: enable additional devices Enable additional devices on the i.MX93 FRDM board: - CAN port and associated transceiver - Bluetooth portion of the IW612 chipset - WiFi SDIO port - user buttons The WiFi portion of the on-board IW612 chipset is still not supported upstream, but since SDIO is a discoverable bus it will be probed once it is. Signed-off-by: Francesco Valla Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx93-11x11-frdm.dts | 152 ++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts index 5bb6ae0d154a..bd14ba28690c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-frdm.dts @@ -9,6 +9,7 @@ model = "NXP i.MX93 11X11 FRDM board"; aliases { + can0 = &flexcan2; ethernet0 = &fec; ethernet1 = &eqos; i2c0 = &lpi2c1; @@ -18,12 +19,40 @@ mmc1 = &usdhc2; /* uSD */ rtc0 = &pcf2131; serial0 = &lpuart1; + serial4 = &lpuart5; }; chosen { stdout-path = &lpuart1; }; + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-k2 { + label = "Button K2"; + linux,code = ; + gpios = <&pcal6524 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + interrupt-parent = <&pcal6524>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + }; + + button-k3 { + label = "Button K3"; + linux,code = ; + gpios = <&pcal6524 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + interrupt-parent = <&pcal6524>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + }; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; off-on-delay-us = <12000>; @@ -37,6 +66,16 @@ enable-active-high; }; + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-name = "VPCIe_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <20000>; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reserved-memory { ranges; #address-cells = <2>; @@ -88,6 +127,11 @@ audio-cpu = <&sai1>; audio-codec = <&mqs1>; }; + + usdhc3_pwrseq: mmc-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; + }; }; &adc1 { @@ -157,11 +201,27 @@ }; }; +&flexcan2 { + phys = <&flexcan2_phy>; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; + pinctrl-names = "default", "sleep"; + status = "okay"; +}; + &lpi2c1 { clock-frequency = <400000>; pinctrl-0 = <&pinctrl_lpi2c1>; pinctrl-names = "default"; status = "okay"; + + pcal6408: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>; + }; }; &lpi2c2 { @@ -322,6 +382,21 @@ status = "okay"; }; +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + uart-has-rtscts; + + bluetooth { + compatible = "nxp,88w8987-bt"; + device-wakeup-gpios = <&pcal6408 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pcal6524 19 GPIO_ACTIVE_LOW>; + vcc-supply = <®_usdhc3_vmmc>; + }; +}; + &mqs1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mqs1>; @@ -394,6 +469,20 @@ status = "okay"; }; +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + status = "okay"; +}; + &wdog3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; @@ -486,6 +575,13 @@ >; }; + pinctrl_flexcan2_sleep: flexcan2sleepgrp { + fsl,pins = < + MX93_PAD_GPIO_IO25__GPIO2_IO25 0x31e + MX93_PAD_GPIO_IO27__GPIO2_IO27 0x31e + >; + }; + pinctrl_lpi2c1: lpi2c1grp { fsl,pins = < MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e @@ -533,6 +629,15 @@ >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < @@ -647,6 +752,53 @@ >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3grpsleepgrp { + fsl,pins = < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e + MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e From 868f5c154c25b7b2fba29c5c07f3b22a7ec8d49e Mon Sep 17 00:00:00 2001 From: Francesco Valla Date: Thu, 15 Jan 2026 18:41:10 +0100 Subject: [PATCH 643/757] arm64: dts: imx91-11x11-frdm: fix CAN transceiver gpio According to the HW schematic, the CAN transceiver does not have an enable pin but a silent one. Fix the GPIO property name and polarity. Fixes: b4bf5e55899e ("arm64: dts: freescale: Add FRDM-IMX91 basic support") Signed-off-by: Francesco Valla Acked-by: Daniel Baluta Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts index 0d1acf8a55a5..c25561574d3f 100644 --- a/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts +++ b/arch/arm64/boot/dts/freescale/imx91-11x11-frdm.dts @@ -39,7 +39,7 @@ compatible = "nxp,tja1051"; #phy-cells = <0>; max-bitrate = <5000000>; - enable-gpios = <&pcal6524 23 GPIO_ACTIVE_LOW>; + silent-gpios = <&pcal6524 23 GPIO_ACTIVE_HIGH>; }; gpio-keys { From b17171492e9897f2c283d7b62d7a283cbbeee6d0 Mon Sep 17 00:00:00 2001 From: Lei Xu Date: Fri, 16 Jan 2026 00:56:13 -0800 Subject: [PATCH 644/757] dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 FRDM board Introduce a new DT compatible string for the NXP i.MX95 15x15 FRDM development board, a compact and cost-effective platform based on the i.MX95 applications processor. Acked-by: Krzysztof Kozlowski Reviewed-by: Daniel Baluta Reviewed-by: Laurentiu Mihalcea Signed-off-by: Lei Xu Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index b45047c15ef1..36e885f7d13c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1446,6 +1446,7 @@ properties: items: - enum: - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board + - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 From 9bdfeed989b126a3c9c5a6f74ad2d96784b69d27 Mon Sep 17 00:00:00 2001 From: Lei Xu Date: Fri, 16 Jan 2026 00:56:14 -0800 Subject: [PATCH 645/757] arm64: dts: freescale: imx95: Add support for i.MX95 15x15 FRDM board The i.MX95 15x15 FRDM board is a compact and cost-effective development platform based on the i.MX95 applications processor. Add device tree support for this board, including: - LPUART1 and LPUART5 - NETC - USB - PCIe - uSDHC1, uSDHC2 and uSDHC3 - FlexCAN2 and FlexCAN5 - LPI2C2, LPI2C3, LPI2C4 and their child nodes - Watchdog3 Reviewed-by: Laurentiu Mihalcea Signed-off-by: Lei Xu Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx95-15x15-frdm.dts | 964 ++++++++++++++++++ 2 files changed, 965 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 83df038701de..700bab4d3e60 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -441,6 +441,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx943-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-frdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts new file mode 100644 index 000000000000..ca1c4966c867 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-frdm.dts @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "imx95.dtsi" + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 /*!< PCAL6408A-0 */ +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /*!< PCAL6408A-4 */ +#define BRD_SM_CTRL_BT_WAKE 0x8002 /*!< PCAL6408A-5 */ +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /*!< PCAL6408A-6 */ +#define BRD_SM_CTRL_BUTTON 0x8004 /*!< PCAL6408A-7 */ + +/ { + compatible = "fsl,imx95-15x15-frdm", "fsl,imx95"; + model = "NXP i.MX95 15X15 FRDM board"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &lpuart1; + serial4 = &lpuart5; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + stdout-path = &lpuart1; + }; + + dmic: dmic { + compatible = "dmic-codec"; + #sound-dai-cells = <0>; + num-channels = <2>; + }; + + flexcan2_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + /* + * Shared SILENT GPIO: CAN PHYs enter silent mode + * together (hardware design). + */ + silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; + }; + + flexcan5_phy: can-phy { + compatible = "nxp,tja1051"; + #phy-cells = <0>; + max-bitrate = <5000000>; + silent-gpios = <&pcal6524 7 GPIO_ACTIVE_HIGH>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "+V5.0_SW"; + }; + + reg_ext_3v3: regulator-ext-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCCEXT_3V3"; + }; + + reg_ext_5v: regulator-ext-5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "VCCEXT_5V"; + gpio = <&pcal6524 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_ekey_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power-ekey"; + gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_m2_mkey_pwr: regulator-m2-mkey-pwr { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-mkey-power"; + gpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_SD2_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_ekey_pwr>; + gpio = <&pcal6524 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_usb_vbus: regulator-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_VBUS"; + gpio = <&pcal6524 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: memory@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: memory@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: memory@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: memory@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: memory@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: memory@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vpu_boot: memory@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + link-name = "micfil hifi"; + format = "i2s"; + + cpu { + sound-dai = <&micfil>; + }; + + codec { + sound-dai = <&dmic>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pcal6524 8 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + phys = <&flexcan2_phy>; + status = "okay"; +}; + +&flexcan5 { + pinctrl-0 = <&pinctrl_flexcan5>; + pinctrl-names = "default"; + phys = <&flexcan5_phy>; + status = "okay"; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + gpio-line-names = "ENET1 PHY reset", + "ENET2 PHY reset", + "SPI3/GPIO select", + "UART3/GPIO select", + "CAN2&5/GPIO select", + "PWM/GPIO select", + "Watch dog enable", + "CAN1&2&5 silent", + "SDIO_nRST", + "WL_nDISABLE1", + "WL_nDISABLE2", + "M.2 Mkey NC06", + "EXT_5V0_PWR_EN", + "EXT_3V3_PWR_EN", + "Mkey power control", + "USB2 power control", + "Ekey power control", + "MIPI-DSICSI reset", + "MIPI-DSI IO2", + "MIPI-CSI reset", + "LVDS TP reset", + "LVDS BL enable", + "LVDS BL power enable", + "IT6263 reset"; + + lpspi-gpio-sel-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + }; + + lpuart-gpio-sel-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-low; + }; + + can-gpio-sel-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-low; + }; + + pwm-gpio-sel-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ptn5110>; + pinctrl-names = "default"; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-names = "default"; + status = "okay"; + + pca9632: led-controller@62 { + compatible = "nxp,pca9632"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + nxp,inverted-out; + + led_backlight0: led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <0>; + }; + + led_backlight1: led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <1>; + }; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +/* Configure MSI and IOMMU mappings specific to the i.MX95 15x15 FRDM board. */ +&netc_bus0 { + msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; //NETC Timer + iommu-map = <0x0 &smmu 0x20 0x1>, + <0x10 &smmu 0x21 0x1>, + <0x20 &smmu 0x22 0x1>, + <0x40 &smmu 0x23 0x1>, + <0x50 &smmu 0x25 0x1>, + <0x60 &smmu 0x26 0x1>, + <0x80 &smmu 0x24 0x1>, + <0xc0 &smmu 0x27 0x1>; +}; + +&netc_emdio { + pinctrl-0 = <&pinctrl_emdio>; + pinctrl-names = "default"; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 0 GPIO_ACTIVE_LOW>; + }; + + ethphy1: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 1 GPIO_ACTIVE_LOW>; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; + supports-clkreq; + vpcie-supply = <®_m2_mkey_pwr>; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e + IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e + >; + }; + + pinctrl_flexcan5: flexcan5grp { + fsl,pins = < + IMX95_PAD_GPIO_IO22__CAN5_TX 0x39e + IMX95_PAD_GPIO_IO23__CAN5_RX 0x39e + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids = ; +}; + +&thermal_zones { + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&usb2 { + disable-over-current; + dr_mode = "host"; + vbus-supply = <®_usb_vbus>; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; From db5e9260be8d3437222df74b5074359b22f1f029 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 25 Dec 2025 18:36:15 +0800 Subject: [PATCH 646/757] ARM: dts: allwinner: Replace status "failed" with "fail" The device tree bindings specify using "fail", not "failed". Fix up all the ones that are wrong. Link: https://patch.msgid.link/20251225103616.3203473-5-wens@kernel.org Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts | 2 +- arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts | 2 +- arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts | 2 +- arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts index 63e77c05bfda..f2413ba6a858 100644 --- a/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-dserve-dsrv9703c.dts @@ -112,7 +112,7 @@ &i2c1 { /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; + status = "fail"; }; &i2c2 { diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts index c32596947647..e0c7099015da 100644 --- a/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts +++ b/arch/arm/boot/dts/allwinner/sun4i-a10-pov-protab2-ips9.dts @@ -96,7 +96,7 @@ &i2c1 { /* pull-ups and devices require AXP209 LDO3 */ - status = "failed"; + status = "fail"; }; &i2c2 { diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts index 5bce7a32651e..5dfd36e3a49d 100644 --- a/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/allwinner/sun6i-a31-hummingbird.dts @@ -170,7 +170,7 @@ &i2c0 { /* pull-ups and devices require AXP221 DLDO3 */ - status = "failed"; + status = "fail"; }; &i2c1 { diff --git a/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts b/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts index b32b70ada7fd..fefd887fbc39 100644 --- a/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts +++ b/arch/arm/boot/dts/allwinner/sun6i-a31s-primo81.dts @@ -90,7 +90,7 @@ &i2c0 { /* pull-ups and device VDDIO use AXP221 DLDO3 */ - status = "failed"; + status = "fail"; }; &i2c1 { From 18649ffbb63bca40896f973b6997914f9d603b1e Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:58 +0800 Subject: [PATCH 647/757] riscv: dts: anlogic: dr1v90: Add "b" ISA extension "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update dr1v90.dtsi to conform to this rule. Line balancing is performed to improve readability. Signed-off-by: Guodong Xu Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi index a5d0765ade32..9fe183f5f5c8 100644 --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -27,8 +27,9 @@ mmu-type = "riscv,sv39"; reg = <0>; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc", - "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", + "zba", "zbb", "zbc", "zbkc", "zbs", + "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; cpu0_intc: interrupt-controller { From a8e3d66ff5c0c37e7c10b3e486d2c5047bf9cf2b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 13:56:23 +0100 Subject: [PATCH 648/757] dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant Add support for the mediatek,mt8192-audsys compatible, which uses a different audio controller (mt8192-afe-pcm) compared to mt8183 and mt2701. This resolves a dtbs_check warning on all MT8192 devicetrees. Reviewed-by: Rob Herring (Arm) Signed-off-by: AngeloGioacchino Del Regno --- .../arm/mediatek/mediatek,audsys.yaml | 46 +++++++++++++------ 1 file changed, 33 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml index f3a761cbd0fd..09a6c16e7e82 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -48,19 +48,39 @@ required: - compatible - '#clock-cells' -if: - properties: - compatible: - contains: - const: mediatek,mt8183-audiosys -then: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt8183-audio.yaml# -else: - properties: - audio-controller: - $ref: /schemas/sound/mediatek,mt2701-audio.yaml# +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-audsys + - mediatek,mt7622-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-audiosys + then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt8183-audio.yaml# + + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-audsys + then: + properties: + audio-controller: + $ref: /schemas/sound/mt8192-afe-pcm.yaml# + additionalProperties: false From 25556c12f4d3edc2f614f752f204c3941697b30a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 15 Jan 2026 13:56:24 +0100 Subject: [PATCH 649/757] arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to audio-controller Device tree nodes should have generic names, and this one doesn't. Rename the mt8192-afe-pcm subnode of audsys to `audio-controller`. This commit brings no functional changes, but resolves dtbs_check warnings. Acked-by: Rob Herring (Arm) Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 47dea10dd3b8..9f8f115edd4c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -973,7 +973,7 @@ reg = <0 0x11210000 0 0x2000>; #clock-cells = <1>; - afe: mt8192-afe-pcm { + afe: audio-controller { compatible = "mediatek,mt8192-audio"; interrupts = ; resets = <&watchdog 17>; From 4cf8d541f4716444b61a919e3fe6f04814165782 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 21 Jun 2025 15:19:58 +0200 Subject: [PATCH 650/757] ARM: dts: qcom: msm8974: Sort header includes alphabetically Before adding more headers in a random order, let's sort the includes once so that's done. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250621-msm8974-rpmpd-switch-v1-3-0a2cb303c446@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 7e119370f337..8459a840d9ff 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -1,14 +1,14 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -#include -#include #include #include #include #include -#include #include +#include +#include +#include / { #address-cells = <1>; From df7c440c904f754d8c94863a910d99e7ed8bbda9 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sat, 21 Jun 2025 15:19:59 +0200 Subject: [PATCH 651/757] ARM: dts: qcom: msm8974: Start using rpmpd for power domains Due to historical reasons all msm8974 boards have used the CX power rail as regulator instead of going through the power domain framework. Since rpmpd has gained msm8974 support quite a bit ago, let's start using it and replace all usages of pm8841_s2 (CX), pm8841_s4 (GFX) and for the boards using pma8084 pma8084_s2 (CX), pma8084_s7 (GFX). For reference, downstream is using GFX power rail as parent-supply for mmcc's OXILI_GDSC GDSC which then is used for GPU, but nothing there is modelled upstream. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20250621-msm8974-rpmpd-switch-v1-4-0a2cb303c446@lucaweiss.eu Signed-off-by: Bjorn Andersson --- .../dts/qcom/qcom-apq8074-dragonboard.dts | 13 ------ .../qcom-msm8974-lge-nexus5-hammerhead.dts | 12 ----- .../dts/qcom/qcom-msm8974-samsung-hlte.dts | 12 ----- .../qcom/qcom-msm8974-sony-xperia-rhine.dtsi | 12 ----- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 44 +++++++++++++++++++ .../qcom/qcom-msm8974pro-fairphone-fp2.dts | 8 ---- .../boot/dts/qcom/qcom-msm8974pro-htc-m8.dts | 11 ----- .../qcom/qcom-msm8974pro-oneplus-bacon.dts | 9 ---- .../qcom-msm8974pro-samsung-klte-common.dtsi | 11 ++--- ...msm8974pro-sony-xperia-shinano-common.dtsi | 12 ----- 10 files changed, 48 insertions(+), 96 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index 34b0cf35fdac..d3ae6c6a6f83 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -198,15 +198,12 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; - firmware-name = "qcom/apq8074/adsp.mbn"; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -225,20 +222,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index 8f4a1fda9276..e34d7b864e30 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -369,12 +369,10 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -390,20 +388,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts index b7a1367d3470..7f61f80761e1 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts @@ -188,12 +188,10 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -209,20 +207,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi index d7322fc6a095..96682d82b1c3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-sony-xperia-rhine.dtsi @@ -204,12 +204,10 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -225,20 +223,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 8459a840d9ff..2a82ddce94a2 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include / { @@ -146,6 +147,40 @@ clocks = <&xo_board>; clock-names = "xo"; }; + + rpmpd: power-controller { + compatible = "qcom,msm8974-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; }; }; }; @@ -743,6 +778,9 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; + power-domains = <&rpmpd MSM8974_VDDCX>; + power-domain-names = "cx"; + qcom,smem-states = <&wcnss_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -1545,6 +1583,9 @@ resets = <&gcc GCC_MSS_RESTART>; reset-names = "mss_restart"; + power-domains = <&rpmpd MSM8974_VDDCX>; + power-domain-names = "cx"; + qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>; qcom,smem-states = <&modem_smp2p_out 0>; @@ -2208,6 +2249,9 @@ clocks = <&xo_board>; clock-names = "xo"; + power-domains = <&rpmpd MSM8974_VDDCX>; + power-domain-names = "cx"; + memory-region = <&adsp_region>; qcom,smem-states = <&adsp_smp2p_out 0>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts index fe227fd3f908..a081aeadd1d4 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts @@ -156,7 +156,6 @@ status = "okay"; vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; vddpx-supply = <&pm8941_s3>; pinctrl-names = "default"; @@ -181,12 +180,10 @@ &remoteproc_adsp { status = "okay"; - cx-supply = <&pm8841_s2>; }; &remoteproc_mss { status = "okay"; - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -201,11 +198,6 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts index b896cc1ad6f7..402372834c53 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts @@ -70,7 +70,6 @@ &pronto { vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; vddpx-supply = <&pm8941_s3>; pinctrl-0 = <&wcnss_pin_a>; @@ -104,20 +103,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <815000>; - regulator-max-microvolt = <900000>; - }; }; regulators-1 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts index 88ff6535477b..258bbbecd927 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-oneplus-bacon.dts @@ -214,7 +214,6 @@ &pronto { vddmx-supply = <&pm8841_s1>; - vddcx-supply = <&pm8841_s2>; vddpx-supply = <&pm8941_s3>; pinctrl-names = "default"; @@ -240,8 +239,6 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; - status = "okay"; }; @@ -254,12 +251,6 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - pm8841_s3: s3 { regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi index d3959741d2ea..56a1a25f3df3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-samsung-klte-common.dtsi @@ -453,12 +453,10 @@ &remoteproc_adsp { status = "okay"; - cx-supply = <&pma8084_s2>; }; &remoteproc_mss { status = "okay"; - cx-supply = <&pma8084_s2>; mss-supply = <&pma8084_s6>; mx-supply = <&pma8084_s1>; pll-supply = <&pma8084_l12>; @@ -474,11 +472,6 @@ regulator-always-on; }; - pma8084_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pma8084_s3: s3 { regulator-min-microvolt = <1300000>; regulator-max-microvolt = <1300000>; @@ -648,6 +641,10 @@ }; }; +&rpmpd { + compatible = "qcom,msm8974pro-pma8084-rpmpd"; +}; + &sdhc_1 { status = "okay"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi index 6af7c71c7158..3d2de30b495e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi @@ -207,12 +207,10 @@ }; &remoteproc_adsp { - cx-supply = <&pm8841_s2>; status = "okay"; }; &remoteproc_mss { - cx-supply = <&pm8841_s2>; mss-supply = <&pm8841_s3>; mx-supply = <&pm8841_s1>; pll-supply = <&pm8941_l12>; @@ -228,20 +226,10 @@ regulator-max-microvolt = <1050000>; }; - pm8841_s2: s2 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; - pm8841_s3: s3 { regulator-min-microvolt = <500000>; regulator-max-microvolt = <1050000>; }; - - pm8841_s4: s4 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1050000>; - }; }; regulators-1 { From 589deb6bc2757787f2b15a84017c23839db3bf8e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 28 Oct 2025 17:40:49 +0100 Subject: [PATCH 652/757] arm64: dts: qcom: msm8953: Re-sort tlmm pinctrl states Follow the Devicetree Sources Coding Style and sort the pinctrl nodes by the pins property. This makes it simpler to add new pinctrl states in the future. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251028-msm8953-cci-v2-4-b5f9f7135326@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 611 +++++++++++++------------- 1 file changed, 305 insertions(+), 306 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 76317c578349..7884a3ed8aef 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -545,6 +545,20 @@ interrupt-controller; #interrupt-cells = <2>; + i2c_1_default: i2c-1-default-state { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + i2c_1_sleep: i2c-1-sleep-state { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + uart_console_active: uart-console-active-state { pins = "gpio4", "gpio5"; function = "blsp_uart2"; @@ -559,6 +573,297 @@ bias-pull-down; }; + i2c_2_default: i2c-2-default-state { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + i2c_2_sleep: i2c-2-sleep-state { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_3_default: spi-3-default-state { + cs-pins { + pins = "gpio10"; + function = "blsp_spi3"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "blsp_spi3"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_3_sleep: spi-3-sleep-state { + cs-pins { + pins = "gpio10"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + i2c_3_default: i2c-3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + i2c_3_sleep: i2c-3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_default: i2c-4-default-state { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_sleep: i2c-4-sleep-state { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_5_default: spi-5-default-state { + cs-pins { + pins = "gpio18"; + function = "blsp_spi5"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "blsp_spi5"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_5_sleep: spi-5-sleep-state { + cs-pins { + pins = "gpio18"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio16", "gpio17", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + uart_5_default: uart-5-default-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "blsp_uart5"; + drive-strength = <16>; + bias-disable; + }; + + uart_5_sleep: uart-5-sleep-state { + pins = "gpio16", "gpio17", "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_default: i2c-5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_sleep: i2c-5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_6_default: spi-6-default-state { + cs-pins { + pins = "gpio22"; + function = "blsp_spi6"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "blsp_spi6"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_6_sleep: spi-6-sleep-state { + cs-pins { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio20", "gpio21", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + i2c_6_default: i2c-6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + i2c_6_sleep: i2c-6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcnss_pin_a: wcnss-active-state { + wcss-wlan2-pins { + pins = "gpio76"; + function = "wcss_wlan2"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan1-pins { + pins = "gpio77"; + function = "wcss_wlan1"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan0-pins { + pins = "gpio78"; + function = "wcss_wlan0"; + drive-strength = <6>; + bias-pull-up; + }; + + wcss-wlan-pins { + pins = "gpio79", "gpio80"; + function = "wcss_wlan"; + drive-strength = <6>; + bias-pull-up; + }; + }; + + gpio_key_default: gpio-key-default-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c_8_default: i2c-8-default-state { + pins = "gpio98", "gpio99"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + i2c_8_sleep: i2c-8-sleep-state { + pins = "gpio98", "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_on: cd-on-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_default: i2c-7-default-state { + pins = "gpio135", "gpio136"; + function = "blsp_i2c7"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_sleep: i2c-7-sleep-state { + pins = "gpio135", "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_7_default: spi-7-default-state { + cs-pins { + pins = "gpio136"; + function = "blsp_spi7"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio135", "gpio137", "gpio138"; + function = "blsp_spi7"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_7_sleep: spi-7-sleep-state { + cs-pins { + pins = "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi-pins { + pins = "gpio135", "gpio137", "gpio138"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + sdc1_clk_on: sdc1-clk-on-state { pins = "sdc1_clk"; bias-disable; @@ -640,312 +945,6 @@ bias-pull-up; drive-strength = <2>; }; - - sdc2_cd_on: cd-on-state { - pins = "gpio133"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - sdc2_cd_off: cd-off-state { - pins = "gpio133"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - gpio_key_default: gpio-key-default-state { - pins = "gpio85"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - - i2c_1_default: i2c-1-default-state { - pins = "gpio2", "gpio3"; - function = "blsp_i2c1"; - drive-strength = <2>; - bias-disable; - }; - - i2c_1_sleep: i2c-1-sleep-state { - pins = "gpio2", "gpio3"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_2_default: i2c-2-default-state { - pins = "gpio6", "gpio7"; - function = "blsp_i2c2"; - drive-strength = <2>; - bias-disable; - }; - - i2c_2_sleep: i2c-2-sleep-state { - pins = "gpio6", "gpio7"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_3_default: i2c-3-default-state { - pins = "gpio10", "gpio11"; - function = "blsp_i2c3"; - drive-strength = <2>; - bias-disable; - }; - - i2c_3_sleep: i2c-3-sleep-state { - pins = "gpio10", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_4_default: i2c-4-default-state { - pins = "gpio14", "gpio15"; - function = "blsp_i2c4"; - drive-strength = <2>; - bias-disable; - }; - - i2c_4_sleep: i2c-4-sleep-state { - pins = "gpio14", "gpio15"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_5_default: i2c-5-default-state { - pins = "gpio18", "gpio19"; - function = "blsp_i2c5"; - drive-strength = <2>; - bias-disable; - }; - - i2c_5_sleep: i2c-5-sleep-state { - pins = "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_6_default: i2c-6-default-state { - pins = "gpio22", "gpio23"; - function = "blsp_i2c6"; - drive-strength = <2>; - bias-disable; - }; - - i2c_6_sleep: i2c-6-sleep-state { - pins = "gpio22", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_7_default: i2c-7-default-state { - pins = "gpio135", "gpio136"; - function = "blsp_i2c7"; - drive-strength = <2>; - bias-disable; - }; - - i2c_7_sleep: i2c-7-sleep-state { - pins = "gpio135", "gpio136"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - i2c_8_default: i2c-8-default-state { - pins = "gpio98", "gpio99"; - function = "blsp_i2c8"; - drive-strength = <2>; - bias-disable; - }; - - i2c_8_sleep: i2c-8-sleep-state { - pins = "gpio98", "gpio99"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi_3_default: spi-3-default-state { - cs-pins { - pins = "gpio10"; - function = "blsp_spi3"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio8", "gpio9", "gpio11"; - function = "blsp_spi3"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_3_sleep: spi-3-sleep-state { - cs-pins { - pins = "gpio10"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio8", "gpio9", "gpio11"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_5_default: spi-5-default-state { - cs-pins { - pins = "gpio18"; - function = "blsp_spi5"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio16", "gpio17", "gpio19"; - function = "blsp_spi5"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_5_sleep: spi-5-sleep-state { - cs-pins { - pins = "gpio18"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio16", "gpio17", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_6_default: spi-6-default-state { - cs-pins { - pins = "gpio22"; - function = "blsp_spi6"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio20", "gpio21", "gpio23"; - function = "blsp_spi6"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_6_sleep: spi-6-sleep-state { - cs-pins { - pins = "gpio22"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio20", "gpio21", "gpio23"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - spi_7_default: spi-7-default-state { - cs-pins { - pins = "gpio136"; - function = "blsp_spi7"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio135", "gpio137", "gpio138"; - function = "blsp_spi7"; - drive-strength = <12>; - bias-disable; - }; - }; - - spi_7_sleep: spi-7-sleep-state { - cs-pins { - pins = "gpio136"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - spi-pins { - pins = "gpio135", "gpio137", "gpio138"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - }; - - uart_5_default: uart-5-default-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "blsp_uart5"; - drive-strength = <16>; - bias-disable; - }; - - uart_5_sleep: uart-5-sleep-state { - pins = "gpio16", "gpio17", "gpio18", "gpio19"; - function = "gpio"; - drive-strength = <2>; - bias-disable; - }; - - wcnss_pin_a: wcnss-active-state { - - wcss-wlan2-pins { - pins = "gpio76"; - function = "wcss_wlan2"; - drive-strength = <6>; - bias-pull-up; - }; - - wcss-wlan1-pins { - pins = "gpio77"; - function = "wcss_wlan1"; - drive-strength = <6>; - bias-pull-up; - }; - - wcss-wlan0-pins { - pins = "gpio78"; - function = "wcss_wlan0"; - drive-strength = <6>; - bias-pull-up; - }; - - wcss-wlan-pins { - pins = "gpio79", "gpio80"; - function = "wcss_wlan"; - drive-strength = <6>; - bias-pull-up; - }; - }; }; gcc: clock-controller@1800000 { From 842c0aa3e04201bc13f51f5ce9edbb8100ef0d73 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 28 Oct 2025 17:40:50 +0100 Subject: [PATCH 653/757] arm64: dts: qcom: msm8953: Add CCI nodes Add the nodes for the camera I2C bus on the MSM8953 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251028-msm8953-cci-v2-5-b5f9f7135326@lucaweiss.eu Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 57 +++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 7884a3ed8aef..753167c3f861 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -753,6 +753,20 @@ bias-disable; }; + cci0_default: cci0-default-state { + pins = "gpio29", "gpio30"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + + cci1_default: cci1-default-state { + pins = "gpio31", "gpio32"; + function = "cci_i2c"; + drive-strength = <2>; + bias-disable; + }; + wcnss_pin_a: wcnss-active-state { wcss-wlan2-pins { pins = "gpio76"; @@ -1200,6 +1214,49 @@ }; }; + cci: cci@1b0c000 { + compatible = "qcom,msm8953-cci"; + reg = <0x1b0c000 0x4000>; + + interrupts = ; + + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>, + <&gcc GCC_CAMSS_AHB_CLK>; + clock-names = "camss_top_ahb", + "cci_ahb", + "cci", + "camss_ahb"; + + assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, + <&gcc GCC_CAMSS_CCI_CLK>; + assigned-clock-rates = <80000000>, + <19200000>; + + pinctrl-0 = <&cci0_default &cci1_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + cci_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gpu: gpu@1c00000 { compatible = "qcom,adreno-506.0", "qcom,adreno"; reg = <0x01c00000 0x40000>; From 9e834e768d0b2e9007cd6a5c778d2d8e3674e78f Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 28 Oct 2025 17:40:51 +0100 Subject: [PATCH 654/757] arm64: dts: qcom: sdm632-fairphone-fp3: Add camera fixed regulators Add the definitions for a few fixed regulators found on the Fairphone 3. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251028-msm8953-cci-v2-6-b5f9f7135326@lucaweiss.eu Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm632-fairphone-fp3.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 55a45b528bd3..557925a66276 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -36,6 +36,42 @@ }; }; + vreg_cam_af_2p85: regulator-cam-af-2p85 { + compatible = "regulator-fixed"; + regulator-name = "cam_af_2p85"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vreg_cam_io_1p8: regulator-cam-io-1p8 { + compatible = "regulator-fixed"; + regulator-name = "cam_io_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 130 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + + vreg_cam2_dig_1p2: regulator-cam2-dig-1p2 { + compatible = "regulator-fixed"; + regulator-name = "cam2_dig_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vph_pwr>; + }; + /* Dummy regulator until PMI632 has LCDB VSP/VSN support */ lcdb_dummy: regulator-lcdb-dummy { compatible = "regulator-fixed"; From cfc22c2121cbf8bb75cb9a9993f13c17587ed55e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 28 Oct 2025 17:40:52 +0100 Subject: [PATCH 655/757] arm64: dts: qcom: sdm632-fairphone-fp3: Enable CCI and add EEPROM Enable the CCI where the camera modules are connected to, and add a node for the EEPROM found next to the IMX363 rear camera. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251028-msm8953-cci-v2-7-b5f9f7135326@lucaweiss.eu Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm632-fairphone-fp3.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts index 557925a66276..0edb2992b902 100644 --- a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -88,6 +88,27 @@ }; }; +&cci { + status = "okay"; +}; + +&cci_i2c0 { + /* Sony IMX363 (rear) @ 0x10 */ + + eeprom@50 { + compatible = "belling,bl24s64", "atmel,24c64"; + reg = <0x50>; + vcc-supply = <&vreg_cam_io_1p8>; + read-only; + }; + + /* ON Semi LC898217 VCM @ 0x72 */ +}; + +&cci_i2c1 { + /* Samsung S5K4H7YX (front) @ 0x10 */ +}; + &gpu { status = "okay"; }; From 4535af3dc91c43c16c31e4e2ad9e79cead0ef308 Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Mon, 24 Nov 2025 15:35:22 -0800 Subject: [PATCH 656/757] ARM: dts: qcom: msm8960: Add GSBI2 & GSBI7 Add the GSBI2 & GSBI7 Node, which is similar to the other GSBI nodes in this file. Reviewed-by: Konrad Dybcio Signed-off-by: Rudraksha Gupta Link: https://lore.kernel.org/r/20251124-expressatt_nfc_accel_magn_light-v4-1-9c5686ad67e2@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 96 ++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 38bd4fd8dda5..fd28401cebb5 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -149,6 +149,24 @@ }; }; + i2c2_default_state: i2c2-default-state { + i2c2-pins { + pins = "gpio12", "gpio13"; + function = "gsbi2"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c2_sleep_state: i2c2-sleep-state { + i2c2-pins { + pins = "gpio12", "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + i2c3_default_state: i2c3-default-state { i2c3-pins { pins = "gpio16", "gpio17"; @@ -167,6 +185,24 @@ }; }; + i2c7_default_state: i2c7-default-state { + i2c7-pins { + pins = "gpio32", "gpio33"; + function = "gsbi7"; + drive-strength = <8>; + bias-disable; + }; + }; + + i2c7_sleep_state: i2c7-sleep-state { + i2c7-pins { + pins = "gpio32", "gpio33"; + function = "gpio"; + drive-strength = <2>; + bias-bus-hold; + }; + }; + i2c8_default_state: i2c8-default-state { i2c8-pins { pins = "gpio36", "gpio37"; @@ -543,6 +579,36 @@ }; }; + gsbi2: gsbi@16100000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16100000 0x100>; + ranges; + cell-index = <2>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi2_i2c: i2c@16180000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16180000 0x1000>; + pinctrl-0 = <&i2c2_default_state>; + pinctrl-1 = <&i2c2_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI2_QUP_CLK>, + <&gcc GSBI2_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + gsbi3: gsbi@16200000 { compatible = "qcom,gsbi-v1.0.0"; reg = <0x16200000 0x100>; @@ -600,6 +666,36 @@ }; }; + gsbi7: gsbi@16600000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16600000 0x100>; + ranges; + cell-index = <7>; + clocks = <&gcc GSBI7_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + + status = "disabled"; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16680000 0x1000>; + pinctrl-0 = <&i2c7_default_state>; + pinctrl-1 = <&i2c7_sleep_state>; + pinctrl-names = "default", "sleep"; + interrupts = ; + clocks = <&gcc GSBI7_QUP_CLK>, + <&gcc GSBI7_H_CLK>; + clock-names = "core", + "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + gsbi8: gsbi@1a000000 { compatible = "qcom,gsbi-v1.0.0"; reg = <0x1a000000 0x100>; From 72c6158e17cd3ef2069423ae70a24b955b1c0b72 Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Mon, 24 Nov 2025 15:35:23 -0800 Subject: [PATCH 657/757] ARM: dts: qcom: msm8960: expressatt: Add Light/Proximity Sensor Currently the Proximity Sensor doesn't work, but light sensor does. Left the proximity sensor as a TODO for later. Reviewed-by: Konrad Dybcio Signed-off-by: Rudraksha Gupta Link: https://lore.kernel.org/r/20251124-expressatt_nfc_accel_magn_light-v4-2-9c5686ad67e2@gmail.com Signed-off-by: Bjorn Andersson --- .../qcom/qcom-msm8960-samsung-expressatt.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index 5ee919dce75b..8d75ebd7976c 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -54,6 +54,31 @@ }; }; +&gsbi2 { + qcom,mode = ; + + status = "okay"; +}; + +&gsbi2_i2c { + status = "okay"; + + light-sensor@39 { + compatible = "amstaos,tmd2772"; + reg = <0x39>; + interrupts-extended = <&pm8921_gpio 6 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8921_l9>; + vddio-supply = <&pm8921_lvs4>; + + /* TODO: Proximity doesn't work */ + amstaos,proximity-diodes = <0>; + led-max-microamp = <100000>; + + pinctrl-0 = <&prox_sensor_int>; + pinctrl-names = "default"; + }; +}; + &gsbi5 { qcom,mode = ; status = "okay"; @@ -163,6 +188,15 @@ interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; }; +&pm8921_gpio { + prox_sensor_int: prox-sensor-int-state { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-disable; + }; +}; + &rpm { regulators { compatible = "qcom,rpm-pm8921-regulators"; From 7f07c27808e68af92cbf6d352f675248c3ea7cab Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Mon, 24 Nov 2025 15:35:24 -0800 Subject: [PATCH 658/757] ARM: dts: qcom: msm8960: expressatt: Add NFC Add pn544 NFC chip Reviewed-by: Konrad Dybcio Signed-off-by: Rudraksha Gupta Link: https://lore.kernel.org/r/20251124-expressatt_nfc_accel_magn_light-v4-3-9c5686ad67e2@gmail.com Signed-off-by: Bjorn Andersson --- .../qcom/qcom-msm8960-samsung-expressatt.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index 8d75ebd7976c..4f9b59db7bc3 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -182,6 +182,22 @@ bias-disable; drive-strength = <2>; }; + + nfc_default: nfc-default-state { + irq-pins { + pins = "gpio106"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + firmware-pins { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; }; &pm8921 { @@ -195,6 +211,14 @@ input-enable; bias-disable; }; + + nfc_enable: nfc-enable-state { + pins = "gpio21"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + power-source = ; + }; }; &rpm { @@ -442,3 +466,24 @@ dr_mode = "otg"; status = "okay"; }; + +&gsbi7 { + qcom,mode = ; + + status = "okay"; +}; + +&gsbi7_i2c { + status = "okay"; + + nfc@2b { + compatible = "nxp,pn544-i2c"; + reg = <0x2b>; + interrupts-extended = <&tlmm 106 IRQ_TYPE_EDGE_RISING>; + enable-gpios = <&pm8921_gpio 21 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default &nfc_enable>; + pinctrl-names = "default"; + }; +}; From 3649a120a7106aca89a4eddbddbc2e5a85aa64f9 Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Mon, 24 Nov 2025 15:35:25 -0800 Subject: [PATCH 659/757] ARM: dts: qcom: msm8960: expressatt: Add Magnetometer Add the Yamaha magnetometer. Mount Matrix is left as a TODO. Reviewed-by: Konrad Dybcio Signed-off-by: Rudraksha Gupta Link: https://lore.kernel.org/r/20251124-expressatt_nfc_accel_magn_light-v4-4-9c5686ad67e2@gmail.com Signed-off-by: Bjorn Andersson --- .../qcom/qcom-msm8960-samsung-expressatt.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index 4f9b59db7bc3..d32461fc58e9 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -487,3 +487,22 @@ pinctrl-names = "default"; }; }; + +&gsbi12 { + qcom,mode = ; + + status = "okay"; +}; + +&gsbi12_i2c { + status = "okay"; + + magnetometer@2e { + compatible = "yamaha,yas532"; + reg = <0x2e>; + vdd-supply = <&pm8921_l9>; + iovdd-supply = <&pm8921_lvs4>; + + /* TODO: Figure out Mount Matrix */ + }; +}; From 7f45d77240f9fc9948ba4d9c4eec3b97c3e2c51d Mon Sep 17 00:00:00 2001 From: Rudraksha Gupta Date: Mon, 24 Nov 2025 15:35:27 -0800 Subject: [PATCH 660/757] ARM: dts: qcom: msm8960: expressatt: Add Accelerometer Add the Bosch Accelerometer. Reviewed-by: Konrad Dybcio Signed-off-by: Rudraksha Gupta Link: https://lore.kernel.org/r/20251124-expressatt_nfc_accel_magn_light-v4-6-9c5686ad67e2@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts index d32461fc58e9..5a39abd6f3ce 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8960-samsung-expressatt.dts @@ -497,6 +497,17 @@ &gsbi12_i2c { status = "okay"; + accelerometer@18 { + compatible = "bosch,bma254"; + reg = <0x18>; + vdd-supply = <&pm8921_l9>; + vddio-supply = <&pm8921_lvs4>; + + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + magnetometer@2e { compatible = "yamaha,yas532"; reg = <0x2e>; From 6609c1976e64b6ce31fc2de11136dd7703372f20 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 24 Dec 2025 12:45:20 +0200 Subject: [PATCH 661/757] dt-bindings: watchdog: Document X1E80100 compatible Document the compatible for the X1E80100 platform to the Qualcomm watchdog binding. The HW implementation is compatible with the KPSS WDT. Acked-by: Rob Herring (Arm) Reviewed-by: Guenter Roeck Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20251224-arm64-dts-qcom-x1e80100-el2-add-apss-wdt-v3-1-1801c55d2883@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 54f5311ed016..f2c4bc900e5f 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -43,6 +43,7 @@ properties: - qcom,apss-wdt-sm6350 - qcom,apss-wdt-sm8150 - qcom,apss-wdt-sm8250 + - qcom,apss-wdt-x1e80100 - const: qcom,kpss-wdt - const: qcom,kpss-wdt deprecated: true From 4da4883613f62d4d60ada443d09ac36644f27d8a Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 24 Dec 2025 12:45:21 +0200 Subject: [PATCH 662/757] arm64: dts: qcom: hamoa: Add the APSS watchdog The watchdog support in EL1 is SBSA compliant, handled by Gunyah hypervisor, but in EL2. the watchdog is an instance of the APSS WDT HW block, same as older platforms. So describe the APSS WDT node and mark it as reserved, as it will only be enabled in EL2 overlay. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20251224-arm64-dts-qcom-x1e80100-el2-add-apss-wdt-v3-2-1801c55d2883@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index 01434f8a5300..db65c392e618 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -8360,6 +8360,14 @@ }; }; + apss_watchdog: watchdog@17410000 { + compatible = "qcom,apss-wdt-x1e80100", "qcom,kpss-wdt"; + reg = <0x0 0x17410000 0x0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + status = "reserved"; /* Reserved by Gunyah */ + }; + cpucp_mbox: mailbox@17430000 { compatible = "qcom,x1e80100-cpucp-mbox"; reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>; From f010e0b997035d82586e32e3427d88ef76edb3cb Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 24 Dec 2025 12:45:22 +0200 Subject: [PATCH 663/757] arm64: dts: qcom: x1-el2: Enable the APSS watchdog In EL2, the APSS watchdog is available. So enable it in the overlay. Reviewed-by: Dmitry Baryshkov Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251224-arm64-dts-qcom-x1e80100-el2-add-apss-wdt-v3-3-1801c55d2883@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/x1-el2.dtso | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-el2.dtso b/arch/arm64/boot/dts/qcom/x1-el2.dtso index 2d1c9151cf1b..175679be01eb 100644 --- a/arch/arm64/boot/dts/qcom/x1-el2.dtso +++ b/arch/arm64/boot/dts/qcom/x1-el2.dtso @@ -7,6 +7,10 @@ /dts-v1/; /plugin/; +&apss_watchdog { + status = "okay"; +}; + /* We can't and don't need to use zap shader in EL2 as linux can zap the gpu on it's own. */ &gpu_zap_shader { status = "disabled"; From dda4bdd325326dd67ae4401f4f3d35b9cf781e3f Mon Sep 17 00:00:00 2001 From: Viken Dadhaniya Date: Tue, 11 Nov 2025 22:33:50 +0530 Subject: [PATCH 664/757] arm64: dts: qcom: talos: Drop opp-shared from QUP OPP table QUP devices are currently marked with opp-shared in their OPP table, causing the kernel to treat them as part of a shared OPP domain. This leads to the qcom_geni_serial driver failing to probe with error -EBUSY (-16). Remove the opp-shared property to ensure the OPP framework treats the QUP OPP table as device-specific, allowing the serial driver to probe successfully Fixes: f6746dc9e379 ("arm64: dts: qcom: qcs615: Add QUPv3 configuration") Signed-off-by: Viken Dadhaniya Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251111170350.525832-1-viken.dadhaniya@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/talos.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index d956c91c7cc8..88980d8c3ee3 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -532,7 +532,6 @@ qup_opp_table: opp-table-qup { compatible = "operating-points-v2"; - opp-shared; opp-75000000 { opp-hz = /bits/ 64 <75000000>; From ebd1eb365caef3c815cb8a041d300dfe4263faea Mon Sep 17 00:00:00 2001 From: Jie Gan Date: Thu, 20 Nov 2025 21:48:54 +0800 Subject: [PATCH 665/757] arm64: qcom: dts: sm8750: add coresight nodes Add CoreSight DT nodes for AOSS, QDSS, CDSP, and Modem blocks to enable the STM and TPDM sources to route trace data to the ETF for debugging. Reviewed-by: Abel Vesa Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251120-add-coresight-nodes-for-pakala-v3-1-03bb7651bc90@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 980 +++++++++++++++++++++++++++ 1 file changed, 980 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index a76bf5193a70..51fd1d05503c 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3505,6 +3505,947 @@ #reset-cells = <1>; }; + stm@10002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x0 0x10002000 0x0 0x1000>, + <0x0 0x37280000 0x0 0x180000>; + reg-names = "stm-base", + "stm-stimulus-base"; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in7>; + }; + }; + }; + }; + + tpda@10004000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10004000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + tpda_qdss_in1: endpoint { + remote-endpoint = <&tpdm_spdm_out>; + }; + }; + + }; + + out-ports { + port { + tpda_qdss_out: endpoint { + remote-endpoint = <&funnel_in0_in6>; + }; + }; + }; + }; + + tpdm@1000f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1000f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_spdm_out: endpoint { + remote-endpoint = <&tpda_qdss_in1>; + }; + }; + }; + }; + + funnel@10041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10041000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + funnel_in0_in0: endpoint { + remote-endpoint = <&tn_ag_out>; + }; + }; + + port@6 { + reg = <6>; + + funnel_in0_in6: endpoint { + remote-endpoint = <&tpda_qdss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_in0_in7: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&funnel_aoss_in7>; + }; + }; + }; + }; + + tpdm@10800000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10800000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_modem0_out: endpoint { + remote-endpoint = <&tpda_modem_in0>; + }; + }; + }; + }; + + tpda@10803000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10803000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_modem_in0: endpoint { + remote-endpoint = <&tpdm_modem0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_modem_in1: endpoint { + remote-endpoint = <&tpdm_modem1_out>; + }; + }; + }; + + out-ports { + port { + tpda_modem_out: endpoint { + remote-endpoint = <&funnel_modem_dl_in0>; + }; + }; + }; + }; + + funnel@10804000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10804000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_modem_dl_in0: endpoint { + remote-endpoint = <&tpda_modem_out>; + }; + }; + }; + + out-ports { + port { + funnel_modem_dl_out: endpoint { + remote-endpoint = <&tn_ag_in13>; + }; + }; + }; + }; + + cti@1080b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x1080b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@1082c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1082c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_gcc_out: endpoint { + remote-endpoint = <&tn_ag_in17>; + }; + }; + }; + }; + + tpdm@10841000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10841000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_prng_out: endpoint { + remote-endpoint = <&tn_ag_in18>; + }; + }; + }; + }; + + tpdm@1084e000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1084e000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_bcv_out: endpoint { + remote-endpoint = <&tpda_mm_in0>; + }; + }; + }; + }; + + tpdm@1084f000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x1084f000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <32>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_lmh_out: endpoint { + remote-endpoint = <&tpda_mm_in1>; + }; + }; + }; + }; + + tpdm@10850000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10850000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_mm_dpm_out: endpoint { + remote-endpoint = <&tpda_mm_in2>; + }; + }; + }; + }; + + tpda@10851000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10851000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_mm_in0: endpoint { + remote-endpoint = <&tpdm_mm_bcv_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_mm_in1: endpoint { + remote-endpoint = <&tpdm_mm_lmh_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_mm_in2: endpoint { + remote-endpoint = <&tpdm_mm_dpm_out>; + }; + }; + }; + + out-ports { + port { + tpda_mm_out: endpoint { + remote-endpoint = <&tn_ag_in4>; + }; + }; + }; + }; + + tpdm@10980000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10980000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_cdsp_out: endpoint { + remote-endpoint = <&tpda_cdsp_in0>; + }; + }; + }; + }; + + tpda@10986000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10986000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_cdsp_in0: endpoint { + remote-endpoint = <&tpdm_cdsp_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_cdsp_in1: endpoint { + remote-endpoint = <&tpdm_cdsp_llm_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_cdsp_in2: endpoint { + remote-endpoint = <&tpdm_cdsp_llm2_out>; + }; + }; + }; + + out-ports { + port { + tpda_cdsp_out: endpoint { + remote-endpoint = <&funnel_cdsp_in0>; + }; + }; + }; + }; + + funnel@10987000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10987000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + funnel_cdsp_in0: endpoint { + remote-endpoint = <&tpda_cdsp_out>; + }; + }; + }; + + out-ports { + port { + funnel_cdsp_out: endpoint { + remote-endpoint = <&tn_ag_in16>; + }; + }; + }; + }; + + cti@1098b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0 0x1098b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + }; + + tpdm@109a3000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a3000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_pmu_out: endpoint { + remote-endpoint = <&tn_ag_in29>; + }; + }; + }; + }; + + tpdm@109a4000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a4000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_ipcc_cmb_out: endpoint { + remote-endpoint = <&tn_ag_in28>; + }; + }; + }; + }; + + tpdm@109a5000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a5000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_dl_mm_out: endpoint { + remote-endpoint = <&tn_ag_in25>; + }; + }; + }; + }; + + tpdm@109a6000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a6000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_north_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in26>; + }; + }; + }; + }; + + tpdm@109a7000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a7000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_south_dsb_out: endpoint { + remote-endpoint = <&tn_ag_in27>; + }; + }; + }; + }; + + tpdm@109a8000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a8000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb0_out: endpoint { + remote-endpoint = <&tn_ag_in30>; + }; + }; + }; + }; + + tpdm@109a9000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109a9000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb1_out: endpoint { + remote-endpoint = <&tn_ag_in31>; + }; + }; + }; + }; + + tpdm@109aa000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109aa000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_rdpm_cmb2_out: endpoint { + remote-endpoint = <&tn_ag_in32>; + }; + }; + }; + }; + + tn@109ab000 { + compatible = "qcom,coresight-tnoc", "arm,primecell"; + reg = <0x0 0x109ab000 0x0 0x4200>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + + tn_ag_in4: endpoint { + remote-endpoint = <&tpda_mm_out>; + }; + }; + + port@d { + reg = <0xd>; + + tn_ag_in13: endpoint { + remote-endpoint = <&funnel_modem_dl_out>; + }; + }; + + port@10 { + reg = <0x10>; + + tn_ag_in16: endpoint { + remote-endpoint = <&funnel_cdsp_out>; + }; + }; + + port@11 { + reg = <0x11>; + + tn_ag_in17: endpoint { + remote-endpoint = <&tpdm_gcc_out>; + }; + }; + + port@12 { + reg = <0x12>; + + tn_ag_in18: endpoint { + remote-endpoint = <&tpdm_prng_out>; + }; + }; + + port@13 { + reg = <0x13>; + + tn_ag_in19: endpoint { + remote-endpoint = <&tpdm_qm_out>; + }; + }; + + port@19 { + reg = <0x19>; + + tn_ag_in25: endpoint { + remote-endpoint = <&tpdm_dl_mm_out>; + }; + }; + + port@1a { + reg = <0x1a>; + + tn_ag_in26: endpoint { + remote-endpoint = <&tpdm_north_dsb_out>; + }; + }; + + port@1b { + reg = <0x1b>; + + tn_ag_in27: endpoint { + remote-endpoint = <&tpdm_south_dsb_out>; + }; + }; + + port@1c { + reg = <0x1c>; + + tn_ag_in28: endpoint { + remote-endpoint = <&tpdm_ipcc_cmb_out>; + }; + }; + + port@1d { + reg = <0x1d>; + + tn_ag_in29: endpoint { + remote-endpoint = <&tpdm_pmu_out>; + }; + }; + + port@1e { + reg = <0x1e>; + + tn_ag_in30: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb0_out>; + }; + }; + + port@1f { + reg = <0x1f>; + + tn_ag_in31: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb1_out>; + }; + }; + + port@20 { + reg = <0x20>; + + tn_ag_in32: endpoint { + remote-endpoint = <&tpdm_rdpm_cmb2_out>; + }; + }; + }; + + out-ports { + port { + tn_ag_out: endpoint { + remote-endpoint = <&funnel_in0_in0>; + }; + }; + }; + }; + + tpdm@109d0000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x109d0000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_qm_out: endpoint { + remote-endpoint = <&tn_ag_in19>; + }; + }; + }; + }; + + funnel@10b04000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x0 0x10b04000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@6 { + reg = <6>; + + funnel_aoss_in6: endpoint { + remote-endpoint = <&tpda_aoss_out>; + }; + }; + + port@7 { + reg = <7>; + + funnel_aoss_in7: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + }; + + out-ports { + port { + funnel_aoss_out: endpoint { + remote-endpoint = <&tmc_etf_in>; + }; + }; + }; + }; + + tmc@10b05000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x0 0x10b05000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + port { + tmc_etf_in: endpoint { + remote-endpoint = <&funnel_aoss_out>; + }; + }; + }; + }; + + tpda@10b08000 { + compatible = "qcom,coresight-tpda", "arm,primecell"; + reg = <0x0 0x10b08000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpda_aoss_in0: endpoint { + remote-endpoint = <&tpdm_swao_prio0_out>; + }; + }; + + port@1 { + reg = <1>; + + tpda_aoss_in1: endpoint { + remote-endpoint = <&tpdm_swao_prio1_out>; + }; + }; + + port@2 { + reg = <2>; + + tpda_aoss_in2: endpoint { + remote-endpoint = <&tpdm_swao_prio2_out>; + }; + }; + + port@3 { + reg = <3>; + + tpda_aoss_in3: endpoint { + remote-endpoint = <&tpdm_swao_prio3_out>; + }; + }; + + port@4 { + reg = <4>; + + tpda_aoss_in4: endpoint { + remote-endpoint =<&tpdm_swao_out>; + }; + }; + }; + + out-ports { + port { + tpda_aoss_out: endpoint { + remote-endpoint = <&funnel_aoss_in6>; + }; + }; + }; + }; + + tpdm@10b09000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b09000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio0_out: endpoint { + remote-endpoint = <&tpda_aoss_in0>; + }; + }; + }; + }; + + tpdm@10b0a000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0a000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio1_out: endpoint { + remote-endpoint = <&tpda_aoss_in1>; + }; + }; + }; + }; + + tpdm@10b0b000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0b000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio2_out: endpoint { + remote-endpoint = <&tpda_aoss_in2>; + }; + }; + }; + }; + + tpdm@10b0c000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0c000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,cmb-element-bits = <64>; + qcom,cmb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_prio3_out: endpoint { + remote-endpoint = <&tpda_aoss_in3>; + }; + }; + }; + }; + + tpdm@10b0d000 { + compatible = "qcom,coresight-tpdm", "arm,primecell"; + reg = <0x0 0x10b0d000 0x0 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb_pclk"; + + qcom,dsb-element-bits = <32>; + qcom,dsb-msrs-num = <32>; + + out-ports { + port { + tpdm_swao_out: endpoint { + remote-endpoint = <&tpda_aoss_in4>; + }; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0 0x15000000 0x0 0x100000>; @@ -4457,4 +5398,43 @@ , ; }; + + tpdm-cdsp-llm { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm_out: endpoint { + remote-endpoint = <&tpda_cdsp_in1>; + }; + }; + }; + }; + + tpdm-cdsp-llm2 { + compatible = "qcom,coresight-static-tpdm"; + qcom,cmb-element-bits = <32>; + + out-ports { + port { + tpdm_cdsp_llm2_out: endpoint { + remote-endpoint = <&tpda_cdsp_in2>; + }; + }; + }; + }; + + tpdm-modem1 { + compatible = "qcom,coresight-static-tpdm"; + qcom,dsb-element-bits = <32>; + + out-ports { + port { + tpdm_modem1_out: endpoint { + remote-endpoint = <&tpda_modem_in1>; + }; + }; + }; + }; }; From 5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 13 Jan 2026 10:38:26 +0800 Subject: [PATCH 666/757] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi As we have a separate CPU dtsi file, move the PLIC and CLINT node to the CPU dtsi file. This will make the sg2042.dtsi focus on peripheral devices, and make the CPU dtsi force CPU related devices. Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 ------------------- 2 files changed, 305 insertions(+), 303 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 94a4b71acad3..509488eee432 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -2189,4 +2189,309 @@ cache-unified; }; }; + + soc { + intc: interrupt-controller@7090000000 { + compatible = "sophgo,sg2042-plic", "thead,c900-plic"; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x00000070 0x90000000 0x00000000 0x04000000>; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>, + <&cpu8_intc 11>, <&cpu8_intc 9>, + <&cpu9_intc 11>, <&cpu9_intc 9>, + <&cpu10_intc 11>, <&cpu10_intc 9>, + <&cpu11_intc 11>, <&cpu11_intc 9>, + <&cpu12_intc 11>, <&cpu12_intc 9>, + <&cpu13_intc 11>, <&cpu13_intc 9>, + <&cpu14_intc 11>, <&cpu14_intc 9>, + <&cpu15_intc 11>, <&cpu15_intc 9>, + <&cpu16_intc 11>, <&cpu16_intc 9>, + <&cpu17_intc 11>, <&cpu17_intc 9>, + <&cpu18_intc 11>, <&cpu18_intc 9>, + <&cpu19_intc 11>, <&cpu19_intc 9>, + <&cpu20_intc 11>, <&cpu20_intc 9>, + <&cpu21_intc 11>, <&cpu21_intc 9>, + <&cpu22_intc 11>, <&cpu22_intc 9>, + <&cpu23_intc 11>, <&cpu23_intc 9>, + <&cpu24_intc 11>, <&cpu24_intc 9>, + <&cpu25_intc 11>, <&cpu25_intc 9>, + <&cpu26_intc 11>, <&cpu26_intc 9>, + <&cpu27_intc 11>, <&cpu27_intc 9>, + <&cpu28_intc 11>, <&cpu28_intc 9>, + <&cpu29_intc 11>, <&cpu29_intc 9>, + <&cpu30_intc 11>, <&cpu30_intc 9>, + <&cpu31_intc 11>, <&cpu31_intc 9>, + <&cpu32_intc 11>, <&cpu32_intc 9>, + <&cpu33_intc 11>, <&cpu33_intc 9>, + <&cpu34_intc 11>, <&cpu34_intc 9>, + <&cpu35_intc 11>, <&cpu35_intc 9>, + <&cpu36_intc 11>, <&cpu36_intc 9>, + <&cpu37_intc 11>, <&cpu37_intc 9>, + <&cpu38_intc 11>, <&cpu38_intc 9>, + <&cpu39_intc 11>, <&cpu39_intc 9>, + <&cpu40_intc 11>, <&cpu40_intc 9>, + <&cpu41_intc 11>, <&cpu41_intc 9>, + <&cpu42_intc 11>, <&cpu42_intc 9>, + <&cpu43_intc 11>, <&cpu43_intc 9>, + <&cpu44_intc 11>, <&cpu44_intc 9>, + <&cpu45_intc 11>, <&cpu45_intc 9>, + <&cpu46_intc 11>, <&cpu46_intc 9>, + <&cpu47_intc 11>, <&cpu47_intc 9>, + <&cpu48_intc 11>, <&cpu48_intc 9>, + <&cpu49_intc 11>, <&cpu49_intc 9>, + <&cpu50_intc 11>, <&cpu50_intc 9>, + <&cpu51_intc 11>, <&cpu51_intc 9>, + <&cpu52_intc 11>, <&cpu52_intc 9>, + <&cpu53_intc 11>, <&cpu53_intc 9>, + <&cpu54_intc 11>, <&cpu54_intc 9>, + <&cpu55_intc 11>, <&cpu55_intc 9>, + <&cpu56_intc 11>, <&cpu56_intc 9>, + <&cpu57_intc 11>, <&cpu57_intc 9>, + <&cpu58_intc 11>, <&cpu58_intc 9>, + <&cpu59_intc 11>, <&cpu59_intc 9>, + <&cpu60_intc 11>, <&cpu60_intc 9>, + <&cpu61_intc 11>, <&cpu61_intc 9>, + <&cpu62_intc 11>, <&cpu62_intc 9>, + <&cpu63_intc 11>, <&cpu63_intc 9>; + riscv,ndev = <224>; + }; + + clint_mswi: interrupt-controller@7094000000 { + compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; + reg = <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended = <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>, + <&cpu4_intc 3>, + <&cpu5_intc 3>, + <&cpu6_intc 3>, + <&cpu7_intc 3>, + <&cpu8_intc 3>, + <&cpu9_intc 3>, + <&cpu10_intc 3>, + <&cpu11_intc 3>, + <&cpu12_intc 3>, + <&cpu13_intc 3>, + <&cpu14_intc 3>, + <&cpu15_intc 3>, + <&cpu16_intc 3>, + <&cpu17_intc 3>, + <&cpu18_intc 3>, + <&cpu19_intc 3>, + <&cpu20_intc 3>, + <&cpu21_intc 3>, + <&cpu22_intc 3>, + <&cpu23_intc 3>, + <&cpu24_intc 3>, + <&cpu25_intc 3>, + <&cpu26_intc 3>, + <&cpu27_intc 3>, + <&cpu28_intc 3>, + <&cpu29_intc 3>, + <&cpu30_intc 3>, + <&cpu31_intc 3>, + <&cpu32_intc 3>, + <&cpu33_intc 3>, + <&cpu34_intc 3>, + <&cpu35_intc 3>, + <&cpu36_intc 3>, + <&cpu37_intc 3>, + <&cpu38_intc 3>, + <&cpu39_intc 3>, + <&cpu40_intc 3>, + <&cpu41_intc 3>, + <&cpu42_intc 3>, + <&cpu43_intc 3>, + <&cpu44_intc 3>, + <&cpu45_intc 3>, + <&cpu46_intc 3>, + <&cpu47_intc 3>, + <&cpu48_intc 3>, + <&cpu49_intc 3>, + <&cpu50_intc 3>, + <&cpu51_intc 3>, + <&cpu52_intc 3>, + <&cpu53_intc 3>, + <&cpu54_intc 3>, + <&cpu55_intc 3>, + <&cpu56_intc 3>, + <&cpu57_intc 3>, + <&cpu58_intc 3>, + <&cpu59_intc 3>, + <&cpu60_intc 3>, + <&cpu61_intc 3>, + <&cpu62_intc 3>, + <&cpu63_intc 3>; + }; + + clint_mtimer0: timer@70ac004000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + clint_mtimer1: timer@70ac014000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu4_intc 7>, + <&cpu5_intc 7>, + <&cpu6_intc 7>, + <&cpu7_intc 7>; + }; + + clint_mtimer2: timer@70ac024000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu8_intc 7>, + <&cpu9_intc 7>, + <&cpu10_intc 7>, + <&cpu11_intc 7>; + }; + + clint_mtimer3: timer@70ac034000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu12_intc 7>, + <&cpu13_intc 7>, + <&cpu14_intc 7>, + <&cpu15_intc 7>; + }; + + clint_mtimer4: timer@70ac044000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu16_intc 7>, + <&cpu17_intc 7>, + <&cpu18_intc 7>, + <&cpu19_intc 7>; + }; + + clint_mtimer5: timer@70ac054000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu20_intc 7>, + <&cpu21_intc 7>, + <&cpu22_intc 7>, + <&cpu23_intc 7>; + }; + + clint_mtimer6: timer@70ac064000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu24_intc 7>, + <&cpu25_intc 7>, + <&cpu26_intc 7>, + <&cpu27_intc 7>; + }; + + clint_mtimer7: timer@70ac074000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu28_intc 7>, + <&cpu29_intc 7>, + <&cpu30_intc 7>, + <&cpu31_intc 7>; + }; + + clint_mtimer8: timer@70ac084000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu32_intc 7>, + <&cpu33_intc 7>, + <&cpu34_intc 7>, + <&cpu35_intc 7>; + }; + + clint_mtimer9: timer@70ac094000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu36_intc 7>, + <&cpu37_intc 7>, + <&cpu38_intc 7>, + <&cpu39_intc 7>; + }; + + clint_mtimer10: timer@70ac0a4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu40_intc 7>, + <&cpu41_intc 7>, + <&cpu42_intc 7>, + <&cpu43_intc 7>; + }; + + clint_mtimer11: timer@70ac0b4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu44_intc 7>, + <&cpu45_intc 7>, + <&cpu46_intc 7>, + <&cpu47_intc 7>; + }; + + clint_mtimer12: timer@70ac0c4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu48_intc 7>, + <&cpu49_intc 7>, + <&cpu50_intc 7>, + <&cpu51_intc 7>; + }; + + clint_mtimer13: timer@70ac0d4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu52_intc 7>, + <&cpu53_intc 7>, + <&cpu54_intc 7>, + <&cpu55_intc 7>; + }; + + clint_mtimer14: timer@70ac0e4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu56_intc 7>, + <&cpu57_intc 7>, + <&cpu58_intc 7>, + <&cpu59_intc 7>; + }; + + clint_mtimer15: timer@70ac0f4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu60_intc 7>, + <&cpu61_intc 7>, + <&cpu62_intc 7>, + <&cpu63_intc 7>; + }; + }; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index ec99da39150f..e6891f95d479 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -352,309 +352,6 @@ status = "disabled"; }; - clint_mswi: interrupt-controller@7094000000 { - compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; - reg = <0x00000070 0x94000000 0x00000000 0x00004000>; - interrupts-extended = <&cpu0_intc 3>, - <&cpu1_intc 3>, - <&cpu2_intc 3>, - <&cpu3_intc 3>, - <&cpu4_intc 3>, - <&cpu5_intc 3>, - <&cpu6_intc 3>, - <&cpu7_intc 3>, - <&cpu8_intc 3>, - <&cpu9_intc 3>, - <&cpu10_intc 3>, - <&cpu11_intc 3>, - <&cpu12_intc 3>, - <&cpu13_intc 3>, - <&cpu14_intc 3>, - <&cpu15_intc 3>, - <&cpu16_intc 3>, - <&cpu17_intc 3>, - <&cpu18_intc 3>, - <&cpu19_intc 3>, - <&cpu20_intc 3>, - <&cpu21_intc 3>, - <&cpu22_intc 3>, - <&cpu23_intc 3>, - <&cpu24_intc 3>, - <&cpu25_intc 3>, - <&cpu26_intc 3>, - <&cpu27_intc 3>, - <&cpu28_intc 3>, - <&cpu29_intc 3>, - <&cpu30_intc 3>, - <&cpu31_intc 3>, - <&cpu32_intc 3>, - <&cpu33_intc 3>, - <&cpu34_intc 3>, - <&cpu35_intc 3>, - <&cpu36_intc 3>, - <&cpu37_intc 3>, - <&cpu38_intc 3>, - <&cpu39_intc 3>, - <&cpu40_intc 3>, - <&cpu41_intc 3>, - <&cpu42_intc 3>, - <&cpu43_intc 3>, - <&cpu44_intc 3>, - <&cpu45_intc 3>, - <&cpu46_intc 3>, - <&cpu47_intc 3>, - <&cpu48_intc 3>, - <&cpu49_intc 3>, - <&cpu50_intc 3>, - <&cpu51_intc 3>, - <&cpu52_intc 3>, - <&cpu53_intc 3>, - <&cpu54_intc 3>, - <&cpu55_intc 3>, - <&cpu56_intc 3>, - <&cpu57_intc 3>, - <&cpu58_intc 3>, - <&cpu59_intc 3>, - <&cpu60_intc 3>, - <&cpu61_intc 3>, - <&cpu62_intc 3>, - <&cpu63_intc 3>; - }; - - clint_mtimer0: timer@70ac004000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu0_intc 7>, - <&cpu1_intc 7>, - <&cpu2_intc 7>, - <&cpu3_intc 7>; - }; - - clint_mtimer1: timer@70ac014000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu4_intc 7>, - <&cpu5_intc 7>, - <&cpu6_intc 7>, - <&cpu7_intc 7>; - }; - - clint_mtimer2: timer@70ac024000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu8_intc 7>, - <&cpu9_intc 7>, - <&cpu10_intc 7>, - <&cpu11_intc 7>; - }; - - clint_mtimer3: timer@70ac034000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu12_intc 7>, - <&cpu13_intc 7>, - <&cpu14_intc 7>, - <&cpu15_intc 7>; - }; - - clint_mtimer4: timer@70ac044000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu16_intc 7>, - <&cpu17_intc 7>, - <&cpu18_intc 7>, - <&cpu19_intc 7>; - }; - - clint_mtimer5: timer@70ac054000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu20_intc 7>, - <&cpu21_intc 7>, - <&cpu22_intc 7>, - <&cpu23_intc 7>; - }; - - clint_mtimer6: timer@70ac064000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu24_intc 7>, - <&cpu25_intc 7>, - <&cpu26_intc 7>, - <&cpu27_intc 7>; - }; - - clint_mtimer7: timer@70ac074000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu28_intc 7>, - <&cpu29_intc 7>, - <&cpu30_intc 7>, - <&cpu31_intc 7>; - }; - - clint_mtimer8: timer@70ac084000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu32_intc 7>, - <&cpu33_intc 7>, - <&cpu34_intc 7>, - <&cpu35_intc 7>; - }; - - clint_mtimer9: timer@70ac094000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu36_intc 7>, - <&cpu37_intc 7>, - <&cpu38_intc 7>, - <&cpu39_intc 7>; - }; - - clint_mtimer10: timer@70ac0a4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu40_intc 7>, - <&cpu41_intc 7>, - <&cpu42_intc 7>, - <&cpu43_intc 7>; - }; - - clint_mtimer11: timer@70ac0b4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu44_intc 7>, - <&cpu45_intc 7>, - <&cpu46_intc 7>, - <&cpu47_intc 7>; - }; - - clint_mtimer12: timer@70ac0c4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu48_intc 7>, - <&cpu49_intc 7>, - <&cpu50_intc 7>, - <&cpu51_intc 7>; - }; - - clint_mtimer13: timer@70ac0d4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu52_intc 7>, - <&cpu53_intc 7>, - <&cpu54_intc 7>, - <&cpu55_intc 7>; - }; - - clint_mtimer14: timer@70ac0e4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu56_intc 7>, - <&cpu57_intc 7>, - <&cpu58_intc 7>, - <&cpu59_intc 7>; - }; - - clint_mtimer15: timer@70ac0f4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu60_intc 7>, - <&cpu61_intc 7>, - <&cpu62_intc 7>, - <&cpu63_intc 7>; - }; - - intc: interrupt-controller@7090000000 { - compatible = "sophgo,sg2042-plic", "thead,c900-plic"; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x00000070 0x90000000 0x00000000 0x04000000>; - interrupt-controller; - interrupts-extended = - <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>, - <&cpu5_intc 11>, <&cpu5_intc 9>, - <&cpu6_intc 11>, <&cpu6_intc 9>, - <&cpu7_intc 11>, <&cpu7_intc 9>, - <&cpu8_intc 11>, <&cpu8_intc 9>, - <&cpu9_intc 11>, <&cpu9_intc 9>, - <&cpu10_intc 11>, <&cpu10_intc 9>, - <&cpu11_intc 11>, <&cpu11_intc 9>, - <&cpu12_intc 11>, <&cpu12_intc 9>, - <&cpu13_intc 11>, <&cpu13_intc 9>, - <&cpu14_intc 11>, <&cpu14_intc 9>, - <&cpu15_intc 11>, <&cpu15_intc 9>, - <&cpu16_intc 11>, <&cpu16_intc 9>, - <&cpu17_intc 11>, <&cpu17_intc 9>, - <&cpu18_intc 11>, <&cpu18_intc 9>, - <&cpu19_intc 11>, <&cpu19_intc 9>, - <&cpu20_intc 11>, <&cpu20_intc 9>, - <&cpu21_intc 11>, <&cpu21_intc 9>, - <&cpu22_intc 11>, <&cpu22_intc 9>, - <&cpu23_intc 11>, <&cpu23_intc 9>, - <&cpu24_intc 11>, <&cpu24_intc 9>, - <&cpu25_intc 11>, <&cpu25_intc 9>, - <&cpu26_intc 11>, <&cpu26_intc 9>, - <&cpu27_intc 11>, <&cpu27_intc 9>, - <&cpu28_intc 11>, <&cpu28_intc 9>, - <&cpu29_intc 11>, <&cpu29_intc 9>, - <&cpu30_intc 11>, <&cpu30_intc 9>, - <&cpu31_intc 11>, <&cpu31_intc 9>, - <&cpu32_intc 11>, <&cpu32_intc 9>, - <&cpu33_intc 11>, <&cpu33_intc 9>, - <&cpu34_intc 11>, <&cpu34_intc 9>, - <&cpu35_intc 11>, <&cpu35_intc 9>, - <&cpu36_intc 11>, <&cpu36_intc 9>, - <&cpu37_intc 11>, <&cpu37_intc 9>, - <&cpu38_intc 11>, <&cpu38_intc 9>, - <&cpu39_intc 11>, <&cpu39_intc 9>, - <&cpu40_intc 11>, <&cpu40_intc 9>, - <&cpu41_intc 11>, <&cpu41_intc 9>, - <&cpu42_intc 11>, <&cpu42_intc 9>, - <&cpu43_intc 11>, <&cpu43_intc 9>, - <&cpu44_intc 11>, <&cpu44_intc 9>, - <&cpu45_intc 11>, <&cpu45_intc 9>, - <&cpu46_intc 11>, <&cpu46_intc 9>, - <&cpu47_intc 11>, <&cpu47_intc 9>, - <&cpu48_intc 11>, <&cpu48_intc 9>, - <&cpu49_intc 11>, <&cpu49_intc 9>, - <&cpu50_intc 11>, <&cpu50_intc 9>, - <&cpu51_intc 11>, <&cpu51_intc 9>, - <&cpu52_intc 11>, <&cpu52_intc 9>, - <&cpu53_intc 11>, <&cpu53_intc 9>, - <&cpu54_intc 11>, <&cpu54_intc 9>, - <&cpu55_intc 11>, <&cpu55_intc 9>, - <&cpu56_intc 11>, <&cpu56_intc 9>, - <&cpu57_intc 11>, <&cpu57_intc 9>, - <&cpu58_intc 11>, <&cpu58_intc 9>, - <&cpu59_intc 11>, <&cpu59_intc 9>, - <&cpu60_intc 11>, <&cpu60_intc 9>, - <&cpu61_intc 11>, <&cpu61_intc 9>, - <&cpu62_intc 11>, <&cpu62_intc 9>, - <&cpu63_intc 11>, <&cpu63_intc 9>; - riscv,ndev = <224>; - }; - rstgen: reset-controller@7030013000 { compatible = "sophgo,sg2042-reset"; reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; From ebb87dd74c34a76e1e93041e9329cf9269be35ed Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 13 Jan 2026 10:38:27 +0800 Subject: [PATCH 667/757] riscv: dts: sophgo: fix the node order of SG2042 peripheral In sg2042.dtsi, some peripheral device node does not follow the address order. Reorder them in ascending order by address. Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++------------- 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index e6891f95d479..9fddf3f0b3b9 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -264,94 +264,6 @@ #clock-cells = <1>; }; - pcie_rc0: pcie@7060000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x60000000 0x0 0x00800000>, - <0x40 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, - <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, - <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc1: pcie@7060800000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x60800000 0x0 0x00800000>, - <0x44 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, - <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, - <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc2: pcie@7062000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x62000000 0x0 0x00800000>, - <0x48 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <2>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, - <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, - <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc3: pcie@7062800000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x62800000 0x0 0x00800000>, - <0x4c 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <3>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, - <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, - <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, - <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, - <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - rstgen: reset-controller@7030013000 { compatible = "sophgo,sg2042-reset"; reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; @@ -486,5 +398,93 @@ "timer"; status = "disabled"; }; + + pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; }; }; From f16ae81b80ca4e721f4c4ed1f28390115f7721eb Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:59 +0800 Subject: [PATCH 668/757] riscv: dts: sophgo: sg2044: Add "b" ISA extension "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update sg2044-cpus.dtsi to conform to this rule. Signed-off-by: Guodong Xu Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++---------- 1 file changed, 128 insertions(+), 128 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 523799a1a8b8..3135409c2149 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -24,10 +24,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -60,10 +60,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -96,10 +96,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -132,10 +132,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -168,10 +168,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -204,10 +204,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -240,10 +240,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -276,10 +276,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -312,10 +312,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -348,10 +348,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -384,10 +384,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -420,10 +420,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -456,10 +456,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -492,10 +492,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -528,10 +528,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -564,10 +564,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -600,10 +600,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -636,10 +636,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -672,10 +672,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -708,10 +708,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -744,10 +744,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -780,10 +780,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -816,10 +816,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -852,10 +852,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -888,10 +888,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -924,10 +924,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -960,10 +960,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -996,10 +996,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1032,10 +1032,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1068,10 +1068,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1104,10 +1104,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1140,10 +1140,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1176,10 +1176,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1212,10 +1212,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1248,10 +1248,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1284,10 +1284,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1320,10 +1320,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1356,10 +1356,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1392,10 +1392,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1428,10 +1428,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1464,10 +1464,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1500,10 +1500,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1536,10 +1536,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1572,10 +1572,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1608,10 +1608,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1644,10 +1644,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1680,10 +1680,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1716,10 +1716,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1752,10 +1752,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1788,10 +1788,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1824,10 +1824,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1860,10 +1860,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1896,10 +1896,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1932,10 +1932,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1968,10 +1968,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2004,10 +2004,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2040,10 +2040,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2076,10 +2076,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2112,10 +2112,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2148,10 +2148,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2184,10 +2184,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2220,10 +2220,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2256,10 +2256,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2292,10 +2292,10 @@ device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", From 1099b3b6ab01e481c5aaf6c74e9c8892c9636fe6 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Fri, 16 Jan 2026 10:36:11 +0800 Subject: [PATCH 669/757] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable eMMC storage Enable the on-board eMMC storage for Khadas VIM1S. The VIM1S features a 16GB eMMC 5.1 module. This patch adds the necessary regulators and the eMMC controller node. Signed-off-by: Nick Xie Reviewed-by: Martin Blumenstingl Link: https://patch.msgid.link/20260116023611.2033078-1-nick@khadas.com Signed-off-by: Neil Armstrong --- .../amlogic/meson-s4-s905y4-khadas-vim1s.dts | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts index 79ffc703a2e9..4a66c1bec965 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -38,6 +38,11 @@ }; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>; + }; + sdio_32k: sdio-32k { compatible = "pwm-clock"; #clock-cells = <0>; @@ -80,6 +85,24 @@ 3300000 0>; }; + vddao_3v3: regulator-vddao-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&main_5v>; + regulator-always-on; + }; + + vddio_ao1v8: regulator-vddio-ao1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + /* SY8120B1ABC DC/DC Regulator. */ vddcpu: regulator-vddcpu { compatible = "pwm-regulator"; @@ -136,6 +159,25 @@ }; }; +&emmc { + status = "okay"; + pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; +}; + ðmac { status = "okay"; phy-handle = <&internal_ephy>; From 436418ef5baa024b7b15dd730c36d651c6aaaf47 Mon Sep 17 00:00:00 2001 From: Eric Neulight Date: Fri, 16 Jan 2026 23:02:20 -0500 Subject: [PATCH 670/757] arm64: dts: amlogic: meson-sm1-odroid: Eliminate Odroid HC4 power glitches during boot. Fix issue with Odroid HC4 (and all meson-sm1-odroid) DTS that causes regulator power to momentarily glitch OFF-ON during boot. Add regulator-boot-on to all regulator-fixed and regulator-gpio entries that (1) define a gpio AND (2) define regulator-always-on. U-boot powers on devices necessary for boot then hands off the DTB to the kernel. During probe, linux drivers/regulator/fixed.c and gpio-regulator.c both first set the regulator control gpio (that U-boot already turned ON) to default OFF before then setting it to the defined (ON) state. This glitches the power to the affected devices, unless regulator-boot-on is specified with it. In fact, U-boot has the same behavior. So, during reboot, a power glitch can actually happen twice: once when U-boot reads the DTB and probes the gpio and again when the kernel reads the DTB and probes the gpio. Problem this fixes: On the Odroid HC4, power to the SATA ports glitches during boot and causes some HDDs to do emergency head retract, which should be avoided. On the HC4, power glitches to the SD card, USB, SATA, and HDMI interfaces during boot. These are all boot devices. A power glitch can potentially cause a problem for any sensitive devices during boot. NOTE: This is not limited to just the HC4, likely an issue with ALL DTS with regulator-fixed or regulator-gpio entries that (1) define a gpio AND (2) define regulator-always-on. All such entries should also include regulator-boot-on in order to avoid potential power glitches. At worst, adding regulator-boot-on in such cases is harmless because of regulator-always-on, and, at best, it eliminates detrimental power glitches during boot. So, this is best-practice. Fixes: 164147f094ec5d0fc2c2098a888f4b50cf3096a7 ("arm64: dts: meson-sm1-odroid-hc4: add regulators controlled by GPIOH_8") Fixes: 45d736ab17b44257e15e75e0dba364139fdb0983 ("arm64: dts: meson-sm1-odroid: add 5v regulator gpio") Fixes: 1f80a5cf74a60997b92d2cde772edec093bec4d9 ("arm64: dts: meson-sm1-odroid: add missing enable gpio and supply for tf_io regulator") Fixes: 88d537bc92ca035e2a9920b0abc750dd62146520 ("arm64: dts: meson: convert meson-sm1-odroid-c4 to dtsi") Signed-off-by: Eric Neulight Reviewed-by: Neil Armstrong Acked-by: Viacheslav Bocharov Tested-by: Ricardo Pardini # on Odroid-HC4 5V HDD Link: https://patch.msgid.link/20260116-odroid-hc4-dts-v1-1-459b601cd5cf@linuxdev.slmail.me [narmstrong: fixed subject prefix] Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index 0170139b8d32..3ece30a0a1ff 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -52,6 +52,7 @@ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; enable-active-high; + regulator-boot-on; regulator-always-on; }; @@ -65,6 +66,7 @@ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; enable-active-high; + regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index db9124779b87..e6f02d738a21 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -37,6 +37,7 @@ gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; enable-active-high; + regulator-boot-on; regulator-always-on; }; @@ -50,6 +51,7 @@ enable-gpios = <&gpio_ao GPIOE_2 GPIO_OPEN_DRAIN>; enable-active-high; + regulator-boot-on; regulator-always-on; gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>; @@ -81,6 +83,7 @@ regulator-name = "5V"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; regulator-always-on; vin-supply = <&main_12v>; gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>; From 2afef25cc448ada7c9a7771fbfe4087a9e1a6d03 Mon Sep 17 00:00:00 2001 From: Ricardo Pardini Date: Thu, 15 Jan 2026 18:52:46 +0100 Subject: [PATCH 671/757] arm64: dts: amlogic: add the type-c controller on Radxa Zero 2 The Radxa Zero2 has an FUSB302 controller on i2c3 at address 0x22 and INT# wired to GPIOA-13; include a minimal connector. Signed-off-by: Ricardo Pardini Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260115-arm64-dts-amlogic-radxa-zero2-additions-v2-1-948bb0479a45@pardini.net Signed-off-by: Neil Armstrong --- .../dts/amlogic/meson-g12b-radxa-zero2.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts index 0591331f61e5..50565851f3d8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-radxa-zero2.dts @@ -351,12 +351,46 @@ }; }; +/* Also exposed on the 40-pin header: SDA pin 3, SCL pin 5 */ +&i2c3 { + pinctrl-0 = <&i2c3_sda_a_pins>, <&i2c3_sck_a_pins>; + pinctrl-names = "default"; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + pinctrl-0 = <&fusb302_irq_pins>; + pinctrl-names = "default"; + interrupt-parent = <&gpio_intc>; + interrupts = <74 IRQ_TYPE_LEVEL_LOW>; + + vbus-supply = <&ao_5v>; + + connector { + compatible = "usb-c-connector"; + }; + }; +}; + &ir { status = "disabled"; pinctrl-0 = <&remote_input_ao_pins>; pinctrl-names = "default"; }; +&periphs_pinctrl { + fusb302_irq_pins: fusb302-irq { + mux { + groups = "GPIOA_13"; + function = "gpio_periphs"; + bias-pull-up; + output-disable; + }; + }; +}; + &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; From e89ae0ec2fb8c29f351dd2790574f3fc22599875 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 13 Nov 2025 16:13:53 +0100 Subject: [PATCH 672/757] ARM: dts: stm32: Update LED nodes for stm32 MCU boards Add function porperty for led nodes. Add LED color property for LED nodes. Reorder include dt-bindings. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-2-45090db9e2e5@foss.st.com Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-3-45090db9e2e5@foss.st.com Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-4-45090db9e2e5@foss.st.com Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-5-45090db9e2e5@foss.st.com Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-6-45090db9e2e5@foss.st.com Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-7-45090db9e2e5@foss.st.com Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-10-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32429i-eval.dts | 8 +++++++- arch/arm/boot/dts/st/stm32746g-eval.dts | 6 ++++++ arch/arm/boot/dts/st/stm32f429-disco.dts | 6 +++++- arch/arm/boot/dts/st/stm32f469-disco.dts | 6 ++++++ arch/arm/boot/dts/st/stm32f746-disco.dts | 3 +++ arch/arm/boot/dts/st/stm32f769-disco.dts | 5 +++++ arch/arm/boot/dts/st/stm32h747i-disco.dts | 6 ++++++ 7 files changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts index 6ce8d7e5565a..a138c0ac8e77 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -48,8 +48,9 @@ /dts-v1/; #include "stm32f429.dtsi" #include "stm32f429-pinctrl.dtsi" -#include #include +#include +#include #include / { @@ -85,16 +86,21 @@ leds { compatible = "gpio-leds"; led-green { + function = LED_FUNCTION_HEARTBEAT; + color = ; gpios = <&gpiog 6 1>; linux,default-trigger = "heartbeat"; }; led-orange { + color = ; gpios = <&gpiog 7 1>; }; led-red { + color = ; gpios = <&gpiog 10 1>; }; led-blue { + color = ; gpios = <&gpiog 12 1>; }; }; diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts index e9ac37b6eca0..78ceec4a9487 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -45,6 +45,7 @@ #include "stm32f746-pinctrl.dtsi" #include #include +#include / { model = "STMicroelectronics STM32746g-EVAL board"; @@ -67,16 +68,21 @@ leds { compatible = "gpio-leds"; led-green { + function = LED_FUNCTION_HEARTBEAT; + color = ; gpios = <&gpiof 10 1>; linux,default-trigger = "heartbeat"; }; led-orange { + color = ; gpios = <&stmfx_pinctrl 17 1>; }; led-red { + color = ; gpios = <&gpiob 7 1>; }; led-blue { + color = ; gpios = <&stmfx_pinctrl 19 1>; }; }; diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts index a3cb4aabdd5a..15f92842c8e1 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -48,9 +48,10 @@ /dts-v1/; #include "stm32f429.dtsi" #include "stm32f429-pinctrl.dtsi" +#include #include #include -#include +#include / { model = "STMicroelectronics STM32F429i-DISCO board"; @@ -73,9 +74,12 @@ leds { compatible = "gpio-leds"; led-red { + color = ; gpios = <&gpiog 14 0>; }; led-green { + function = LED_FUNCTION_HEARTBEAT; + color = ; gpios = <&gpiog 13 0>; linux,default-trigger = "heartbeat"; }; diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts index 8a4f8ddd083d..f43547ec436d 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -50,6 +50,7 @@ #include "stm32f469-pinctrl.dtsi" #include #include +#include / { model = "STMicroelectronics STM32F469i-DISCO board"; @@ -83,16 +84,21 @@ leds { compatible = "gpio-leds"; led-green { + function = LED_FUNCTION_HEARTBEAT; + color = ; gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; led-orange { + color = ; gpios = <&gpiod 4 GPIO_ACTIVE_LOW>; }; led-red { + color = ; gpios = <&gpiod 5 GPIO_ACTIVE_LOW>; }; led-blue { + color = ; gpios = <&gpiok 3 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index b57dbdce2f40..2e6086eea6ed 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -46,6 +46,7 @@ #include #include #include +#include / { model = "STMicroelectronics STM32F746-DISCO board"; @@ -81,6 +82,8 @@ leds { compatible = "gpio-leds"; led-usr { + function = LED_FUNCTION_HEARTBEAT; + color = ; gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 535cfdc4681c..97c276f81f9a 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -45,6 +45,7 @@ #include "stm32f769-pinctrl.dtsi" #include #include +#include / { model = "STMicroelectronics STM32F769-DISCO board"; @@ -80,13 +81,17 @@ leds { compatible = "gpio-leds"; led-usr2 { + function = LED_FUNCTION_HEARTBEAT; + color = ; gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; led-usr1 { + color = ; gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; led-usr3 { + color = ; gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts index 99f0255dae8e..bb6649a58bc1 100644 --- a/arch/arm/boot/dts/st/stm32h747i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts @@ -8,6 +8,7 @@ #include "stm32h7-pinctrl.dtsi" #include #include +#include / { model = "STMicroelectronics STM32H747i-Discovery board"; @@ -39,16 +40,21 @@ leds { compatible = "gpio-leds"; led-green { + function = LED_FUNCTION_HEARTBEAT; + color = ; gpios = <&gpioi 12 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; }; led-orange { + color = ; gpios = <&gpioi 13 GPIO_ACTIVE_LOW>; }; led-red { + color = ; gpios = <&gpioi 14 GPIO_ACTIVE_LOW>; }; led-blue { + color = ; gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; }; }; From f5f2fce8af2a7a8c5f6abd1ccee71998bcd83651 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 13 Nov 2025 16:13:59 +0100 Subject: [PATCH 673/757] ARM: dts: stm32: Add LED support for stm32h743i-disco Add gpio led support for LED green,orange,red and blue in stm32h743i-disco.dts. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-8-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32h743i-disco.dts | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts index 8451a54a9a08..f20266de4e7f 100644 --- a/arch/arm/boot/dts/st/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -43,6 +43,8 @@ /dts-v1/; #include "stm32h743.dtsi" #include "stm32h7-pinctrl.dtsi" +#include +#include / { model = "STMicroelectronics STM32H743i-Discovery board"; @@ -69,6 +71,31 @@ regulator-max-microvolt = <3300000>; regulator-always-on; }; + + leds { + compatible = "gpio-leds"; + led-green { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioi 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-orange { + color = ; + gpios = <&gpioi 13 GPIO_ACTIVE_LOW>; + }; + + led-red { + color = ; + gpios = <&gpioi 14 GPIO_ACTIVE_LOW>; + }; + + led-blue { + color = ; + gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; + }; + }; }; &clk_hse { From 4d33caf1f0b7a859661f00b8ff909fb7fbcc02d7 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 13 Nov 2025 16:14:00 +0100 Subject: [PATCH 674/757] ARM: dts: stm32: Add LED support for stm32h743i-eval Add green and red LEDs support for stm32h743-eval. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-9-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32h743i-eval.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts index 4b0ced27b80e..4b3e0c5a9009 100644 --- a/arch/arm/boot/dts/st/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -43,6 +43,8 @@ /dts-v1/; #include "stm32h743.dtsi" #include "stm32h7-pinctrl.dtsi" +#include +#include / { model = "STMicroelectronics STM32H743i-EVAL board"; @@ -62,6 +64,22 @@ serial0 = &usart1; }; + led { + compatible = "gpio-leds"; + led-green { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpiof 10 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led-red { + color = ; + gpios = <&gpioa 4 GPIO_ACTIVE_LOW>; + }; + }; + vdda: regulator-vdda { compatible = "regulator-fixed"; regulator-name = "vdda"; From 31f0d9a486a8c7361692fd5e9d77e187720a5ece Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 13 Nov 2025 16:14:02 +0100 Subject: [PATCH 675/757] ARM: dts: stm32: Add red LED for stm32mp135f-dk board Add LED red node for stm32mp135f-dk. This LED is used as status lLED in U-Boot. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-11-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index f894ee35b3db..2549cf604ca3 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -80,6 +80,12 @@ linux,default-trigger = "heartbeat"; default-state = "off"; }; + + led-red { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; }; panel_backlight: panel-backlight { From 7f2815c962039965b01de8e0c01dc6baa6726fbd Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 13 Nov 2025 16:14:03 +0100 Subject: [PATCH 676/757] ARM: dts: stm32: Add red LED for stm32mp157c-ed1 board Add led-red node for stm32mp157c-ed1. This LED is used as status LED in U-Boot. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-12-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts index f6c478dbd041..6a1c4e5d31a4 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -81,6 +81,12 @@ function = LED_FUNCTION_HEARTBEAT; color = ; }; + + led-red { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; }; sd_switch: regulator-sd_switch { From 55fb8865f35336b04b1b27efe6ce2bbafcc2c507 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 13 Nov 2025 16:14:04 +0100 Subject: [PATCH 677/757] ARM: dts: stm32: Update LED node for stm32mp15xx-dkx board Add led-red node for stm32mp15xx-dkx, this LED is used as status LED in U-Boot. Update led-blue node by adding color property and replacing obsolete label property by function property. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-13-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index 8cea6facd27b..fc0ff818e1fa 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include / { @@ -64,11 +65,18 @@ led { compatible = "gpio-leds"; led-blue { - label = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + color = ; gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; + + led-red { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; }; sound { From 86e73410c8bc512d7153a589cb9e13ca7c91c4b0 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 13 Nov 2025 16:14:05 +0100 Subject: [PATCH 678/757] arm64: dts: st: Add green and orange LED for stm32mp2 ST boards Add green and orange LED support on stm32mp235f-dk board. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-14-45090db9e2e5@foss.st.com Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-15-45090db9e2e5@foss.st.com Link: https://lore.kernel.org/r/20251113-upstream_update_led_nodes-v2-16-45090db9e2e5@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 10 ++++++++++ arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 10 ++++++++++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 23 ++++++++++++++++++++++ 3 files changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index c3e688068223..ab9a30103db7 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -53,6 +53,16 @@ linux,default-trigger = "heartbeat"; default-state = "off"; }; + + led-green { + color = ; + gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>; + }; + + led-orange { + color = ; + gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>; + }; }; memory@80000000 { diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index e718d888ce21..dc1a75f10f49 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -53,6 +53,16 @@ linux,default-trigger = "heartbeat"; default-state = "off"; }; + + led-green { + color = ; + gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>; + }; + + led-orange { + color = ; + gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>; + }; }; memory@80000000 { diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index bb6d6393d2e4..6e9aa392ba9a 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -7,6 +7,7 @@ /dts-v1/; #include +#include #include #include "stm32mp257.dtsi" #include "stm32mp25xf.dtsi" @@ -42,6 +43,28 @@ }; }; + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioj 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led-green { + color = ; + gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>; + }; + + led-orange { + color = ; + gpios = <&gpioj 6 GPIO_ACTIVE_HIGH>; + }; + }; + imx335_2v9: regulator-2v9 { compatible = "regulator-fixed"; regulator-name = "imx335-avdd"; From 5c6f60c2d2f83499e2fe5075e58ab11402059691 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 8 Jan 2026 16:52:35 +0100 Subject: [PATCH 679/757] ARM: dts: stm32: Add boot-led for stm32 MCU ST boards Add options/u-boot/boot-led property to specify to U-Boot the LED which indicates a successful boot. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-1-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-2-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-3-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-4-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-5-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-6-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-7-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-8-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-9-50a3a9b339a8@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32429i-eval.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32746g-eval.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32f429-disco.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32f469-disco.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32f746-disco.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32f769-disco.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32h743i-disco.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32h743i-eval.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32h747i-disco.dts | 9 ++++++++- 9 files changed, 72 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts index a138c0ac8e77..f4b1c4eb64f2 100644 --- a/arch/arm/boot/dts/st/stm32429i-eval.dts +++ b/arch/arm/boot/dts/st/stm32429i-eval.dts @@ -85,7 +85,7 @@ leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpiog 6 1>; @@ -127,6 +127,13 @@ regulator-max-microvolt = <3300000>; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + panel_rgb: panel-rgb { compatible = "ampire,am-480272h3tmqw-t01h"; power-supply = <&vdd_panel>; diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts index 78ceec4a9487..6772c1f9d03e 100644 --- a/arch/arm/boot/dts/st/stm32746g-eval.dts +++ b/arch/arm/boot/dts/st/stm32746g-eval.dts @@ -67,7 +67,7 @@ leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpiof 10 1>; @@ -133,6 +133,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts index 15f92842c8e1..ded369abee4f 100644 --- a/arch/arm/boot/dts/st/stm32f429-disco.dts +++ b/arch/arm/boot/dts/st/stm32f429-disco.dts @@ -77,7 +77,7 @@ color = ; gpios = <&gpiog 14 0>; }; - led-green { + led_green: led-green { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpiog 13 0>; @@ -95,6 +95,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + /* This turns on vbus for otg for host mode (dwc2) */ vcc5v_otg: vcc5v-otg-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts index f43547ec436d..943afba06b5f 100644 --- a/arch/arm/boot/dts/st/stm32f469-disco.dts +++ b/arch/arm/boot/dts/st/stm32f469-disco.dts @@ -83,7 +83,7 @@ leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpiog 6 GPIO_ACTIVE_LOW>; @@ -113,6 +113,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + /* This turns on vbus for otg for host mode (dwc2) */ vcc5v_otg: vcc5v-otg-regulator { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index 2e6086eea6ed..61ca41ea523e 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -81,7 +81,7 @@ leds { compatible = "gpio-leds"; - led-usr { + led_usr: led-usr { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>; @@ -99,6 +99,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_usr>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts index 97c276f81f9a..e5854fa1071b 100644 --- a/arch/arm/boot/dts/st/stm32f769-disco.dts +++ b/arch/arm/boot/dts/st/stm32f769-disco.dts @@ -80,7 +80,7 @@ leds { compatible = "gpio-leds"; - led-usr2 { + led_usr2: led-usr2 { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; @@ -106,6 +106,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_usr2>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/arch/arm/boot/dts/st/stm32h743i-disco.dts b/arch/arm/boot/dts/st/stm32h743i-disco.dts index f20266de4e7f..78d55b77db7c 100644 --- a/arch/arm/boot/dts/st/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h743i-disco.dts @@ -74,7 +74,7 @@ leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioi 12 GPIO_ACTIVE_LOW>; @@ -96,6 +96,13 @@ gpios = <&gpioi 15 GPIO_ACTIVE_LOW>; }; }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; }; &clk_hse { diff --git a/arch/arm/boot/dts/st/stm32h743i-eval.dts b/arch/arm/boot/dts/st/stm32h743i-eval.dts index 4b3e0c5a9009..e5e10b0758ee 100644 --- a/arch/arm/boot/dts/st/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/st/stm32h743i-eval.dts @@ -66,7 +66,7 @@ led { compatible = "gpio-leds"; - led-green { + led_green: led-green { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpiof 10 GPIO_ACTIVE_LOW>; @@ -80,6 +80,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; + vdda: regulator-vdda { compatible = "regulator-fixed"; regulator-name = "vdda"; diff --git a/arch/arm/boot/dts/st/stm32h747i-disco.dts b/arch/arm/boot/dts/st/stm32h747i-disco.dts index bb6649a58bc1..c9dcc680e26d 100644 --- a/arch/arm/boot/dts/st/stm32h747i-disco.dts +++ b/arch/arm/boot/dts/st/stm32h747i-disco.dts @@ -39,7 +39,7 @@ leds { compatible = "gpio-leds"; - led-green { + led_green: led-green { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioi 12 GPIO_ACTIVE_LOW>; @@ -93,6 +93,13 @@ gpios = <&gpiok 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; }; + + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_green>; + }; + }; }; &clk_hse { From 2e54d44665606b20e8c65be65b54d09616564321 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 12 Nov 2025 16:48:13 +0100 Subject: [PATCH 680/757] ARM: dts: stm32: Add boot-led for stm32mp1 ST boards Add options/u-boot/boot-led property to specify to U-Boot the LED which indicates a successful boot. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-10-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-11-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-12-50a3a9b339a8@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 9 ++++++++- arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 9 ++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 2549cf604ca3..8dcf68b212b4 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -73,7 +73,7 @@ leds { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; @@ -88,6 +88,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + panel_backlight: panel-backlight { compatible = "gpio-backlight"; gpios = <&gpioe 12 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts index 6a1c4e5d31a4..49dd555cc228 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts @@ -74,7 +74,7 @@ led { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; @@ -89,6 +89,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + sd_switch: regulator-sd_switch { compatible = "regulator-gpio"; regulator-name = "sd_switch"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi index fc0ff818e1fa..7ed2b01958fe 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -64,7 +64,7 @@ led { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; @@ -79,6 +79,13 @@ }; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + sound { compatible = "audio-graph-card"; label = "STM32MP15-DK"; From 0dfff7c550f3aa29441d0a5e581161b9eaa58697 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 12 Nov 2025 16:48:16 +0100 Subject: [PATCH 681/757] arm64: dts: st: Add boot-led for stm32mp2 ST boards Add options/u-boot/boot-led property to specify to U-Boot the LED which indicates a successful boot. Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-13-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-14-50a3a9b339a8@foss.st.com Link: https://lore.kernel.org/r/20251112-upstream_add_boot-led_for_stm32_boards-v1-15-50a3a9b339a8@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 9 ++++++++- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 9 ++++++++- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 9 ++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index ab9a30103db7..4d7e3939ba5c 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -46,7 +46,7 @@ gpio-leds { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; @@ -70,6 +70,13 @@ reg = <0x0 0x80000000 0x0 0x80000000>; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index dc1a75f10f49..d260e18cc1c9 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -46,7 +46,7 @@ gpio-leds { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; @@ -70,6 +70,13 @@ reg = <0x0 0x80000000 0x1 0x0>; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 6e9aa392ba9a..9821ef14e8f2 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -46,7 +46,7 @@ gpio-leds { compatible = "gpio-leds"; - led-blue { + led_blue: led-blue { function = LED_FUNCTION_HEARTBEAT; color = ; gpios = <&gpioj 7 GPIO_ACTIVE_HIGH>; @@ -94,6 +94,13 @@ reg = <0x0 0x80000000 0x1 0x0>; }; + options { + u-boot { + compatible = "u-boot,config"; + boot-led = <&led_blue>; + }; + }; + panel_lvds: display { compatible = "edt,etml0700z9ndha", "panel-lvds"; enable-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>; From 6d280a351e280a1f4f4f1ddcb1b75360f18406aa Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 15 Dec 2025 13:26:21 +0100 Subject: [PATCH 682/757] arm64: dts: st: add power-domains in all spi of stm32mp251.dtsi Add the power-domains property in all spi instances available on the stm32mp251.dtsi Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251215-stm32-spi-mp2x-dt-updates-v1-2-464a5fd20f13@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index a8e6e0f77b83..64c3487b3cda 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -672,6 +672,7 @@ <&hpdma 52 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 23>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -702,6 +703,7 @@ <&hpdma 54 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 24>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1048,6 +1050,7 @@ <&hpdma 50 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 22>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1063,6 +1066,7 @@ <&hpdma 56 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 25>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1171,6 +1175,7 @@ <&hpdma 58 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 26>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1380,6 +1385,7 @@ <&hpdma 60 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 27>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1395,6 +1401,7 @@ <&hpdma 62 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 28>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1444,6 +1451,7 @@ <&hpdma 172 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 29>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; From a5692f50392b4a947a3c328c6175b9abe1980129 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 15 Dec 2025 13:26:22 +0100 Subject: [PATCH 683/757] arm64: dts: st: add power-domains in all spi of stm32mp231.dtsi Add the power-domains property in all spi instances available on the stm32mp231.dtsi Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251215-stm32-spi-mp2x-dt-updates-v1-3-464a5fd20f13@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 88e214d395ab..6b1cd5cd2cfb 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -251,6 +251,7 @@ <&hpdma 52 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 23>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -281,6 +282,7 @@ <&hpdma 54 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 24>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -433,6 +435,7 @@ <&hpdma 50 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 22>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -448,6 +451,7 @@ <&hpdma 56 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 25>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -463,6 +467,7 @@ <&hpdma 58 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 26>; + power-domains = <&cluster_pd>; status = "disabled"; }; From 974e24ed49e03586c101c414ba9cf9764de5863b Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 15 Dec 2025 13:19:40 +0100 Subject: [PATCH 684/757] dt-bindings: i2c: st,stm32-i2c: add 'power-domains' property STM32 I2C may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 I2C. Signed-off-by: Alain Volmat Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251215-stm32-i2c-mp2x-dt-updates-v1-1-2738a05a7af8@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index 457bb0702ed9..64aaa0dfa8fa 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -127,6 +127,9 @@ properties: wakeup-source: true + power-domains: + maxItems: 1 + access-controllers: minItems: 1 maxItems: 2 From 4dc102d8fb7cd5e9da134c88693ef95e99407a9c Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 15 Dec 2025 13:19:41 +0100 Subject: [PATCH 685/757] arm64: dts: st: add power-domains in all i2c of stm32mp251.dtsi Add the power-domains property in all i2c instances available on the stm32mp251.dtsi Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251215-stm32-i2c-mp2x-dt-updates-v1-2-2738a05a7af8@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 64c3487b3cda..d62731c8a7cb 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -782,6 +782,7 @@ <&hpdma 28 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 41>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -798,6 +799,7 @@ <&hpdma 31 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 42>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -814,6 +816,7 @@ <&hpdma 34 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 43>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -830,6 +833,7 @@ <&hpdma 37 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 44>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -846,6 +850,7 @@ <&hpdma 40 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 45>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -862,6 +867,7 @@ <&hpdma 43 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 46>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -878,6 +884,7 @@ <&hpdma 46 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 47>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; @@ -1468,6 +1475,7 @@ <&hpdma 169 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 48>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; From d8d366cb6b6566e801da88c1ef44a3885b771610 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 15 Dec 2025 13:19:42 +0100 Subject: [PATCH 686/757] arm64: dts: st: add power-domains in all i2c of stm32mp231.dtsi Add the power-domains property in all i2c instances available on the stm32mp231.dtsi Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251215-stm32-i2c-mp2x-dt-updates-v1-3-2738a05a7af8@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 6b1cd5cd2cfb..9e1d841e8818 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -361,6 +361,7 @@ <&hpdma 28 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 41>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -377,6 +378,7 @@ <&hpdma 31 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 42>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -393,6 +395,7 @@ <&hpdma 46 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 47>; + power-domains = <&cluster_pd>; status = "disabled"; }; @@ -669,6 +672,7 @@ <&hpdma 169 0x20 0x3021>; dma-names = "rx", "tx"; access-controllers = <&rifsc 48>; + power-domains = <&cluster_pd>; status = "disabled"; }; From a81fcfd4487ba35de66e814933fe5df1c4a6b3e7 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 15 Dec 2025 13:19:43 +0100 Subject: [PATCH 687/757] arm64: dts: st: enable i2c analog-filter in stm32mp251.dtsi By default enable the analog filter on all i2c instances on the stm32mp25x series. Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251215-stm32-i2c-mp2x-dt-updates-v1-4-2738a05a7af8@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index d62731c8a7cb..e9e70ab46415 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -783,6 +783,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 41>; power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -800,6 +801,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 42>; power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -817,6 +819,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 43>; power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -834,6 +837,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 44>; power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -851,6 +855,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 45>; power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -868,6 +873,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 46>; power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -885,6 +891,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 47>; power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; @@ -1476,6 +1483,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 48>; power-domains = <&CLUSTER_PD>; + i2c-analog-filter; status = "disabled"; }; From 5e697793315433094196362000deb8a0c7f552b8 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 15 Dec 2025 13:19:44 +0100 Subject: [PATCH 688/757] arm64: dts: st: enable i2c analog-filter in stm32mp231.dtsi By default enable the analog filter on all i2c instances on the stm32mp23x series. Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251215-stm32-i2c-mp2x-dt-updates-v1-5-2738a05a7af8@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 9e1d841e8818..32f322eb7fa7 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -362,6 +362,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 41>; power-domains = <&cluster_pd>; + i2c-analog-filter; status = "disabled"; }; @@ -379,6 +380,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 42>; power-domains = <&cluster_pd>; + i2c-analog-filter; status = "disabled"; }; @@ -396,6 +398,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 47>; power-domains = <&cluster_pd>; + i2c-analog-filter; status = "disabled"; }; @@ -673,6 +676,7 @@ dma-names = "rx", "tx"; access-controllers = <&rifsc 48>; power-domains = <&cluster_pd>; + i2c-analog-filter; status = "disabled"; }; From ec6eac731f7bdfd54d44cb4c81706f85aa462d3e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Tue, 18 Nov 2025 16:08:02 +0100 Subject: [PATCH 689/757] arm64: dts: st: add LPDDR channel to stm32mp257f-dk board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add 32bits LPDDR4 channel to the stm32mp257f-dk board. Signed-off-by: Clément Le Goffic Signed-off-by: Clément Le Goffic Link: https://lore.kernel.org/r/20251118-b4-ddr-bindings-v9-6-a033ac5144da@gmail.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index d260e18cc1c9..dce564e7fabc 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -65,6 +65,13 @@ }; }; + lpddr_channel: sdram-channel-0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,lpddr4-channel"; + io-width = <32>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x1 0x0>; From ba96d918d31432ae4bdbfe2ac5e7a90569d60981 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20Le=20Goffic?= Date: Tue, 18 Nov 2025 16:08:03 +0100 Subject: [PATCH 690/757] arm64: dts: st: add DDR channel to stm32mp257f-ev1 board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add 32bits DDR4 channel to the stm32mp257f-dk board. Signed-off-by: Clément Le Goffic Signed-off-by: Clément Le Goffic Link: https://lore.kernel.org/r/20251118-b4-ddr-bindings-v9-7-a033ac5144da@gmail.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 9821ef14e8f2..e48407201be8 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -65,6 +65,13 @@ }; }; + ddr_channel: sdram-channel-0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,ddr4-channel"; + io-width = <32>; + }; + imx335_2v9: regulator-2v9 { compatible = "regulator-fixed"; regulator-name = "imx335-avdd"; From 75048a8de01bbf790b1da94a31b10665db42e065 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Thu, 18 Dec 2025 11:48:30 +0100 Subject: [PATCH 691/757] ARM: dts: stm32: add spi1 sleep state pinctrl on stm32mp157c-ev1 Add the sleep state of the spi1 instance on stm32mp157c-ev1. Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251218-stm32-spi-enhancements-v2-4-3b69901ca9fe@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts index 8f99c30f1af1..4e46d58bf61f 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -296,8 +296,9 @@ }; &spi1 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_pins_a>; + pinctrl-1 = <&spi1_sleep_pins_a>; status = "disabled"; }; From 9cdfabe2f2d1eed6e57d5b4fb18fb4719b6c565a Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 19 Dec 2025 16:58:03 +0100 Subject: [PATCH 692/757] dt-bindings: media: st: csi: add 'power-domains' property STM32 CSI may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 CSI. Signed-off-by: Alain Volmat Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-1-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml index e9fa3cfea5d2..2ac7c9670c62 100644 --- a/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml @@ -46,6 +46,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports From 886fd33507adfc121dde529f807eec5f76dc8653 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 19 Dec 2025 16:58:04 +0100 Subject: [PATCH 693/757] arm64: dts: st: add power-domain of csi in stm32mp251.dtsi Add the power-domain property in the csi node of stm32mp251.dtsi Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-2-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index e9e70ab46415..dd213bfc6858 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1613,6 +1613,7 @@ <&rcc CK_KER_CSIPHY>; clock-names = "pclk", "txesc", "csi2phy"; access-controllers = <&rifsc 86>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; From f447cf079dba72a655c2ad59a582447831b112aa Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 19 Dec 2025 16:58:05 +0100 Subject: [PATCH 694/757] arm64: dts: st: add power-domain of csi in stm32mp231.dtsi Add the power-domain property in the csi node of stm32mp231.dtsi Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-3-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 32f322eb7fa7..0b773c3c7c06 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -689,6 +689,7 @@ <&rcc CK_KER_CSIPHY>; clock-names = "pclk", "txesc", "csi2phy"; access-controllers = <&rifsc 86>; + power-domains = <&cluster_pd>; status = "disabled"; }; From 196369e3823ed10ff42364f580164640255f5a4c Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 19 Dec 2025 16:58:06 +0100 Subject: [PATCH 695/757] dt-bindings: media: st: dcmipp: add 'power-domains' property STM32 DCMIPP may be in a power domain which is the case for the STM32MP2x based boards. Allow a single 'power-domains' entry for STM32 DCMIPP. Signed-off-by: Alain Volmat Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-4-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml index 7b03a77adbce..162a0c526d5d 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml @@ -37,6 +37,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + access-controllers: minItems: 1 maxItems: 2 From f056d9a424c3ce50822659f06487d3272eca63db Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 19 Dec 2025 16:58:07 +0100 Subject: [PATCH 696/757] arm64: dts: st: add power-domain of dcmipp in stm32mp251.dtsi Add the power-domain property in the dcmipp node of stm32mp251.dtsi Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-5-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index dd213bfc6858..106989e53d94 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1625,6 +1625,7 @@ clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; clock-names = "kclk", "mclk"; access-controllers = <&rifsc 87>; + power-domains = <&CLUSTER_PD>; status = "disabled"; }; From 8648e9b18e3ef8a2960d2cc857b961333b52b183 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 19 Dec 2025 16:58:08 +0100 Subject: [PATCH 697/757] arm64: dts: st: add power-domain of dcmipp in stm32mp231.dtsi Add the power-domain property in the dcmipp node of stm32mp231.dtsi Signed-off-by: Alain Volmat Link: https://lore.kernel.org/r/20251219-stm32-mp2x-dcmipp-csi-power-domain-v1-6-a6edb2aa8154@foss.st.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 0b773c3c7c06..4cc0cd9a6cce 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -701,6 +701,7 @@ clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; clock-names = "kclk", "mclk"; access-controllers = <&rifsc 87>; + power-domains = <&cluster_pd>; status = "disabled"; }; From f4051bcb0f96f235a04d595e497a11eaf1caf13c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:25:45 +0100 Subject: [PATCH 698/757] arm64: dts: st: Use hyphen in node names DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251223152544.155637-3-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp231.dtsi | 4 ++-- arch/arm64/boot/dts/st/stm32mp251.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi index 4cc0cd9a6cce..b5d81d1ee153 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -776,11 +776,11 @@ #address-cells = <1>; #size-cells = <1>; - part_number_otp@24 { + part-number-otp@24 { reg = <0x24 0x4>; }; - package_otp@1e8 { + package-otp@1e8 { reg = <0x1e8 0x1>; bits = <0 3>; }; diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 106989e53d94..8b925ed0d881 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1765,11 +1765,11 @@ #address-cells = <1>; #size-cells = <1>; - part_number_otp@24 { + part-number-otp@24 { reg = <0x24 0x4>; }; - package_otp@1e8 { + package-otp@1e8 { reg = <0x1e8 0x1>; bits = <0 3>; }; From cd7d34dad61f3334fb5a0584fb8e7cfc88716082 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:25:46 +0100 Subject: [PATCH 699/757] arm64: dts: st: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' and before '{' characters. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20251223152544.155637-4-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Alexandre Torgue --- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 2 +- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 2 +- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index 4d7e3939ba5c..5ecc5ef61590 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -110,7 +110,7 @@ phy1_eth1: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; reg = <1>; - reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; }; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index dce564e7fabc..4135e7c0d9a3 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -117,7 +117,7 @@ phy1_eth1: ethernet-phy@1 { compatible = "ethernet-phy-id001c.c916"; reg = <1>; - reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; }; diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index e48407201be8..852a73b0c516 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -223,7 +223,7 @@ phy1_eth1: ethernet-phy@4 { compatible = "ethernet-phy-id001c.c916"; reg = <4>; - reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; reset-deassert-us = <80000>; }; From 7006477e7ff01ce9be7014f25049372450a8e17b Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Tue, 30 Dec 2025 10:14:29 -0800 Subject: [PATCH 700/757] arm64: STM32: drop an undefined Kconfig symbol Drop ARM_SMC_MBOX since it is not defined or used anywhere else in the kernel source tree. Fixes: 9e4e24414cc6 ("arm64: introduce STM32 family on Armv8 architecture") Signed-off-by: Randy Dunlap Link: https://lore.kernel.org/r/20251230181429.3429404-1-rdunlap@infradead.org Signed-off-by: Alexandre Torgue --- arch/arm64/Kconfig.platforms | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index fff14807c965..d8af5633341b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -372,7 +372,6 @@ config ARCH_STM32 bool "STMicroelectronics STM32 SoC Family" select GPIOLIB select PINCTRL - select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select REGULATOR select REGULATOR_ARM_SCMI From 1636348aab60830a1bc58a55916b218ce18712b5 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 13 Jan 2026 14:13:38 -0600 Subject: [PATCH 701/757] arm/arm64: dts: st: Drop unused .dtsi These .dtsi files are not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) Reviewed-by: Alexandre Torgue Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20260113201340.36950-1-robh@kernel.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/spear320s.dtsi | 24 ------- .../boot/dts/st/stm32mp15xxab-pinctrl.dtsi | 57 --------------- arch/arm64/boot/dts/st/stm32mp21xc.dtsi | 8 --- arch/arm64/boot/dts/st/stm32mp23xc.dtsi | 8 --- arch/arm64/boot/dts/st/stm32mp25xc.dtsi | 8 --- .../boot/dts/st/stm32mp25xxal-pinctrl.dtsi | 71 ------------------- 6 files changed, 176 deletions(-) delete mode 100644 arch/arm/boot/dts/st/spear320s.dtsi delete mode 100644 arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi delete mode 100644 arch/arm64/boot/dts/st/stm32mp21xc.dtsi delete mode 100644 arch/arm64/boot/dts/st/stm32mp23xc.dtsi delete mode 100644 arch/arm64/boot/dts/st/stm32mp25xc.dtsi delete mode 100644 arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi diff --git a/arch/arm/boot/dts/st/spear320s.dtsi b/arch/arm/boot/dts/st/spear320s.dtsi deleted file mode 100644 index 133236dc190d..000000000000 --- a/arch/arm/boot/dts/st/spear320s.dtsi +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * DTS file for SPEAr320s SoC - * - * Copyright 2021 Herve Codina - */ - -/include/ "spear320.dtsi" - -/ { - ahb { - apb { - gpiopinctrl: gpio@b3000000 { - /* - * The "RM0321 SPEAr320s address and map - * registers" document mentions interrupt 6 - * (NPGIO_INTR) for the PL_GPIO interrupt. - */ - interrupts = <6>; - interrupt-parent = <&shirq>; - }; - }; - }; -}; diff --git a/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi deleted file mode 100644 index 328dad140e9b..000000000000 --- a/arch/arm/boot/dts/st/stm32mp15xxab-pinctrl.dtsi +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2019 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@50002000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@50003000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@50004000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 32 16>; - }; - - gpiod: gpio@50005000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@50006000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@50007000 { - status = "okay"; - ngpios = <6>; - gpio-ranges = <&pinctrl 6 86 6>; - }; - - gpiog: gpio@50008000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl 6 102 10>; - }; - - gpioh: gpio@50009000 { - status = "okay"; - ngpios = <2>; - gpio-ranges = <&pinctrl 0 112 2>; - }; -}; diff --git a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi b/arch/arm64/boot/dts/st/stm32mp21xc.dtsi deleted file mode 100644 index e33b00b424e1..000000000000 --- a/arch/arm64/boot/dts/st/stm32mp21xc.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2025 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/ { -}; diff --git a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi b/arch/arm64/boot/dts/st/stm32mp23xc.dtsi deleted file mode 100644 index e33b00b424e1..000000000000 --- a/arch/arm64/boot/dts/st/stm32mp23xc.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2025 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/ { -}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi b/arch/arm64/boot/dts/st/stm32mp25xc.dtsi deleted file mode 100644 index 5e83a6926485..000000000000 --- a/arch/arm64/boot/dts/st/stm32mp25xc.dtsi +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -/ { -}; diff --git a/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi deleted file mode 100644 index 2406e972554c..000000000000 --- a/arch/arm64/boot/dts/st/stm32mp25xxal-pinctrl.dtsi +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author: Alexandre Torgue for STMicroelectronics. - */ - -&pinctrl { - st,package = ; - - gpioa: gpio@44240000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 0 16>; - }; - - gpiob: gpio@44250000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 16 16>; - }; - - gpioc: gpio@44260000 { - status = "okay"; - ngpios = <14>; - gpio-ranges = <&pinctrl 0 32 14>; - }; - - gpiod: gpio@44270000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - gpioe: gpio@44280000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 64 16>; - }; - - gpiof: gpio@44290000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 80 16>; - }; - - gpiog: gpio@442a0000 { - status = "okay"; - ngpios = <16>; - gpio-ranges = <&pinctrl 0 96 16>; - }; - - gpioh: gpio@442b0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 2 114 12>; - }; - - gpioi: gpio@442c0000 { - status = "okay"; - ngpios = <12>; - gpio-ranges = <&pinctrl 0 128 12>; - }; -}; - -&pinctrl_z { - gpioz: gpio@46200000 { - status = "okay"; - ngpios = <10>; - gpio-ranges = <&pinctrl_z 0 400 10>; - }; -}; From 6742b998166485558ccb0e89b5d5fd93c1aae3ca Mon Sep 17 00:00:00 2001 From: Luis Garcia Date: Sun, 18 Jan 2026 18:06:33 -0700 Subject: [PATCH 702/757] arm64: dts: rockchip: Fix imx258 variant on pinephone pro imx258 had the driver updated a while back and it introduced two variants, the imx258 and imx258-pdaf. The pinephone pro is using the pdaf variant so this switches it to the correct variant and eliminates the pdaf pixels from the sensor output resulting in a much cleaner image. Signed-off-by: Luis Garcia Link: https://patch.msgid.link/20260119010633.3447863-1-git@luigi311.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts index 141ab9850290..cee9e35d770e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts @@ -451,7 +451,7 @@ status = "okay"; wcam: camera@1a { - compatible = "sony,imx258"; + compatible = "sony,imx258-pdaf"; reg = <0x1a>; clocks = <&cru SCLK_CIF_OUT>; /* MIPI_MCLK0, derived from CIF_CLKO */ lens-focus = <&wcam_lens>; From b18247f9dab735c9c2d63823d28edc9011e7a1ad Mon Sep 17 00:00:00 2001 From: Jun Yan Date: Fri, 16 Jan 2026 23:12:53 +0800 Subject: [PATCH 703/757] arm64: dts: rockchip: Do not enable hdmi_sound node on Pinebook Pro Remove the redundant enabling of the hdmi_sound node in the Pinebook Pro board dts file, because the HDMI output is unused on this device. [1][2] This change also eliminates the following kernel log warning, which is caused by the unenabled dependent node of hdmi_sound that ultimately results in the node's probe failure: platform hdmi-sound: deferred probe pending: asoc-simple-card: parse error [1] https://files.pine64.org/doc/PinebookPro/pinebookpro_v2.1_mainboard_schematic.pdf [2] https://files.pine64.org/doc/PinebookPro/pinebookpro_schematic_v21a_20220419.pdf Cc: stable@vger.kernel.org Fixes: 5a65505a69884 ("arm64: dts: rockchip: Add initial support for Pinebook Pro") Signed-off-by: Jun Yan Reviewed-by: Peter Robinson Reviewed-by: Dragan Simic Link: https://patch.msgid.link/20260116151253.9223-1-jerrysteve1101@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index eaaca08a7601..a6ac89567baf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -421,10 +421,6 @@ status = "okay"; }; -&hdmi_sound { - status = "okay"; -}; - &i2c0 { clock-frequency = <400000>; i2c-scl-falling-time-ns = <4>; From e546c69ac54e907d0c33bc1fde55689db301981f Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 16 Jan 2026 22:05:24 +0100 Subject: [PATCH 704/757] ARM: dts: rockchip: rk3036: remove mshc aliases The use of mshc aliases is deprecated for some while, so remove them from the rk3036.dtsi file. Signed-off-by: Johan Jonker Link: https://patch.msgid.link/c6feab79-5b73-413b-a94f-9d1b2fa6df43@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rockchip/rk3036.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index fca21ebb224b..78afae42f8b2 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -23,9 +23,6 @@ i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; - mshc0 = &emmc; - mshc1 = &sdmmc; - mshc2 = &sdio; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; From 7d6fe7e381d2912300df06e1a7e7a6f6a9269af0 Mon Sep 17 00:00:00 2001 From: Encrow Thorne Date: Tue, 30 Dec 2025 23:06:53 +0800 Subject: [PATCH 705/757] riscv: dts: spacemit: add reset property Add resets property to K1 I2C node. Signed-off-by: Encrow Thorne Link: https://lore.kernel.org/r/20251230150653.42097-3-jyc0019@gmail.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 86d1db14e2ee..4c045da95d72 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -368,6 +368,7 @@ <&syscon_apbc CLK_TWSI0_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI0>; interrupts = <36>; status = "disabled"; }; @@ -381,6 +382,7 @@ <&syscon_apbc CLK_TWSI1_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI1>; interrupts = <37>; status = "disabled"; }; @@ -394,6 +396,7 @@ <&syscon_apbc CLK_TWSI2_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI2>; interrupts = <38>; status = "disabled"; }; @@ -407,6 +410,7 @@ <&syscon_apbc CLK_TWSI4_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI4>; interrupts = <40>; status = "disabled"; }; @@ -420,6 +424,7 @@ <&syscon_apbc CLK_TWSI5_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI5>; interrupts = <41>; status = "disabled"; }; @@ -490,6 +495,7 @@ <&syscon_apbc CLK_TWSI6_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI6>; interrupts = <70>; status = "disabled"; }; @@ -593,6 +599,7 @@ <&syscon_apbc CLK_TWSI7_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI7>; interrupts = <18>; status = "disabled"; }; @@ -606,6 +613,7 @@ <&syscon_apbc CLK_TWSI8_BUS>; clock-names = "func", "bus"; clock-frequency = <400000>; + resets = <&syscon_apbc RESET_TWSI8>; interrupts = <19>; status = "disabled"; }; From 7689c2d1bb1f53b170af79007d0611b43f232f05 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Tue, 23 Dec 2025 10:24:51 +0800 Subject: [PATCH 706/757] riscv: dts: spacemit: sdhci: add reset support Request two reset line explicitly for SDHCI controller. Reviewed-by: Javier Martinez Canillas Link: https://lore.kernel.org/r/20251223-07-k1-sdhci-reset-v2-3-5b8248cfc522@gentoo.org Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 4c045da95d72..1f7ed108da68 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -1168,6 +1168,9 @@ clocks = <&syscon_apmu CLK_SDH_AXI>, <&syscon_apmu CLK_SDH2>; clock-names = "core", "io"; + resets = <&syscon_apmu RESET_SDH_AXI>, + <&syscon_apmu RESET_SDH2>; + reset-names = "axi", "sdh"; interrupts = <101>; status = "disabled"; }; From 9d591fef025d5008f23ab339a10006b151150578 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:02 +0800 Subject: [PATCH 707/757] riscv: dts: spacemit: Add USB2 PHY node for K1 K1's DWC3 USB 3.0 controller requires two separate PHYs to function: the USB 3.0 combophy (for SuperSpeed) and a USB 2.0 PHY (for High-Speed, Full-Speed, etc.). Add node for this second USB 2.0 PHY (usbphy2). Tested-by: Aurelien Jarno Signed-off-by: Ze Huang Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-1-f5ebd546e904@linux.dev Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 1f7ed108da68..fdf7ebac0590 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -429,6 +429,14 @@ status = "disabled"; }; + usbphy2: phy@c0a30000 { + compatible = "spacemit,k1-usb2-phy"; + reg = <0x0 0xc0a30000 0x0 0x200>; + clocks = <&syscon_apmu CLK_USB30>; + #phy-cells = <0>; + status = "disabled"; + }; + combo_phy: phy@c0b10000 { compatible = "spacemit,k1-combo-phy"; reg = <0x0 0xc0b10000 0x0 0x1000>; From 6e8dcd141833a23d7117fe16896f6d5dfdb2e112 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:03 +0800 Subject: [PATCH 708/757] riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1 Add node for the Synopsys DWC3 USB 3.0 host controller on the K1 SoC. The controller resides on the 'storage-bus' and uses its DMA translations. Tested-by: Aurelien Jarno Signed-off-by: Ze Huang Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-2-f5ebd546e904@linux.dev Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index fdf7ebac0590..75877434f9f7 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -1170,6 +1170,30 @@ #size-cells = <2>; dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + usb_dwc3: usb@c0a00000 { + compatible = "spacemit,k1-dwc3"; + reg = <0x0 0xc0a00000 0x0 0x10000>; + clocks = <&syscon_apmu CLK_USB30>; + clock-names = "usbdrd30"; + interrupts = <125>; + phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi"; + resets = <&syscon_apmu RESET_USB30_AHB>, + <&syscon_apmu RESET_USB30_VCC>, + <&syscon_apmu RESET_USB30_PHY>; + reset-names = "ahb", "vcc", "phy"; + reset-delay = <2>; + snps,hsphy_interface = "utmi"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + emmc: mmc@d4281000 { compatible = "spacemit,k1-sdhci"; reg = <0x0 0xd4281000 0x0 0x200>; From c7e62c4eea026d42d192a0b86ce7313086ef2093 Mon Sep 17 00:00:00 2001 From: Ze Huang Date: Sun, 11 Jan 2026 14:41:04 +0800 Subject: [PATCH 709/757] riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3 Enable the DWC3 USB 3.0 controller and its associated usbphy2 on the Banana Pi F3 board. The board utilizes a VLI VL817 hub, which requires two separate power supplies: one VBUS and one for hub itself. Add two GPIO-controlled fixed-regulators to manage this. Tested-by: Aurelien Jarno Signed-off-by: Ze Huang Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260111-k1-usb3dts-v2-v3-3-f5ebd546e904@linux.dev Signed-off-by: Yixun Lan --- .../boot/dts/spacemit/k1-bananapi-f3.dts | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts index 3f10efd925dc..5971605754b3 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -59,6 +59,25 @@ regulator-always-on; vin-supply = <®_dc_in>; }; + + usb3-vbus-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb3_hub_5v: usb3-hub-5v { + compatible = "regulator-fixed"; + regulator-name = "USB30_HUB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &combo_phy { @@ -313,3 +332,30 @@ pinctrl-0 = <&uart0_2_cfg>; status = "okay"; }; + +&usbphy2 { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb2109,2817"; + reg = <0x1>; + vdd-supply = <&usb3_hub_5v>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; + + hub_3_0: hub@2 { + compatible = "usb2109,817"; + reg = <0x2>; + vdd-supply = <&usb3_hub_5v>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>; + }; +}; From 4168630825f95bf57729dad46d2a097096e73e4d Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:19:00 +0800 Subject: [PATCH 710/757] riscv: dts: spacemit: k1: Add "b" ISA extension "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update k1.dtsi to conform to this rule. Signed-off-by: Guodong Xu Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 75877434f9f7..cf5802687835 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -54,9 +54,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <0>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -84,9 +84,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <1>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -114,9 +114,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <2>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -144,9 +144,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <3>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -174,9 +174,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <4>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -204,9 +204,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <5>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -234,9 +234,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <6>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -264,9 +264,9 @@ compatible = "spacemit,x60", "riscv"; device_type = "cpu"; reg = <7>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; + riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", From 81a52103b90f5cddc41c34f633c014a956236abc Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:40 +0800 Subject: [PATCH 711/757] dt-bindings: riscv: add SpacemiT X100 CPU compatible Add compatible string for the SpacemiT X100 core. [1] The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 supports the RISC-V vector and hypervisor extensions and all mandatory extersions as required by the RVA23U64 and RVA23S64 profiles, per the definition in 'RVA23 Profile, Version 1.0'. [2] From a microarchieture viewpoint, the X100 features a 4-issue out-of-order pipeline. X100 is used in SpacemiT K3 SoC. Acked-by: Paul Walmsley Acked-by: Krzysztof Kozlowski Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] Reviewed-by: Yixun Lan Reviewed-by: Heinrich Schuchardt Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d733c0bd534f..5feeb2203050 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -61,6 +61,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x100 - spacemit,x60 - thead,c906 - thead,c908 From 6cdeb30db4d8faf9f1fa7ab863d91d36a584716d Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:41 +0800 Subject: [PATCH 712/757] dt-bindings: timer: add SpacemiT K3 CLINT Add compatible string for SpacemiT K3 CLINT. Acked-by: Conor Dooley Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 0d3b8dc362ba..3bab40500df9 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 + - spacemit,k3-clint # SpacemiT K3 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 From 60490ca6d54b6f0a00223a4fe59bb180bb1538bf Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:42 +0800 Subject: [PATCH 713/757] dt-bindings: interrupt-controller: add SpacemiT K3 APLIC Add compatible string for SpacemiT K3 APLIC. Acked-by: Conor Dooley Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-3-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- .../devicetree/bindings/interrupt-controller/riscv,aplic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml index bef00521d5da..0718071444d2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml @@ -28,6 +28,7 @@ properties: items: - enum: - qemu,aplic + - spacemit,k3-aplic - const: riscv,aplic reg: From a716729a3ce1055efab477030235777d2be0852b Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:43 +0800 Subject: [PATCH 714/757] dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC Add compatible string for SpacemiT K3 IMSIC. Acked-by: Krzysztof Kozlowski Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-4-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- .../devicetree/bindings/interrupt-controller/riscv,imsics.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml index c23b5c09fdb9..feec122bddde 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml @@ -48,6 +48,7 @@ properties: items: - enum: - qemu,imsics + - spacemit,k3-imsics - const: riscv,imsics reg: From 7cb5fafc180f6e188af7943d6b162051f22490fc Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:44 +0800 Subject: [PATCH 715/757] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX which is a 2.5-inch single-board computer. Acked-by: Conor Dooley Reviewed-by: Yixun Lan Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 9c49482002f7..b958b94a924d 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SpacemiT SoC-based boards maintainers: + - Guodong Xu - Yangyu Chen - Yixun Lan @@ -26,6 +27,10 @@ properties: - xunlong,orangepi-r2s - xunlong,orangepi-rv2 - const: spacemit,k1 + - items: + - enum: + - spacemit,k3-pico-itx + - const: spacemit,k3 additionalProperties: true From 56f37e391a626f964615ee5939710eff212b621f Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:45 +0800 Subject: [PATCH 716/757] riscv: dts: spacemit: add initial support for K3 SoC SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. Add nodes of uarts, timer and interrupt-controllers. Also add M-mode APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware topology and ready for potential firmware usage. Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k3.dtsi | 578 +++++++++++++++++++++++++++ 1 file changed, 578 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k3.dtsi diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi new file mode 100644 index 000000000000..b69cf81b5d55 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -0,0 +1,578 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu + */ + +#include + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SpacemiT K3"; + compatible = "spacemit,k3"; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <24000000>; + + cpu_0: cpu@0 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <0>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_1: cpu@1 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <1>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_2: cpu@2 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <2>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_3: cpu@3 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <3>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache0>; + mmu-type = "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_4: cpu@4 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <4>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_5: cpu@5 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <5>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_6: cpu@6 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <6>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + cpu_7: cpu@7 { + compatible = "spacemit,x100", "riscv"; + device_type = "cpu"; + reg = <7>; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size = <64>; + riscv,cbop-block-size = <64>; + riscv,cboz-block-size = <64>; + i-cache-block-size = <64>; + i-cache-size = <65536>; + i-cache-sets = <256>; + d-cache-block-size = <64>; + d-cache-size = <65536>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache1>; + mmu-type = "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <4194304>; + cache-sets = <4096>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible = "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-size = <4194304>; + cache-sets = <4096>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_0>; + }; + core1 { + cpu = <&cpu_1>; + }; + core2 { + cpu = <&cpu_2>; + }; + core3 { + cpu = <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_4>; + }; + core1 { + cpu = <&cpu_5>; + }; + core2 { + cpu = <&cpu_6>; + }; + core3 { + cpu = <&cpu_7>; + }; + }; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&saplic>; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart2: serial@d4017100 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017100 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart3: serial@d4017200 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017200 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart4: serial@d4017300 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017300 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart5: serial@d4017400 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017400 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart6: serial@d4017500 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017500 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart7: serial@d4017600 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017600 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart8: serial@d4017700 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017700 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart9: serial@d4017800 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd4017800 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + uart10: serial@d401f000 { + compatible = "spacemit,k3-uart", "intel,xscale-uart"; + reg = <0x0 0xd401f000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <14700000>; + interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + simsic: interrupt-controller@e0400000 { + compatible = "spacemit,k3-imsics", "riscv,imsics"; + reg = <0x0 0xe0400000 0x0 0x200000>; + #interrupt-cells = <0>; + #msi-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>, + <&cpu6_intc 9>, <&cpu7_intc 9>; + msi-controller; + riscv,guest-index-bits = <6>; + riscv,hart-index-bits = <4>; + riscv,num-guest-ids = <511>; + riscv,num-ids = <511>; + }; + + saplic: interrupt-controller@e0804000 { + compatible = "spacemit,k3-aplic", "riscv,aplic"; + reg = <0x0 0xe0804000 0x0 0x4000>; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&simsic>; + riscv,num-sources = <512>; + }; + + clint: timer@e081c000 { + compatible = "spacemit,k3-clint", "sifive,clint0"; + reg = <0x0 0xe081c000 0x0 0x4000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + mimsic: interrupt-controller@f1000000 { + compatible = "spacemit,k3-imsics", "riscv,imsics"; + reg = <0x0 0xf1000000 0x0 0x10000>; + #interrupt-cells = <0>; + #msi-cells = <0>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu6_intc 11>, <&cpu7_intc 11>; + msi-controller; + riscv,guest-index-bits = <6>; + riscv,hart-index-bits = <4>; + riscv,num-guest-ids = <511>; + riscv,num-ids = <511>; + status = "reserved"; + }; + + maplic: interrupt-controller@f1800000 { + compatible = "spacemit,k3-aplic", "riscv,aplic"; + reg = <0x0 0xf1800000 0x0 0x4000>; + #interrupt-cells = <2>; + interrupt-controller; + msi-parent = <&mimsic>; + riscv,children = <&saplic>; + riscv,delegation = <&saplic 1 512>; + riscv,num-sources = <512>; + status = "reserved"; + }; + }; +}; From 7a61318049861b777f098d7148d892d7dc79b010 Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:46 +0800 Subject: [PATCH 717/757] riscv: dts: spacemit: add K3 Pico-ITX board support K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT K3 SoC. This minimal device tree enables booting into a serial console with UART output. Signed-off-by: Guodong Xu Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/Makefile | 1 + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/riscv/boot/dts/spacemit/k3-pico-itx.dts diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile index 95889e7269d1..7e2b87702571 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts new file mode 100644 index 000000000000..b691304d4b74 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu + */ + +#include "k3.dtsi" + +/ { + model = "SpacemiT K3 Pico-ITX"; + compatible = "spacemit,k3-pico-itx", "spacemit,k3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + memory@100000000 { + device_type = "memory"; + reg = <0x1 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + status = "okay"; +}; From 4083d8d6c0aa445fc440d70a5258351c47547ee2 Mon Sep 17 00:00:00 2001 From: Troy Mitchell Date: Thu, 8 Jan 2026 14:42:40 +0800 Subject: [PATCH 718/757] riscv: dts: spacemit: pinctrl: update register and IO power Change the size of the reg register to 0x1000 to match the hardware. This register range covers the IO power domain's register addresses. The IO power domain registers are protected. In order to access the protected IO power domain registers, a valid unlock sequence must be performed by writing the required keys to the AIB Secure Access Register (ASAR). The ASAR register resides within the APBC register address space. A corresponding syscon property `spacemit,apbc` is added to allow the pinctrl driver to access this register. Signed-off-by: Troy Mitchell Acked-by: Linus Walleij Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index cf5802687835..529ec68e9c23 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -628,10 +628,11 @@ pinctrl: pinctrl@d401e000 { compatible = "spacemit,k1-pinctrl"; - reg = <0x0 0xd401e000 0x0 0x400>; + reg = <0x0 0xd401e000 0x0 0x1000>; clocks = <&syscon_apbc CLK_AIB>, <&syscon_apbc CLK_AIB_BUS>; clock-names = "func", "bus"; + spacemit,apbc = <&syscon_apbc>; }; pwm8: pwm@d4020000 { From 5164e95565d3fd508ca8a95351323f5716dfb695 Mon Sep 17 00:00:00 2001 From: Chukun Pan Date: Tue, 20 Jan 2026 18:00:01 +0800 Subject: [PATCH 719/757] riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePi On the SpacemiT K1 platform, the MAC can't read statistics when the PHY clock stops. Disable Link Down Power Saving Mode for the YT8531C PHY on OrangePi R2S and RV2 boards to avoid reading statistics timeout logs. Signed-off-by: Chukun Pan Reviewed-by: Yixun Lan Link: https://lore.kernel.org/r/20260120100001.1285624-2-amadeus@jmu.edu.cn Signed-off-by: Yixun Lan --- arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts | 2 ++ arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts index 58098c4a2aab..de75f6aac740 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts @@ -52,6 +52,7 @@ rgmii0: phy@1 { reg = <0x1>; + motorcomm,auto-sleep-disabled; }; }; }; @@ -75,6 +76,7 @@ rgmii1: phy@1 { reg = <0x1>; + motorcomm,auto-sleep-disabled; }; }; }; diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts index 41dc8e35e6eb..7b7331cb3c72 100644 --- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts +++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts @@ -54,6 +54,7 @@ rgmii0: phy@1 { reg = <0x1>; + motorcomm,auto-sleep-disabled; }; }; }; @@ -77,6 +78,7 @@ rgmii1: phy@1 { reg = <0x1>; + motorcomm,auto-sleep-disabled; }; }; }; From 851d5ae6003b6517fb641675c33d4b529765fe14 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 13 Jan 2026 18:41:59 +0200 Subject: [PATCH 720/757] arm64: dts: qcom: agatti: enable FastRPC on the ADSP On Agatti platform the ADSP provides FastRPC support. Add corresponding device node, in order to be able to utilize the DSP offload from the Linux side. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260113-agatti-fastrpc-v2-1-b66870213f89@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 41 ++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 7815ece261ea..217d465df846 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -2287,6 +2287,47 @@ }; }; }; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + + qcom,non-secure-domain; + + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1c3 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1c4 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1c5 0x0>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1c6 0x0>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1c7 0x0>; + }; + }; }; }; From 15bbdb3e56684bfe6ca2a38dd9c2d5bd2d2a8247 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 14 Nov 2025 10:31:13 +0100 Subject: [PATCH 721/757] arm64: dts: qcom: sm6350: Add clocks for aggre1 & aggre2 NoC As per updated bindings, add the clocks for those two interconnects, which are required to set up QoS correctly. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20251114-sm6350-icc-qos-v2-5-6af348cb9c69@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index f34dc6e278b8..9f9b9f9af0da 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1117,6 +1117,7 @@ reg = <0x0 0x016e0000 0x0 0x15080>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; }; aggre2_noc: interconnect@1700000 { @@ -1124,6 +1125,8 @@ reg = <0x0 0x01700000 0x0 0x1f880>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; compute_noc: interconnect-compute-noc { compatible = "qcom,sm6350-compute-noc"; From 1ef28ee5c51f21bc3ff493dfdc175827bbabf195 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 30 Nov 2025 00:22:39 +0100 Subject: [PATCH 722/757] arm64: dts: qcom: oneplus-enchilada: Specify i2c4 clock frequency Per the binding, omitting the clock frequency from a Geni I2C controller node defaults the bus to 100 kHz. But at least in Linux, a friendly info print highlights the lack of explicitly defined frequency in the DeviceTree. Specify the frequency, to give it an explicit value, and to silence the log print in Linux. Downstream doesn't define any frequency, thus also using 100 kHz. Signed-off-by: David Heidelberg Link: https://lore.kernel.org/r/20251130-enchilada-i2c-freq-v1-1-2932480a0261@ixit.cz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index dcaea15c6d43..c7e5268cc3fa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -45,6 +45,8 @@ }; &i2c4 { + clock-frequency = <100000>; + status = "okay"; max98927_codec: max98927@3a { From 854583f9992671411bad28bd8a3867afba7cce77 Mon Sep 17 00:00:00 2001 From: Nick Xie Date: Wed, 21 Jan 2026 09:47:25 +0800 Subject: [PATCH 723/757] arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable SDIO interface Enable the SDIO controller interface connected to the on-board AP6256 WiFi/BT module. Signed-off-by: Nick Xie Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260121014725.122722-1-nick@khadas.com Signed-off-by: Neil Armstrong --- .../amlogic/meson-s4-s905y4-khadas-vim1s.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts index 4a66c1bec965..27d0f6134ea9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts @@ -220,6 +220,33 @@ vqmmc-supply = <&vddio_sd>; }; +&sdio { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <50000000>; + non-removable; + disable-wp; + + no-sd; + no-mmc; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + }; +}; + &spicc0 { status = "okay"; pinctrl-names = "default"; From 16860aee5003dc63f788f6f2999d657da991bd58 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 11 Dec 2025 03:52:52 +0200 Subject: [PATCH 724/757] arm64: dts: qcom: switch to RPMPD_* indices Use generic RPMPD_* defines for power domain instead of using platform-specific defines. Reviewed-by: Bjorn Andersson Acked-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251211-rework-rpmhpd-rpmpd-v2-1-a5ec4028129f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/msm8917.dtsi | 10 +++++----- arch/arm64/boot/dts/qcom/msm8937.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/msm8976.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/qcom/sdm630.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6125.dtsi | 12 ++++++------ 8 files changed, 40 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index d3a25a837488..e39743e22043 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1945,8 +1945,8 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8916_VDDCX>, - <&rpmpd MSM8916_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, @@ -2449,8 +2449,8 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8916_VDDCX>, - <&rpmpd MSM8916_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8917.dtsi b/arch/arm64/boot/dts/qcom/msm8917.dtsi index 6251189b8e6d..a2907f8a6376 100644 --- a/arch/arm64/boot/dts/qcom/msm8917.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8917.dtsi @@ -1070,7 +1070,7 @@ phys = <&mdss_dsi0_phy>; operating-points-v2 = <&mdss_dsi0_opp_table>; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1288,7 +1288,7 @@ pinctrl-0 = <&sdc1_default>; pinctrl-1 = <&sdc1_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-ddr-1_8v; @@ -1313,7 +1313,7 @@ pinctrl-0 = <&sdc2_default>; pinctrl-1 = <&sdc2_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8917_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <4>; status = "disabled"; }; @@ -1517,8 +1517,8 @@ <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8917_VDDCX>, - <&rpmpd MSM8917_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8937.dtsi b/arch/arm64/boot/dts/qcom/msm8937.dtsi index c94eb14e31bd..7de6447de48f 100644 --- a/arch/arm64/boot/dts/qcom/msm8937.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8937.dtsi @@ -1122,7 +1122,7 @@ phys = <&mdss_dsi0_phy>; operating-points-v2 = <&mdss_dsi0_opp_table>; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1210,7 +1210,7 @@ phys = <&mdss_dsi1_phy>; operating-points-v2 = <&mdss_dsi1_opp_table>; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #address-cells = <1>; #size-cells = <0>; @@ -1457,7 +1457,7 @@ pinctrl-1 = <&sdc1_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; mmc-hs200-1_8v; mmc-hs400-1_8v; mmc-ddr-1_8v; @@ -1487,7 +1487,7 @@ pinctrl-1 = <&sdc2_sleep>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd MSM8937_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <4>; status = "disabled"; }; @@ -1710,8 +1710,8 @@ "handover", "stop-ack"; - power-domains = <&rpmpd MSM8937_VDDCX>, - <&rpmpd MSM8937_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index f9962512f243..80a0a09e055d 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -1558,8 +1558,8 @@ "handover", "stop-ack"; - power-domains = <&rpmpd MSM8976_VDDCX>, - <&rpmpd MSM8976_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; qcom,smem-states = <&wcnss_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 5c75fba16ce2..d41b5c470c48 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1497,8 +1497,8 @@ qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - power-domains = <&rpmpd MSM8998_VDDCX>, - <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; status = "disabled"; @@ -1544,7 +1544,7 @@ interrupts = ; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; - power-domains = <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; status = "disabled"; gpu_opp_table: opp-table { @@ -1680,7 +1680,7 @@ qcom,smem-states = <&slpi_smp2p_out 0>; qcom,smem-state-names = "stop"; - power-domains = <&rpmpd MSM8998_SSCCX>; + power-domains = <&rpmpd RPMPD_SSCCX>; power-domain-names = "ssc_cx"; status = "disabled"; @@ -2871,7 +2871,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd MSM8998_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; mdp_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2953,7 +2953,7 @@ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; @@ -3029,7 +3029,7 @@ <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi1_phy>; phy-names = "dsi"; @@ -3277,7 +3277,7 @@ qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; - power-domains = <&rpmpd MSM8998_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 4a72e0718fe4..f4b8e8f468f2 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1058,8 +1058,8 @@ qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; - power-domains = <&rpmpd SDM660_VDDCX>, - <&rpmpd SDM660_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDCX>, + <&rpmpd RPMPD_VDDMX>; power-domain-names = "cx", "mx"; memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>; @@ -1096,7 +1096,7 @@ "rbcpr", "core"; - power-domains = <&rpmpd SDM660_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; iommus = <&kgsl_smmu 0>; nvmem-cells = <&gpu_speed_bin>; @@ -1401,7 +1401,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_state_on>; pinctrl-1 = <&sdc2_state_off>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; status = "disabled"; @@ -1455,7 +1455,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; bus-width = <8>; non-removable; @@ -1618,7 +1618,7 @@ "rotator-mem"; iommus = <&mmss_smmu 0>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; ports { #address-cells = <1>; @@ -1670,7 +1670,7 @@ reg-names = "dsi_ctrl"; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; interrupt-parent = <&mdss>; interrupts = <4>; @@ -2359,7 +2359,7 @@ clock-names = "xo"; memory-region = <&adsp_region>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; qcom,smem-states = <&adsp_smp2p_out 0>; diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index c252f248ef15..3fd6dd82a992 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -194,7 +194,7 @@ /* DSI1 shares the OPP table with DSI0 */ operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SDM660_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; interrupt-parent = <&mdss>; interrupts = <5>; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 8f2d65543373..80c42dff5399 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -724,7 +724,7 @@ clock-names = "iface", "core", "xo"; iommus = <&apps_smmu 0x160 0x0>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040873>; @@ -755,7 +755,7 @@ pinctrl-1 = <&sdc2_off_state>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040873>; @@ -1275,7 +1275,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; ports { #address-cells = <1>; @@ -1345,7 +1345,7 @@ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; @@ -1406,7 +1406,7 @@ "ref"; required-opps = <&rpmpd_opp_nom>; - power-domains = <&rpmpd SM6125_VDDMX>; + power-domains = <&rpmpd RPMPD_VDDMX>; status = "disabled"; }; @@ -1434,7 +1434,7 @@ "gcc_disp_gpll0_div_clk_src"; required-opps = <&rpmpd_opp_ret>; - power-domains = <&rpmpd SM6125_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; #clock-cells = <1>; #power-domain-cells = <1>; From 0bcf9ca23a873e5208a32a7e8b908a6002babc8f Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Tue, 9 Dec 2025 07:37:59 +0000 Subject: [PATCH 725/757] arm64: dts: qcom: sm8750: add memory node for adsp fastrpc Add optional memory heap node that can be used for ADSP fastrpc. Cc: Ekansh Gupta Cc: Srinivas Kandagatla Signed-off-by: Alexey Klimov Link: https://lore.kernel.org/r/20251209-sm8750-fastrpc-adsp-v3-1-ccfff49a8af9@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 51fd1d05503c..9a3cd8224fae 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -540,6 +540,14 @@ reg = <0x0 0xff800000 0x0 0x800000>; no-map; }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x400000>; + size = <0x0 0xc00000>; + reusable; + }; }; smp2p-adsp { From be9d54c35312479ed92c85aec3cd43153513210d Mon Sep 17 00:00:00 2001 From: Alexey Klimov Date: Tue, 9 Dec 2025 07:38:00 +0000 Subject: [PATCH 726/757] arm64: dts: qcom: sm8750: add ADSP fastrpc-compute-cb nodes Add ADSP fastrpc nodes for sm8750 SoC. Cc: Ekansh Gupta Cc: Srinivas Kandagatla Signed-off-by: Alexey Klimov Link: https://lore.kernel.org/r/20251209-sm8750-fastrpc-adsp-v3-2-ccfff49a8af9@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 61 ++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 9a3cd8224fae..f56b1f889b85 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -2222,6 +2223,66 @@ qcom,remote-pid = <2>; label = "lpass"; + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + memory-region = <&adsp_rpc_remote_heap_mem>; + qcom,vmids = ; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1003 0x80>, + <&apps_smmu 0x1043 0x20>; + dma-coherent; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1004 0x80>, + <&apps_smmu 0x1044 0x20>; + dma-coherent; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1005 0x80>, + <&apps_smmu 0x1045 0x20>; + dma-coherent; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x1006 0x80>, + <&apps_smmu 0x1046 0x20>; + dma-coherent; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x1007 0x40>, + <&apps_smmu 0x1067 0x0>, + <&apps_smmu 0x1087 0x0>; + dma-coherent; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x1008 0x80>, + <&apps_smmu 0x1048 0x20>; + dma-coherent; + }; + }; + gpr { compatible = "qcom,gpr"; qcom,glink-channels = "adsp_apps"; From 0fdcc948929a6d673bd0f90631dd6e42090c3dbd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 29 Dec 2025 21:47:40 +0100 Subject: [PATCH 727/757] arm64: dts: qcom: agatti: Add CX_MEM/DBGC GPU regions Describe the GPU register regions, with the former existing but not being used much if at all on this silicon, and the latter containing various debugging levers generally related to dumping the state of the IP upon a crash. Fixes: 4faeef52c8e6 ("arm64: dts: qcom: qcm2290: Add GPU nodes") Reported-by: Krzysztof Kozlowski Closes: https://lore.kernel.org/linux-arm-msm/8a64f70b-8034-45e7-86a3-0015cf357132@oss.qualcomm.com/T/#m404f1425c36b61467760f058b696b8910340a063 Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Link: https://lore.kernel.org/r/20251229-topic-6115_2290_gpu_dbgc-v1-2-4a24d196389c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/agatti.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi index 217d465df846..76b93b7bd50f 100644 --- a/arch/arm64/boot/dts/qcom/agatti.dtsi +++ b/arch/arm64/boot/dts/qcom/agatti.dtsi @@ -1643,8 +1643,12 @@ gpu: gpu@5900000 { compatible = "qcom,adreno-07000200", "qcom,adreno"; - reg = <0x0 0x05900000 0x0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; + reg = <0x0 0x05900000 0x0 0x40000>, + <0x0 0x0599e000 0x0 0x1000>, + <0x0 0x05961000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; interrupts = ; From 78c13dac18cf0e6f6cbc6ea85d4f967e6cca9562 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 29 Dec 2025 21:47:41 +0100 Subject: [PATCH 728/757] arm64: dts: qcom: sm6115: Add CX_MEM/DBGC GPU regions Describe the GPU register regions, with the former existing but not being used much if at all on this silicon, and the latter containing various debugging levers generally related to dumping the state of the IP upon a crash. Fixes: 11750af256f8 ("arm64: dts: qcom: sm6115: Add GPU nodes") Reported-by: Krzysztof Kozlowski Closes: https://lore.kernel.org/linux-arm-msm/8a64f70b-8034-45e7-86a3-0015cf357132@oss.qualcomm.com/T/#m404f1425c36b61467760f058b696b8910340a063 Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Link: https://lore.kernel.org/r/20251229-topic-6115_2290_gpu_dbgc-v1-3-4a24d196389c@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 88513b513871..e9336adbc391 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1715,8 +1715,12 @@ gpu: gpu@5900000 { compatible = "qcom,adreno-610.0", "qcom,adreno"; - reg = <0x0 0x05900000 0x0 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; + reg = <0x0 0x05900000 0x0 0x40000>, + <0x0 0x0599e000 0x0 0x1000>, + <0x0 0x05961000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, From 4506cdf52a806be0d9e1b1c0b6c9bc2909ca8b1c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 11 Dec 2025 03:52:53 +0200 Subject: [PATCH 729/757] ARM: dts: qcom: switch to RPMPD_* indices Use generic RPMPD_* defines for power domain instead of using platform-specific defines. Reviewed-by: Bjorn Andersson Acked-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20251211-rework-rpmhpd-rpmpd-v2-2-a5ec4028129f@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 51a7a3fb36d8..bcf14a3b13a1 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -959,7 +959,7 @@ resets = <&gcc GCC_MSS_RESTART>; reset-names = "mss_restart"; - power-domains = <&rpmpd MSM8226_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; qcom,ext-bhs-reg = <&tcsr_regs_1 0x194>; @@ -1372,7 +1372,7 @@ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - power-domains = <&rpmpd MSM8226_VDDCX>; + power-domains = <&rpmpd RPMPD_VDDCX>; power-domain-names = "cx"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; From f6c8955f08749e2ded547a48ce6002df2c100859 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 12 Jan 2026 15:55:57 +0100 Subject: [PATCH 730/757] arm64: dts: marvell: Add SoC specific compatibles to SafeXcel crypto Following the changes in the binding for the SafeXcel crypto engine, add SoC specific compatibles to the existing nodes in Armada 37xx and CP11x. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 3 ++- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index c612317043ea..87f9367aec12 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -427,7 +427,8 @@ }; crypto: crypto@90000 { - compatible = "inside-secure,safexcel-eip97ies"; + compatible = "marvell,armada-3700-crypto", + "inside-secure,safexcel-eip97ies"; reg = <0x90000 0x20000>; interrupts = , , diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index d9d409eac259..39599171d51b 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -512,7 +512,8 @@ }; CP11X_LABEL(crypto): crypto@800000 { - compatible = "inside-secure,safexcel-eip197b"; + compatible = "marvell,armada-cp110-crypto", + "inside-secure,safexcel-eip197b"; reg = <0x800000 0x200000>; interrupts = <88 IRQ_TYPE_LEVEL_HIGH>, <89 IRQ_TYPE_LEVEL_HIGH>, From f36e738549d483878ebf4cc9826c46d9dc4aa496 Mon Sep 17 00:00:00 2001 From: Alex Studer Date: Tue, 13 Jan 2026 19:29:48 +0100 Subject: [PATCH 731/757] riscv: dts: allwinner: d1: Add CPU thermal sensor and zone The sun20i THS (built in CPU thermal sensor) is supported in code, but was never added to the device tree. So, add it to the device tree, along with a thermal zone for the CPU. Signed-off-by: Alex Studer Changes since v1: - Move include before defines in sun20i-d1s.dtsi - Fix register size for thermal-sensor@2009400 - Move thermal-sensor@2009400 in SoC to match register address sorting - Add thermal-zone for sun8i-t113s.dtsi and fix missing cooling-cells Link: https://lore.kernel.org/r/20250218020629.1476126-1-alex@studer.dev Signed-off-by: Lukas Schmid Link: https://patch.msgid.link/20260113182951.1059690-1-lukas.schmid@netcube.li Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 33 +++++++++++++++++++ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 31 +++++++++++++++++ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 16 +++++++++ 3 files changed, 80 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi index c7181308ae6f..424f4a2487e2 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -4,6 +4,7 @@ #define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr #include +#include #include #include @@ -20,6 +21,7 @@ reg = <0>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -28,6 +30,7 @@ reg = <1>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; + #cooling-cells = <2>; }; }; @@ -56,4 +59,34 @@ ; interrupt-affinity = <&cpu0>, <&cpu1>; }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths>; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index a7442a508433..3f4ee820ef56 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2021-2022 Samuel Holland +#include + #define SOC_PERIPHERAL_IRQ(nr) (nr + 16) #include "sunxi-d1s-t113.dtsi" @@ -115,4 +117,33 @@ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>, <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>; }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths>; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu-crit { + temperature = <100000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; }; diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 895b89a83e75..82cc85acccb1 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -229,6 +229,18 @@ #io-channel-cells = <1>; }; + ths: thermal-sensor@2009400 { + compatible = "allwinner,sun20i-d1-ths"; + reg = <0x2009400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + dmic: dmic@2031000 { compatible = "allwinner,sun20i-d1-dmic", "allwinner,sun50i-h6-dmic"; @@ -489,6 +501,10 @@ reg = <0x3006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x8>; + }; }; crypto: crypto@3040000 { From f1ebfaeee3200b0d12f5f2079c429f0eb1512a79 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Wed, 21 Jan 2026 11:22:37 +0100 Subject: [PATCH 732/757] arm64: dts: rockchip: Add TPS65185 for PineNote As the TPS65185 driver is now upsteram, add it to the PineNote devietrees. This is based on https://ayakael.net/forge/linux-pinenote but modified to the binding requirements. Without any other out-of-tree materials applied, this enables the hwmon temperature reporting and the interrupt counter increments by one per reading. Signed-off-by: Andreas Kemnade Link: https://patch.msgid.link/20260121-rk-tps-v1-1-bc867e1dd200@kemnade.info Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3566-pinenote.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index 5c6f8cc401c9..791719acb9dd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -499,6 +499,40 @@ }; }; }; + + ebc_pmic: pmic@68 { + compatible = "ti,tps65185"; + reg = <0x68>; + interrupt-parent = <&gpio3>; + interrupts = ; + enable-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&ebc_pmic_pins>; + pinctrl-names = "default"; + pwr-good-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + vcom-ctrl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_bat>; + wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + + regulators { + v3p3: v3p3 { + regulator-name = "v3p3"; + /* Keep it always on because IRQ is pulled up against this line */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcom: vcom { + regulator-name = "vcom"; + }; + + vposneg: vposneg { + regulator-name = "vposneg"; + regulator-min-microvolt = <15000000>; + regulator-max-microvolt = <15000000>; + }; + }; + }; }; &i2c5 { @@ -563,6 +597,21 @@ }; }; + ebc-pmic { + ebc_pmic_pins: ebc-pmic-pins { + rockchip,pins = /* wakeup */ + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + /* int */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + /* pwr_good */ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + /* pwrup */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + /* vcom_ctrl */ + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + led { led_pin: led-pin { rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; From 79a3286e61829fc43abdd6e3beb31b24930c7af6 Mon Sep 17 00:00:00 2001 From: Alexey Charkov Date: Wed, 21 Jan 2026 11:42:13 +0400 Subject: [PATCH 733/757] arm64: dts: rockchip: Explicitly request UFS reset pin on RK3576 Rockchip RK3576 UFS controller uses a dedicated pin to reset the connected UFS device, which can operate either in a hardware controlled mode or as a GPIO pin. Power-on default is GPIO mode, but the boot ROM reconfigures it to a hardware controlled mode if it uses UFS to load the next boot stage. Given that existing bindings (and rk3576.dtsi) expect a GPIO-controlled device reset, request the required pin config explicitly. The pin is requested with pull-down enabled, which is in line with the SoC power-on default and helps ensure that the attached UFS chip stays in reset until the driver takes over the control of the respective GPIO line. This doesn't appear to affect Linux, but it does affect U-boot: Before: => md.l 0x2604b398 2604b398: 00000011 00000000 00000000 00000000 ................ < ... snip ... > => ufs init ufshcd-rockchip ufshc@2a2d0000: [RX, TX]: gear=[3, 3], lane[2, 2], pwr[FASTAUTO_MODE, FASTAUTO_MODE], rate = 2 => md.l 0x2604b398 2604b398: 00000011 00000000 00000000 00000000 ................ After: => md.l 0x2604b398 2604b398: 00000011 00000000 00000000 00000000 ................ < ... snip ...> => ufs init ufshcd-rockchip ufshc@2a2d0000: [RX, TX]: gear=[3, 3], lane[2, 2], pwr[FASTAUTO_MODE, FASTAUTO_MODE], rate = 2 => md.l 0x2604b398 2604b398: 00000010 00000000 00000000 00000000 ................ (0x2604b398 is the respective pin mux register, with its BIT0 driving the mode of UFS_RST: unset = GPIO, set = hardware controlled UFS_RST) This helps ensure that GPIO-driven device reset actually fires when the system requests it, not when whatever black box magic inside the UFSHC decides to reset the flash chip. Cc: stable@vger.kernel.org Fixes: c75e5e010fef ("scsi: arm64: dts: rockchip: Add UFS support for RK3576 SoC") Reported-by: Quentin Schulz Reviewed-by: Quentin Schulz Signed-off-by: Alexey Charkov Link: https://patch.msgid.link/20260121-ufs-rst-v3-1-35839bcb4ca7@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi | 7 +++++++ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi index 0b0851a7e4ea..98c9f8013158 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi @@ -5228,6 +5228,13 @@ /* ufs_rstn */ <4 RK_PD0 1 &pcfg_pull_none>; }; + + /omit-if-no-ref/ + ufs_rstgpio: ufs-rstgpio { + rockchip,pins = + /* ufs_rstn */ + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; }; ufs_testdata0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 7286d968e2b0..4d7743dde664 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1865,7 +1865,7 @@ assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; interrupts = ; power-domains = <&power RK3576_PD_USB>; - pinctrl-0 = <&ufs_refclk>; + pinctrl-0 = <&ufs_refclk &ufs_rstgpio>; pinctrl-names = "default"; resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; From 84f42966b80eaec59349c7b474ebd6b0943731e4 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 13 Jan 2026 13:57:19 -0600 Subject: [PATCH 734/757] dt-bindings: arm: rockchip: Add Anbernic RG-DS Add compatible string for the Anbernic RG-DS. Signed-off-by: Chris Morgan Acked-by: Rob Herring (Arm) Link: https://patch.msgid.link/20260113195721.151205-5-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index a494494a6202..ae77ded9fe47 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -60,6 +60,12 @@ properties: - anbernic,rg-arc-s - const: rockchip,rk3566 + - description: Anbernic RK3568 Handheld Gaming Console + items: + - enum: + - anbernic,rg-ds + - const: rockchip,rk3568 + - description: Ariaboard Photonicat items: - const: ariaboard,photonicat From 3c8399d31c8eb10aa34bccec1f49b51694e67b00 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 13 Jan 2026 13:57:20 -0600 Subject: [PATCH 735/757] dt-bindings: input: touchscreen: goodix: Add "panel" property Add a "panel" property to define a relationship between a touchscreen and an associated panel when more than one of each exist in a device. Signed-off-by: Chris Morgan Acked-by: Dmitry Torokhov Acked-by: Rob Herring (Arm) [picked with the rest with Dmitry's Ack] Link: https://patch.msgid.link/20260113195721.151205-6-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/input/touchscreen/goodix.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml index a96137c6f063..a26a54d63a1c 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/goodix.yaml @@ -42,6 +42,8 @@ properties: address, thus it can be driven by the host during the reset sequence. maxItems: 1 + panel: true + reset-gpios: maxItems: 1 From 9e3f8ae040009f66367b2ba1081b7e313b39aeff Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Tue, 13 Jan 2026 13:57:21 -0600 Subject: [PATCH 736/757] arm64: dts: rockchip: Add Anbernic RG-DS Add device tree for the Anbernic RG-DS, based on the Rockchip RK3568. All hardware is currently working except for the accelerometer, the speaker output, and one of the two battery gauges. A bug in the Rockchip VOP2 driver is currently causing the device to pause for 30 seconds at boot and is being investigated. The Anbernic RG-DS includes the following (supported) hardware: - 2 640x480 DSI display screens with touch. - 21 buttons. - 2 Analog joysticks. - 3 LEDs (red and green LED share the same housing). - 32GB eMMC, 1 SDMMC slot. - RTL8821CS WiFi/Bluetooth combo - 1 USB 2.0 port in host mode, 1 USB 2.0 port in peripheral mode. - 3.5mm headphone jack with play button support. - 4000mAH battery The following hardware has incomplete driver support and is not yet working: - An Invensense icm42607p accelerometer. - Two Awinic aw87391 speaker amplifiers. - A Cellwise cw2015 battery monitor, which appears to conflict with the rk817 charger driver at the moment. Co-developed-by: Alexander Weinzerl Signed-off-by: Alexander Weinzerl Signed-off-by: Chris Morgan Link: https://patch.msgid.link/20260113195721.151205-7-macroalpha82@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3568-anbernic-rg-ds.dts | 1237 +++++++++++++++++ 2 files changed, 1238 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 5417f7d6ad98..4d384f153c13 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -135,6 +135,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bigtreetech-pi2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-tinker-board-3s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-9tripod-x3568-v4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-anbernic-rg-ds.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts b/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts new file mode 100644 index 000000000000..6ac1fe0d3c98 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-anbernic-rg-ds.dts @@ -0,0 +1,1237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Anbernic RG DS"; + chassis-type = "handset"; + compatible = "anbernic,rg-ds", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc2; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc_keys_home: adc-keys-home { + compatible = "adc-keys"; + io-channel-names = "buttons"; + io-channels = <&saradc 0>; + keyup-threshold-microvolt = <1800000>; + poll-interval = <60>; + + button-home { + label = "HOME"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + adc_keys_play: adc-keys-play { + compatible = "adc-keys"; + io-channel-names = "buttons"; + io-channels = <&saradc 2>; + keyup-threshold-microvolt = <1300000>; + poll-interval = <60>; + + button-play { + label = "PLAY"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + adc_mux: adc-mux { + compatible = "io-channel-mux"; + channels = "left_x", "right_x", "left_y", "right_y"; + #io-channel-cells = <1>; + io-channels = <&saradc 3>; + io-channel-names = "parent"; + mux-controls = <&gpio_mux>; + settle-time-us = <100>; + }; + + adc-joystick { + compatible = "adc-joystick"; + #address-cells = <1>; + io-channels = <&adc_mux 0>, + <&adc_mux 1>, + <&adc_mux 2>, + <&adc_mux 3>; + pinctrl-0 = <&joy_mux_en>; + pinctrl-names = "default"; + poll-interval = <60>; + #size-cells = <0>; + + axis@0 { + reg = <0>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <1023 15>; + linux,code = ; + }; + + axis@1 { + reg = <1>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = ; + }; + + axis@2 { + reg = <2>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = ; + }; + + axis@3 { + reg = <3>; + abs-flat = <32>; + abs-fuzz = <32>; + abs-range = <15 1023>; + linux,code = ; + }; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + pwms = <&pwm12 0 25000 0>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pwms = <&pwm13 0 25000 0>; + }; + + /* + * Values taken from BSP device-tree except for + * "charge-full-design-microamp-hours" which was set + * incorrectly at 2500000 (based on markings on the battery it + * should be 4000000), "factory-internal-resistance-micro-ohms" + * which was set at 8 but based on context should likely be 80000. + * + * "constant-charge-current-max-microamp" is set at 10 AMPs + * which is likely incorrect but I cannot validate; furthermore + * the onboard charger of the rk817 cannot charge past 3.5A + * anyway. + */ + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <4000000>; + charge-term-current-microamp = <300000>; + constant-charge-current-max-microamp = <10000000>; + constant-charge-voltage-max-microvolt = <4350000>; + factory-internal-resistance-micro-ohms = <80000>; + precharge-current-microamp = <180000>; + precharge-upper-limit-microvolt = <3600000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3000000>; + + /* + * BSP device-tree missing value for 5 percent, so I + * picked a value between 10 and 0. + */ + ocv-capacity-celsius = <20>; + ocv-capacity-table-0 = <4338000 100>, <4251000 95>, + <4191000 90>, <4136000 85>, + <4083000 80>, <4039000 75>, + <3978000 70>, <3947000 65>, + <3908000 60>, <3861000 55>, + <3826000 50>, <3786000 45>, + <3772000 40>, <3761000 35>, + <3749000 30>, <3731000 25>, + <3707000 20>, <3677000 15>, + <3663000 10>, <3446000 5>, + <3400000 0>; + }; + + gpio_keys_control: gpio-keys-control { + compatible = "gpio-keys"; + pinctrl-0 = <&gamepad_keys_l>; + pinctrl-names = "default"; + + button-a { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + label = "EAST"; + linux,code = ; + }; + + button-b { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + label = "SOUTH"; + linux,code = ; + }; + + button-down { + gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = ; + }; + + button-l1 { + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + label = "TL"; + linux,code = ; + }; + + button-l2 { + gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + label = "TL2"; + linux,code = ; + }; + + button-left { + gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = ; + }; + + button-menu { + gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + label = "HOME"; + linux,code = ; + }; + + button-right { + gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = ; + }; + + button-r1 { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + label = "T2"; + linux,code = ; + }; + + button-r2 { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + label = "TR2"; + linux,code = ; + }; + + button-select { + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + label = "SELECT"; + linux,code = ; + }; + + button-start { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + label = "START"; + linux,code = ; + }; + + button-thumbl { + gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; + label = "THUMBL"; + linux,code = ; + }; + + button-thumbr { + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + label = "THUMBR"; + linux,code = ; + }; + + button-up { + gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = ; + }; + + button-x { + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + label = "NORTH"; + linux,code = ; + }; + + button-y { + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + label = "WEST"; + linux,code = ; + }; + }; + + gpio_keys_hall: gpio-keys-hall { + compatible = "gpio-keys"; + pinctrl-0 = <&hall_int_l>; + pinctrl-names = "default"; + + lid-switch { + gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + label = "LID"; + linux,code = ; + linux,input-type = ; + wakeup-event-action = ; + wakeup-source; + }; + }; + + gpio_keys_volume: gpio-keys-volume { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&vol_keys_l>; + pinctrl-names = "default"; + + vol-down-key { + gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + label = "VOLUMEDOWN"; + linux,code = ; + }; + + vol-up-key { + gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + label = "VOLUMEUP"; + linux,code = ; + }; + }; + + gpio_mux: mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + mux-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>, + <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&joy_mux_config>; + pinctrl-names = "default"; + }; + + leds: pwm-leds { + compatible = "pwm-leds"; + + green_led: led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; + max-brightness = <255>; + pwms = <&pwm5 0 25000 0>; + }; + + amber_led: led-1 { + color = ; + function = LED_FUNCTION_CHARGING; + max-brightness = <255>; + pwms = <&pwm6 0 25000 0>; + }; + + red_led: led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + pwms = <&pwm7 0 25000 0>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clock-names = "ext_clock"; + clocks = <&rk817 1>; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-0 = <&hp_det>; + pinctrl-names = "default"; + simple-audio-card,format = "i2s"; + simple-audio-card,hp-det-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rk817_ext"; + simple-audio-card,pin-switches = "Internal Speakers"; + simple-audio-card,routing = + "MICL", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "HPOL", + "Internal Speakers", "HPOR"; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + + simple-audio-card,codec { + sound-dai = <&rk817>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + }; + + vdd_lcd0: regulator-vdd-lcd0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vdd_lcd0_h>; + pinctrl-names = "default"; + regulator-name = "vdd_lcd0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_lcd0: regulator-vccio-lcd0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vccio_lcd0_h>; + pinctrl-names = "default"; + regulator-name = "vccio_lcd0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_lcd1: regulator-vdd-lcd1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vdd_lcd1_h>; + pinctrl-names = "default"; + regulator-name = "vdd_lcd1"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_lcd1: regulator-vccio-lcd1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vccio_lcd1_h>; + pinctrl-names = "default"; + regulator-name = "vccio_lcd1"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: regulator-vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdmmc_pwren_l>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vccio_sd>; + }; + + vcc_sys: regulator-vcc-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-name = "vcc_sys"; + }; + + vibrator: pwm-vibrator { + compatible = "pwm-vibrator"; + pwm-names = "enable"; + pwms = <&pwm14 0 100000 0>; + vcc-supply = <&vcc_sys>; + }; + + vcc_wifi: regulator-vcc-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc_wifi_h>; + pinctrl-names = "default"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_wifi"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&cru { + assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, + <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; + assigned-clock-rates = <32768>, <1200000000>, + <200000000>, <292500000>; +}; + +&dsi0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + dsi0_in: port@0 { + reg = <0>; + dsi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_dsi0>; + }; + }; + + dsi0_out: port@1 { + reg = <1>; + mipi_out_panel0: endpoint { + remote-endpoint = <&mipi_in_panel0>; + }; + }; + }; + + panel0: panel@0 { + compatible = "anbernic,rg-ds-display-bottom", "jadard,jd9365da-h3"; + reg = <0>; + backlight = <&backlight0>; + pinctrl-0 = <&lcd0_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + vdd-supply = <&vdd_lcd0>; + vccio-supply = <&vccio_lcd0>; + + port { + mipi_in_panel0: endpoint { + remote-endpoint = <&mipi_out_panel0>; + }; + }; + }; +}; + +&dsi1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + ports { + dsi1_in: port@0 { + reg = <0>; + dsi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_dsi1>; + }; + }; + + dsi1_out: port@1 { + reg = <1>; + mipi_out_panel1: endpoint { + remote-endpoint = <&mipi_in_panel1>; + }; + }; + }; + + panel1: panel@0 { + compatible = "anbernic,rg-ds-display-top", "jadard,jd9365da-h3"; + reg = <0>; + backlight = <&backlight1>; + pinctrl-0 = <&lcd1_rst>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; + vdd-supply = <&vdd_lcd1>; + vccio-supply = <&vccio_lcd1>; + + port { + mipi_in_panel1: endpoint { + remote-endpoint = <&mipi_out_panel1>; + }; + }; + }; +}; + +&dsi_dphy0 { + status = "okay"; +}; + +&dsi_dphy1 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + clocks = <&cru I2S1_MCLKOUT_TX>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&i2s1m0_mclk &pmic_int_l>; + pinctrl-names = "default"; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <900000>; + regulator-name = "vdd_logic"; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <825000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5400000>; + regulator-min-microvolt = <4700000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk817_charger: charger { + monitored-battery = <&battery>; + rockchip,resistor-sense-micro-ohms = <10000>; + rockchip,sleep-enter-current-microamp = <150000>; + rockchip,sleep-filter-current-microamp = <100000>; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1390000>; + regulator-min-microvolt = <712500>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* + * Currently the rk817_charger and the cw2015 don't work together. + * Disable the cw2015 for now because it performs the same function + * as the rk817_charger for battery monitoring. + */ + cw2015: battery@62 { + compatible = "cellwise,cw2015"; + reg = <0x62>; + cellwise,battery-profile = /bits/ 8 + < 0x17 0x67 0x81 0x6F 0x69 0x65 0x63 0x54 + 0x75 0x50 0x57 0x56 0x4E 0x4F 0x44 0x35 + 0x2C 0x24 0x1E 0x1B 0x24 0x32 0x41 0x4D + 0x1C 0x57 0x0B 0x85 0x34 0x54 0x59 0x6D + 0x85 0x81 0x81 0x84 0x3C 0x1B 0x6C 0x6C + 0x0B 0x41 0x1C 0x4D 0x80 0x95 0xA0 0x14 + 0x38 0x7E 0x98 0xA3 0x80 0x89 0x97 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0xC1 0x46 0xAE>; + cellwise,monitor-interval-ms = <5000>; + monitored-battery = <&battery>; + power-supplies = <&rk817_charger>; + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <200000>; + pinctrl-0 = <&i2c2m1_xfer>; + pinctrl-names = "default"; + status = "okay"; + + /* awinic,aw87391 at 0x58 */ + /* awinic,aw87391 at 0x5b */ + /* invensense,icm42607p at 0x68 */ +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c3m1_xfer>; + pinctrl-names = "default"; + status = "okay"; + + touch1: touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + AVDD28-supply = <&vcc2v8_dvp>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + panel = <&panel1>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <640>; + touchscreen-size-y = <480>; + touchscreen-inverted-x; + touchscreen-inverted-y; + pinctrl-0 = <&touch1_rst &touch1_irq>; + pinctrl-names = "default"; + VDDIO-supply = <&vcc3v3_pmu>; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + status = "okay"; + + touch0: touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + AVDD28-supply = <&vcc2v8_dvp>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + panel = <&panel0>; + reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <640>; + touchscreen-size-y = <480>; + pinctrl-0 = <&touch0_rst &touch0_irq>; + pinctrl-names = "default"; + VDDIO-supply = <&vcc3v3_pmu>; + }; + + /* Unused iSmartWare SW2001 encryption device at 0x3c */ +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_lrcktx &i2s1m0_sdi0 &i2s1m0_sdo0>; + pinctrl-names = "default"; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pinctrl { + gpio-keys { + vol_keys_l: vol-keys_l { + rockchip,pins = + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + gamepad_keys_l: gamepad-keys-l { + rockchip,pins = + <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-lcd { + lcd0_rst: lcd0-rst { + rockchip,pins = + <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd1_rst: lcd1-rst { + rockchip,pins = + <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall-sensor { + hall_int_l: hal-int-l { + rockchip,pins = + <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hp-detect { + hp_det: hp-det { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + joy-mux { + joy_mux_en: joy-mux-en { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + joy_mux_config: joy-mux-config { + rockchip,pins = + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_pwren_l: sdmmc-pwren-l { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch0_rst: touch0-rst { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch0_irq: touch0-irq { + rockchip,pins = + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch1_rst: touch1-rst { + rockchip,pins = + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch1_irq: touch1-irq { + rockchip,pins = + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vcc-lcd { + vdd_lcd0_h: vdd-lcd0-h { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vccio_lcd0_h: vccio-lcd0-h { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vdd_lcd1_h: vdd-lcd1-h { + rockchip,pins = + <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vccio_lcd1_h: vccio-lcd1-h { + rockchip,pins = + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc-wifi { + vcc_wifi_h: vcc-wifi-h { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi-irq { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm5 { + pinctrl-0 = <&pwm5_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm6 { + pinctrl-0 = <&pwm6_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm7 { + pinctrl-0 = <&pwm7_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm13 { + pinctrl-0 = <&pwm13m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + no-sd; + no-sdio; + non-removable; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + pinctrl-names = "default"; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc2 { + #address-cells = <1>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; + pinctrl-names = "default"; + sd-uhs-sdr104; + #size-cells = <0>; + vmmc-supply = <&vcc_wifi>; + status = "okay"; + + sdio_wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio4>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-0 = <&wifi_host_wake_irq>; + pinctrl-names = "default"; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", "realtek,rtl8723bs-bt"; + device-wake-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* No DMA for a debug serial console. */ +&uart2 { + /delete-property/ dmas; + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "peripheral"; + phy-names = "usb2-phy"; + phys = <&usb2phy0_otg>; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&cru PLL_VPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 { + reg = ; + remote-endpoint = <&dsi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dsi1: endpoint@ROCKCHIP_VOP2_EP_MIPI1 { + reg = ; + remote-endpoint = <&dsi1_in_vp1>; + }; +}; From f63ea193a404481f080ca2958f73e9f364682db9 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 5 Jan 2026 16:15:28 +0800 Subject: [PATCH 737/757] arm64: dts: rockchip: Fix rk356x PCIe range mappings The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so that there is no same address allocated from normal system memory. Otherwise it's broken if the same address assigned to the EP for DMA purpose.Fix it to sync with the vendor BSP. Fixes: 568a67e742df ("arm64: dts: rockchip: Fix rk356x PCIe register and range mappings") Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller") Cc: stable@vger.kernel.org Cc: Andrew Powers-Holmes Signed-off-by: Shawn Lin Link: https://patch.msgid.link/1767600929-195341-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index e719a3df126c..658097ed6971 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -185,7 +185,7 @@ <0x0 0xf2000000 0x0 0x00100000>; ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>; + <0x03000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X1_POWERUP>; reset-names = "pipe"; @@ -238,7 +238,7 @@ <0x0 0xf0000000 0x0 0x00100000>; ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>; + <0x03000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>; reg-names = "dbi", "apb", "config"; resets = <&cru SRST_PCIE30X2_POWERUP>; reset-names = "pipe"; diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 8893b7b6cc9f..a2c4957a5899 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -1022,7 +1022,7 @@ power-domains = <&power RK3568_PD_PIPE>; ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, - <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; + <0x03000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; resets = <&cru SRST_PCIE20_POWERUP>; reset-names = "pipe"; #address-cells = <3>; From 46c56b737161060dfa468f25ae699749047902a2 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Mon, 5 Jan 2026 16:15:29 +0800 Subject: [PATCH 738/757] arm64: dts: rockchip: Fix rk3588 PCIe range mappings The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so that there is no same address allocated from normal system memory. Otherwise it's broken if the same address assigned to the EP for DMA purpose.Fix it to sync with the vendor BSP. Fixes: 0acf4fa7f187 ("arm64: dts: rockchip: add PCIe3 support for rk3588") Fixes: 8d81b77f4c49 ("arm64: dts: rockchip: add rk3588 PCIe2 support") Cc: stable@vger.kernel.org Cc: Sebastian Reichel Signed-off-by: Shawn Lin Link: https://patch.msgid.link/1767600929-195341-2-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 4 ++-- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index aa74e8d7b4e9..f79e54c14ff0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -2019,7 +2019,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; reg = <0xa 0x40c00000 0x0 0x00400000>, <0x0 0xfe180000 0x0 0x00010000>, <0x0 0xf3000000 0x0 0x00100000>; @@ -2071,7 +2071,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; reg = <0xa 0x41000000 0x0 0x00400000>, <0x0 0xfe190000 0x0 0x00010000>, <0x0 0xf4000000 0x0 0x00100000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 6e5a58428bba..a2640014ee04 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -375,7 +375,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + <0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; reg = <0xa 0x40000000 0x0 0x00400000>, <0x0 0xfe150000 0x0 0x00010000>, <0x0 0xf0000000 0x0 0x00100000>; @@ -462,7 +462,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + <0x03000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>; reg = <0xa 0x40400000 0x0 0x00400000>, <0x0 0xfe160000 0x0 0x00010000>, <0x0 0xf1000000 0x0 0x00100000>; @@ -512,7 +512,7 @@ power-domains = <&power RK3588_PD_PCIE>; ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, - <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; reg = <0xa 0x40800000 0x0 0x00400000>, <0x0 0xfe170000 0x0 0x00010000>, <0x0 0xf2000000 0x0 0x00100000>; From e9ed88a4ce42bf42cd8b95a5b05298cf225b8b52 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Thu, 22 Jan 2026 14:23:45 -0600 Subject: [PATCH 739/757] ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi This .dtsi file is not included anywhere in the tree and can't be tested. Acked-by: Alexandre Belloni Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20260122202345.3387936-2-robh@kernel.org Signed-off-by: Claudiu Beznea --- .../boot/dts/microchip/usb_a9g20-dab-mmx.dtsi | 93 ------------------- 1 file changed, 93 deletions(-) delete mode 100644 arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi diff --git a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi deleted file mode 100644 index 5b1d80c0ab26..000000000000 --- a/arch/arm/boot/dts/microchip/usb_a9g20-dab-mmx.dtsi +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * calao-dab-mmx.dtsi - Device Tree Include file for Calao DAB-MMX Daughter Board - * - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD - */ - -/ { - ahb { - apb { - usart1: serial@fffb4000 { - status = "okay"; - }; - - usart3: serial@fffd0000 { - status = "okay"; - }; - }; - }; - - i2c-gpio@0 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - - user_led1 { - label = "user_led1"; - gpios = <&pioB 20 GPIO_ACTIVE_LOW>; - }; - -/* -* led already used by mother board but active as high -* user_led2 { -* label = "user_led2"; -* gpios = <&pioB 21 GPIO_ACTIVE_LOW>; -* }; -*/ - user_led3 { - label = "user_led3"; - gpios = <&pioB 22 GPIO_ACTIVE_LOW>; - }; - - user_led4 { - label = "user_led4"; - gpios = <&pioB 23 GPIO_ACTIVE_LOW>; - }; - - red { - label = "red"; - gpios = <&pioB 24 GPIO_ACTIVE_LOW>; - }; - - orange { - label = "orange"; - gpios = <&pioB 30 GPIO_ACTIVE_LOW>; - }; - - green { - label = "green"; - gpios = <&pioB 31 GPIO_ACTIVE_LOW>; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - button-user-pb1 { - label = "user_pb1"; - gpios = <&pioB 25 GPIO_ACTIVE_LOW>; - linux,code = <0x100>; - }; - - button-user-pb2 { - label = "user_pb2"; - gpios = <&pioB 13 GPIO_ACTIVE_LOW>; - linux,code = <0x101>; - }; - - button-user-pb3 { - label = "user_pb3"; - gpios = <&pioA 26 GPIO_ACTIVE_LOW>; - linux,code = <0x102>; - }; - - button-user-pb4 { - label = "user_pb4"; - gpios = <&pioC 9 GPIO_ACTIVE_LOW>; - linux,code = <0x103>; - }; - }; -}; From b3370479a5f7edf4baf0e307f1163f8fe9e09e17 Mon Sep 17 00:00:00 2001 From: Elad Nachman Date: Thu, 22 Jan 2026 18:59:22 +0200 Subject: [PATCH 740/757] arm64: dts: a7k: add COM Express boards Add support for Armada 7020 Express Type 7 CPU module board by Marvell. Define this COM Express CPU module as dtsi and provide a dtsi file for the carrier board (Marvell DB-98CX85x0 COM Express type 7 carrier board). Since memory is soldered on CPU module, memory node is on CPU module dtsi file. This Carrier board only utilizes the PCIe link, hence no special device or driver support is provided by this dtsi file. Devise a dts file for the combined com express carrier and CPU module. The Aramda 7020 CPU COM Express board offers the following features: 1. Armada 7020 CPU, with dual ARM A72 cores 2. DDR4 memory, 8GB, on board soldered 3. 1Gbit Out of Band Ethernet via RGMII to PHY and RJ45 connector, all are present on A7K CPU module (none on the carrier) 4. Optional 10G KR Ethernet going via the COM Express type 7 connector 5. On-board 8 Gbit, 8-bit bus width NAND flash 6. On-board 512 Mbit SPI flash 7. PCIe Root Complex, 4 lanes PCIe gen3 connectivity, going via the COM Express type 7 connector 8. m.2 SATA connector 9. Micro-SD card connector 10. USB 2.0 via COM Express type 7 connector 11. Two i2c interfaces - one to the CPU module, and one to the carrier board via the COM Express type 7 connector 12. UART (mini USB connector by virtue of FT2232D UART to USB converter, connected to the Armada 7020 UART0) gc: 10gbase-kr is legacy, use "10gbase-r" instead in cp0_eth0 node Signed-off-by: Elad Nachman Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/Makefile | 1 + .../dts/marvell/armada-7020-comexpress.dtsi | 161 ++++++++++++++++++ arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 7 + .../boot/dts/marvell/armada-ap806-dual.dtsi | 4 +- .../dts/marvell/db-falcon-carrier-a7k.dts | 27 +++ .../boot/dts/marvell/db-falcon-carrier.dtsi | 22 +++ 6 files changed, 220 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi create mode 100644 arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts create mode 100644 arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile index a774bc74a0a0..09d1544041af 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-espressobin-v7-emmc.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-gl-mv1000.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-turris-mox.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-uDPU.dtb +dtb-$(CONFIG_ARCH_MVEBU) += db-falcon-carrier-a7k.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-mochabin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-clearfog-gt-8k.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi new file mode 100644 index 000000000000..2b5ec4a451e3 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-7020-comexpress.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell Technology Group Ltd. + * + * Device Tree file for Marvell Armada 7020 Com Express CPU module board. + */ + +#include "armada-7020.dtsi" + +/ { + model = "Marvell Armada-7020 COMEXPRESS board setup"; + compatible = "marvell,armada7020-cpu-module", "marvell,armada7020", + "marvell,armada-ap806-dual", "marvell,armada-ap806"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x2 0x00000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &cp0_eth0; + ethernet1 = &cp0_eth1; + }; +}; + +&ap_clk { + status = "okay"; +}; + +&gic { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&spi0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&cp0_mdio { + status = "okay"; + + phy0: ethernet-phy@10 { + reg = <0x10>; + }; +}; + +&cp0_ethernet { + status = "okay"; +}; + +&cp0_eth0 { + status = "okay"; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy4 0>; +}; + +&cp0_eth1 { + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; +}; + +&cp0_usb3_0 { + status = "okay"; +}; + +&cp0_usb3_1 { + status = "okay"; +}; + +&cp0_clk { + status = "okay"; +}; + +&cp0_i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&cp0_nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "main-storage"; + nand-rb = <0>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@200000 { + label = "Linux"; + reg = <0x400000 0x100000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x500000 0x1e00000>; + }; + }; + }; +}; + +&cp0_pcie0 { + status = "okay"; + num-lanes = <4>; + num-viewport = <8>; + + ranges = <0x81000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x00010000 + 0x82000000 0x0 0x00000000 0x0 0xc0000000 0x0 0x30000000>; + + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy0 0 + &cp0_comphy1 0 + &cp0_comphy2 0 + &cp0_comphy3 0>; +}; + +&cp0_sata0 { + /* CPM Lane 0 - U29 */ + status = "okay"; + + sata-port@1 { + status = "okay"; + /* Generic PHY, providing serdes lanes */ + phys = <&cp0_comphy5 1>; + }; +}; + +&cp0_sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; + status = "okay"; + bus-width = <4>; + no-1-8-v; + broken-cd; +}; + diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index df939426d258..36e0a8a0ade3 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -47,6 +47,13 @@ cp0_pinctrl: pinctrl { compatible = "marvell,armada-7k-pinctrl"; + + sdhci_pins: sdhci-pins { + marvell,pins = "mpp56", "mpp57", "mpp58", + "mpp59", "mpp60", "mpp61", "mpp62"; + marvell,function = "sdio"; + }; + nand_pins: nand-pins { marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18", diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi index 82f4dedfc25e..0868d59d561b 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi @@ -54,7 +54,7 @@ }; thermal-zones { - /delete-node/ ap-thermal-cpu2; - /delete-node/ ap-thermal-cpu3; + /delete-node/ ap-cpu2-thermal; + /delete-node/ ap-cpu3-thermal; }; }; diff --git a/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts b/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts new file mode 100644 index 000000000000..5d1ae7b35b62 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/db-falcon-carrier-a7k.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the Falcon DB Type 7 Com Express carrier board, + * Utilizing the Armada 7020 COM Express CPU module board. + * This specific carrier board (DB-98CX8540/80) + * only maintains a PCIe link with the CPU module, + * which does not require any special DTS definitions. + * + * There is no Linux CPU booting in this mode on the carrier, only on the + * Armada 7020 COM Express CPU module. + * What runs the Linux is the Armada 7020 on the COM Express CPU module, + * And it accesses the switch end-point on the Falcon DB portion of the carrier + * via PCIe. + */ + +#include "armada-7020-comexpress.dtsi" +#include "db-falcon-carrier.dtsi" + +/ { + model = "Marvell Falcon DB COM EXPRESS type 7 carrier board with Armada 7020 CPU module"; + compatible = "marvell,armada7020-falcon-carrier", "marvell,db-falcon-carrier", + "marvell,armada7020-cpu-module", "marvell,armada7020", + "marvell,armada-ap806-dual", "marvell,armada-ap806"; + +}; diff --git a/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi b/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi new file mode 100644 index 000000000000..c85ad1547ec5 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/db-falcon-carrier.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Marvell International Ltd. + * + * Device tree for the Falcon DB Type 7 Com Express carrier board, + * This (DB-98CX8540/80) specific carrier board only maintains + * a PCIe link with the COM Express CPU module, which does not + * require any special DTS definitions. + * + * The board contains the 98CX8540/80 Switch, which connects by + * PCIe to the COM Express CPU module. + * This CPU module can be any standard COM Express CPU module with + * PCIe support. + * + * There is no Linux CPU booting in this mode on the carrier, + * only on the COM Express CPU module. + */ + +/ { + model = "Marvell Armada Falcon DB COM EXPRESS type 7 carrier board"; + compatible = "marvell,db-falcon-carrier"; +}; From fcaf733ca526b69595ed1d227e2cc59ddd24eff7 Mon Sep 17 00:00:00 2001 From: Elad Nachman Date: Thu, 22 Jan 2026 18:59:23 +0200 Subject: [PATCH 741/757] MAINTAINERS: Add Falcon DB Add Falcon DB to the list of maintained Marvell Armada dts files Signed-off-by: Elad Nachman Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9d..f502b13643e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2943,6 +2943,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git F: Documentation/devicetree/bindings/arm/marvell/ F: arch/arm/boot/dts/marvell/armada* +F: arch/arm/boot/dts/marvell/db-falcon* F: arch/arm/boot/dts/marvell/kirkwood* F: arch/arm/configs/mvebu_*_defconfig F: arch/arm/mach-mvebu/ From aeec6d68b673aaafbd8951a766b964a6935fe0c5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jan 2026 19:21:17 +0100 Subject: [PATCH 742/757] ARM: dts: nuvoton: Minor whitespace cleanup The DTS code coding style expects exactly one space around '=' character. Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20250819131725.86770-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260117182117.14483-4-krzk@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi index 98c35771534e..ab3c3c5713ae 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi @@ -154,7 +154,7 @@ status = "disabled"; reg = <0xf0842000 0x200>; interrupts = ; - clocks = <&clk NPCM7XX_CLK_AHB>; + clocks = <&clk NPCM7XX_CLK_AHB>; clock-names = "clk_mmc"; pinctrl-names = "default"; pinctrl-0 = <&mmc8_pins @@ -166,7 +166,7 @@ status = "disabled"; reg = <0xf0840000 0x200>; interrupts = ; - clocks = <&clk NPCM7XX_CLK_AHB>; + clocks = <&clk NPCM7XX_CLK_AHB>; clock-names = "clk_sdhc"; pinctrl-names = "default"; pinctrl-0 = <&sd1_pins>; From d5e22ed44b0b8c742acd763125c64a02f169e472 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Sat, 17 Jan 2026 19:22:54 +0100 Subject: [PATCH 743/757] ARM: dts: samsung: Drop s3c6400.dtsi This .dtsi file is not included anywhere in the tree and can't be tested. Signed-off-by: Rob Herring (Arm) Link: https://patch.msgid.link/20251212203226.458694-7-robh@kernel.org Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260117182257.14799-2-krzk@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/samsung/s3c6400.dtsi | 38 -------------------------- 1 file changed, 38 deletions(-) delete mode 100644 arch/arm/boot/dts/samsung/s3c6400.dtsi diff --git a/arch/arm/boot/dts/samsung/s3c6400.dtsi b/arch/arm/boot/dts/samsung/s3c6400.dtsi deleted file mode 100644 index 7cc785a63866..000000000000 --- a/arch/arm/boot/dts/samsung/s3c6400.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C6400 SoC device tree source - * - * Copyright (c) 2013 Tomasz Figa - * - * Samsung's S3C6400 SoC device nodes are listed in this file. S3C6400 - * based board files can include this file and provide values for board specific - * bindings. - * - * Note: This file does not include device nodes for all the controllers in - * S3C6400 SoC. As device tree coverage for S3C6400 increases, additional - * nodes can be added to this file. - */ - -#include "s3c64xx.dtsi" - -/ { - compatible = "samsung,s3c6400"; -}; - -&vic0 { - valid-mask = <0xfffffe1f>; - valid-wakeup-mask = <0x00200004>; -}; - -&vic1 { - valid-mask = <0xffffffff>; - valid-wakeup-mask = <0x53020000>; -}; - -&soc { - clocks: clock-controller@7e00f000 { - compatible = "samsung,s3c6400-clock"; - reg = <0x7e00f000 0x1000>; - #clock-cells = <1>; - }; -}; From d83bcab6842f01bad024056c3801c39f55e61f30 Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Tue, 27 Jan 2026 15:14:00 +0800 Subject: [PATCH 744/757] dt-bindings: arm: realtek: Add Kent Soc family compatibles Define compatible strings for Realtek RTD1501s, RTD1861b and RTD1920s. Additionally, convert legacy DTS-style comments to YAML description properties, following the pattern from the ARM bindings conversion series [1]. [1] https://lore.kernel.org/lkml/20200622125527.24207-2-afaerber@suse.de/ Acked-by: Conor Dooley Signed-off-by: Yu-Chun Lin Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260127071530.25426-2-eleanor15x@gmail.com Signed-off-by: Arnd Bergmann --- .../devicetree/bindings/arm/realtek.yaml | 42 +++++++++++++------ 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/realtek.yaml b/Documentation/devicetree/bindings/arm/realtek.yaml index ddd9a85099e9..be529490640c 100644 --- a/Documentation/devicetree/bindings/arm/realtek.yaml +++ b/Documentation/devicetree/bindings/arm/realtek.yaml @@ -14,21 +14,21 @@ properties: const: '/' compatible: oneOf: - # RTD1195 SoC based boards - - items: + - description: RTD1195 SoC based boards + items: - enum: - mele,x1000 # MeLE X1000 - realtek,horseradish # Realtek Horseradish EVB - const: realtek,rtd1195 - # RTD1293 SoC based boards - - items: + - description: RTD1293 SoC based boards + items: - enum: - synology,ds418j # Synology DiskStation DS418j - const: realtek,rtd1293 - # RTD1295 SoC based boards - - items: + - description: RTD1295 SoC based boards + items: - enum: - mele,v9 # MeLE V9 - probox2,ava # ProBox2 AVA @@ -36,25 +36,43 @@ properties: - zidoo,x9s # Zidoo X9S - const: realtek,rtd1295 - # RTD1296 SoC based boards - - items: + - description: RTD1296 SoC based boards + items: - enum: - synology,ds418 # Synology DiskStation DS418 - const: realtek,rtd1296 - # RTD1395 SoC based boards - - items: + - description: RTD1395 SoC based boards + items: - enum: - bananapi,bpi-m4 # Banana Pi BPI-M4 - realtek,lion-skin # Realtek Lion Skin EVB - const: realtek,rtd1395 - # RTD1619 SoC based boards - - items: + - description: RTD1501s SoC based boards + items: + - enum: + - realtek,phantom # Realtek Phantom EVB (8GB) + - const: realtek,rtd1501s + + - description: RTD1619 SoC based boards + items: - enum: - realtek,mjolnir # Realtek Mjolnir EVB - const: realtek,rtd1619 + - description: RTD1861b SoC based boards + items: + - enum: + - realtek,krypton # Realtek Krypton EVB (8GB) + - const: realtek,rtd1861b + + - description: RTD1920s SoC based boards + items: + - enum: + - realtek,smallville # Realtek Smallville EVB (4GB) + - const: realtek,rtd1920s + additionalProperties: true ... From b095c27fc874ef5e26a025a0ddbdacfc3c94d663 Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Tue, 27 Jan 2026 15:14:01 +0800 Subject: [PATCH 745/757] arm64: dts: realtek: Add Kent SoC and EVB device trees Add Device Tree hierarchy for Realtek Kent SoC family: - kent.dtsi: base SoC layer - rtd.dtsi: SoC variant layer - rtd-.dtsi: board layer - rtd--.dts: board configuration layer Include RTD1501s Phantom EVB (8GB), RTD1861B Krypton EVB (8GB), and RTD1920s Smallville EVB (4GB). Signed-off-by: Yu-Chun Lin Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260127071530.25426-3-eleanor15x@gmail.com Signed-off-by: Arnd Bergmann --- arch/arm64/boot/dts/realtek/Makefile | 7 +- arch/arm64/boot/dts/realtek/kent.dtsi | 166 ++++++++++++++++++ arch/arm64/boot/dts/realtek/rtd1501.dtsi | 12 ++ .../boot/dts/realtek/rtd1501s-phantom-8gb.dts | 25 +++ .../boot/dts/realtek/rtd1501s-phantom.dtsi | 118 +++++++++++++ arch/arm64/boot/dts/realtek/rtd1861.dtsi | 12 ++ .../boot/dts/realtek/rtd1861b-krypton-8gb.dts | 25 +++ .../boot/dts/realtek/rtd1861b-krypton.dtsi | 72 ++++++++ arch/arm64/boot/dts/realtek/rtd1920.dtsi | 12 ++ .../dts/realtek/rtd1920s-smallville-4gb.dts | 23 +++ .../boot/dts/realtek/rtd1920s-smallville.dtsi | 128 ++++++++++++++ 11 files changed, 596 insertions(+), 4 deletions(-) create mode 100644 arch/arm64/boot/dts/realtek/kent.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1501.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1861.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1920.dtsi create mode 100644 arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts create mode 100644 arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi diff --git a/arch/arm64/boot/dts/realtek/Makefile b/arch/arm64/boot/dts/realtek/Makefile index ef8d8fcbaa05..60a37d5a948c 100644 --- a/arch/arm64/boot/dts/realtek/Makefile +++ b/arch/arm64/boot/dts/realtek/Makefile @@ -1,15 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_REALTEK) += rtd1293-ds418j.dtb - dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-mele-v9.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-probox2-ava.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-xnano-x5.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb - dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb - dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb - +dtb-$(CONFIG_ARCH_REALTEK) += rtd1501s-phantom-8gb.dtb dtb-$(CONFIG_ARCH_REALTEK) += rtd1619-mjolnir.dtb +dtb-$(CONFIG_ARCH_REALTEK) += rtd1861b-krypton-8gb.dtb +dtb-$(CONFIG_ARCH_REALTEK) += rtd1920s-smallville-4gb.dtb diff --git a/arch/arm64/boot/dts/realtek/kent.dtsi b/arch/arm64/boot/dts/realtek/kent.dtsi new file mode 100644 index 000000000000..ae006ce24420 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/kent.dtsi @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek Kent SoC family + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&l2_0>; + dynamic-power-coefficient = <454>; + #cooling-cells = <2>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <256>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&l2_1>; + dynamic-power-coefficient = <454>; + #cooling-cells = <2>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <256>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x200>; + enable-method = "psci"; + next-level-cache = <&l2_2>; + dynamic-power-coefficient = <454>; + #cooling-cells = <2>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <256>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x300>; + enable-method = "psci"; + next-level-cache = <&l2_3>; + dynamic-power-coefficient = <454>; + #cooling-cells = <2>; + + l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-line-size = <64>; + cache-sets = <256>; + cache-size = <0x40000>; + cache-unified; + next-level-cache = <&l3>; + }; + }; + + l3: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-line-size = <64>; + cache-sets = <512>; + cache-size = <0x200000>; + cache-unified; + }; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x40000>, /* boot code */ + <0x98000000 0x0 0x98000000 0xef0000>, /* rbus */ + <0xa0000000 0x0 0xa0000000 0x10000000>, /* PCIE */ + <0xff000000 0x0 0xff000000 0x200000>; /* GIC */ + #address-cells = <1>; + #size-cells = <1>; + + rbus: bus@98000000 { + compatible = "simple-bus"; + ranges = <0x0 0x98000000 0xef0000>, + <0xa0000000 0xa0000000 0x10000000>; /* PCIE */ + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@7800 { + compatible = "snps,dw-apb-uart"; + reg = <0x7800 0x100>; + clock-frequency = <432000000>; + interrupts = ; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + reg = <0xff100000 0x10000>, + <0xff140000 0x80000>; + interrupt-controller; + interrupts = ; + #address-cells = <1>; + #interrupt-cells = <3>; + #size-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501.dtsi b/arch/arm64/boot/dts/realtek/rtd1501.dtsi new file mode 100644 index 000000000000..65f7ede3df73 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts b/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts new file mode 100644 index 000000000000..09e544acfd34 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom-8gb.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501S Phantom EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1501s-phantom.dtsi" + +/ { + compatible = "realtek,phantom", "realtek,rtd1501s"; + model = "Realtek Phantom EVB Chromium (8GB)"; + + memory@40000 { + device_type = "memory"; + reg = <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa0600000 0x0 0x5ea00000>, + <0x1 0x0 0x0 0xa0000000>, + <0x1 0xa0600000 0x0 0x5fa00000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi b/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi new file mode 100644 index 000000000000..bcfb96799671 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1501s-phantom.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1501S Phantom EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include +#include "rtd1501.dtsi" + +/ { + chosen { + stdout-path = "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0x20000000>; + size = <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp800: opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <830000 830000 1100000>; + }; + + opp900: opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <850000 850000 1100000>; + }; + + opp1000: opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <870000 870000 1100000>; + }; + + opp1100: opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <890000 890000 1100000>; + }; + + opp1200: opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <910000 910000 1100000>; + }; + + opp1300: opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <930000 930000 1100000>; + }; + + opp1400: opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <950000 950000 1100000>; + }; + + opp1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <970000 970000 1100000>; + }; + + opp1600: opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <990000 990000 1100000>; + opp-suspend; + }; + + opp1700: opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1010000 1010000 1100000>; + }; + + opp1800: opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1030000 1030000 1100000>; + }; + + opp1900: opp-1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1050000 1050000 1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861.dtsi b/arch/arm64/boot/dts/realtek/rtd1861.dtsi new file mode 100644 index 000000000000..44c3de8f1f48 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts b/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts new file mode 100644 index 000000000000..9c23d901c49c --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton-8gb.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861B Krypton EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1861b-krypton.dtsi" + +/ { + compatible = "realtek,krypton", "realtek,rtd1861b"; + model = "Realtek Krypton EVB (8GB)"; + + memory@40000 { + device_type = "memory"; + reg = <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa0600000 0x0 0x5ea00000>, + <0x1 0x0 0x0 0xa0000000>, + <0x1 0xa0600000 0x0 0x5fa00000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi b/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi new file mode 100644 index 000000000000..b500f4d2c502 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1861b-krypton.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1861B Krypton EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1861.dtsi" + +/ { + chosen { + stdout-path = "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0x20000000>; + size = <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp1200: opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <900000>; + }; + + opp1600: opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <1000000>; + opp-suspend; + }; + + opp1800: opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1050000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920.dtsi b/arch/arm64/boot/dts/realtek/rtd1920.dtsi new file mode 100644 index 000000000000..becf546216e9 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920 SoC + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +#include "kent.dtsi" + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts b/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts new file mode 100644 index 000000000000..9fd6976e0d9b --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville-4gb.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920S Smallville EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include "rtd1920s-smallville.dtsi" + +/ { + compatible = "realtek,smallville", "realtek,rtd1920s"; + model = "Realtek Smallville EVB (4GB)"; + + memory@40000 { + device_type = "memory"; + reg = <0x0 0x50000 0x0 0x7ffb0000>, + <0x0 0x8a100000 0x0 0xdef0000>, + <0x0 0x98700000 0x0 0x7900000>, + <0x0 0xa1000000 0x0 0x5e000000>; + }; +}; diff --git a/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi b/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi new file mode 100644 index 000000000000..3db8fcea6447 --- /dev/null +++ b/arch/arm64/boot/dts/realtek/rtd1920s-smallville.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Realtek RTD1920S Smallville EVB + * + * Copyright (c) 2024 Realtek Semiconductor Corp. + */ + +/dts-v1/; + +#include +#include "rtd1920.dtsi" + +/ { + chosen { + stdout-path = "serial0:460800n8"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + protected_mem: protected-mem@50000 { + reg = <0x0 0x50000 0x0 0xbf0000>; + no-map; + }; + + metadata: metadata@c40000 { + reg = <0x0 0xc40000 0x0 0x3c4000>; + no-map; + }; + + linux,cma { + compatible = "shared-dma-pool"; + alignment = <0x0 0x400000>; + alloc-ranges = <0x0 0x0 0x0 0x20000000>; + size = <0x0 0x2000000>; + reusable; + linux,cma-default; + }; + }; + + cpu_opps: opp-table-cpu { + compatible = "operating-points-v2"; + opp-shared; + + opp800: opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <830000 830000 1100000>; + }; + + opp900: opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <850000 850000 1100000>; + }; + + opp1000: opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <870000 870000 1100000>; + }; + + opp1100: opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <890000 890000 1100000>; + }; + + opp1200: opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <910000 910000 1100000>; + }; + + opp1300: opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <930000 930000 1100000>; + }; + + opp1400: opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <950000 950000 1100000>; + }; + + opp1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <970000 970000 1100000>; + }; + + opp1600: opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <990000 990000 1100000>; + opp-suspend; + }; + + opp1700: opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <1010000 1010000 1100000>; + }; + + opp1800: opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1030000 1030000 1100000>; + }; + + opp1900: opp-1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1050000 1050000 1100000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opps>; + #cooling-cells = <2>; +}; From 8c4caab05ff162e2dd9b66a72a21d9605fb143cf Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Wed, 3 Dec 2025 07:47:35 +0800 Subject: [PATCH 746/757] arm64: dts: socfpga: agilex5: Add dma-coherent property Add the `dma-coherent` property to these device nodes to inform the kernel and DMA subsystem that the devices support hardware-managed cache coherence. Changes: - Add `dma-coherent` to `cdns,hp-nfc` - Add `dma-coherent` to both `snps,axi-dma-1.01a` instances (dmac0, dmac1) This aligns the Agilex5 device tree with the coherent DMA-capable devices accordingly. Signed-off-by: Khairul Anuar Romli Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index a5c2025a616e..89a2ff59554b 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -312,6 +312,7 @@ clock-names = "nf_clk"; cdns,board-delay-ps = <4830>; iommus = <&smmu 4>; + dma-coherent; status = "disabled"; }; @@ -339,6 +340,7 @@ snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; iommus = <&smmu 8>; + dma-coherent; }; dmac1: dma-controller@10dc0000 { @@ -357,6 +359,7 @@ snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; iommus = <&smmu 9>; + dma-coherent; }; rst: rstmgr@10d11000 { From 2bd42d859b093e3a4c71258767c3cac298265993 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Tue, 2 Dec 2025 18:16:51 +0800 Subject: [PATCH 747/757] dt-bindings: intel: Add Agilex5 SoCFPGA modular board Add compatible for Agilex5 SoCFPGA modular board. Signed-off-by: Niravkumar L Rabara Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index c918837bd41c..6b2d88947352 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -32,6 +32,7 @@ properties: - enum: - intel,socfpga-agilex5-socdk - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 From ebb6a68a4857107f3574ef058f2b83f3288d0d08 Mon Sep 17 00:00:00 2001 From: Niravkumar L Rabara Date: Tue, 2 Dec 2025 18:16:52 +0800 Subject: [PATCH 748/757] arm64: dts: socfpga: agilex5: add support for modular board The Agilex5 Modular board consists of a compute module (Agilex5 SoCFPGA) attached to a carrier board that provides PCIe and additional system interfaces. Signed-off-by: Niravkumar L Rabara Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + .../intel/socfpga_agilex5_socdk_modular.dts | 109 ++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index a117268267ee..b15e9c5083b6 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_013b.dtb \ + socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts new file mode 100644 index 000000000000..1831402d8808 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, Altera Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK - Modular development kit"; + compatible = "intel,socfpga-agilex5-socdk-modular", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "hps_led0"; + gpios = <&porta 0x0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "micron,mt25qu02g", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0be00000>; + }; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; From 67c1d7894766d3a503e6c48c729f17a9a9dea32c Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Wed, 3 Dec 2025 18:29:00 -0800 Subject: [PATCH 749/757] arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes To enable SMMU integration, populate the iommus property to the ethernet device-tree node. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 89a2ff59554b..db8d5c426821 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -568,6 +568,7 @@ snps,tso; altr,sysmgr-syscon = <&sysmgr 0x44 0>; snps,clk-csr = <0>; + iommus = <&smmu 1>; status = "disabled"; stmmac_axi_emac0_setup: stmmac-axi-config { @@ -680,6 +681,7 @@ snps,tso; altr,sysmgr-syscon = <&sysmgr 0x48 0>; snps,clk-csr = <0>; + iommus = <&smmu 2>; status = "disabled"; stmmac_axi_emac1_setup: stmmac-axi-config { @@ -792,6 +794,7 @@ snps,tso; altr,sysmgr-syscon = <&sysmgr 0x4c 0>; snps,clk-csr = <0>; + iommus = <&smmu 3>; status = "disabled"; stmmac_axi_emac2_setup: stmmac-axi-config { From 1cb8486ac5f3adc0a4f38e8b59962c2314fc2ca5 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 10 Dec 2025 21:59:39 -0600 Subject: [PATCH 750/757] dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml For all SoCFPGA platforms, whether it has the "intel" or "altr" vendor prefix are referring to the same business unit that is responsible for the platform. And now that Altera has spun off to be a separate corporate entity from Intel, it would make sense to have the device bindings documentation in the same file. Move the Intel AgileX board binding documentations into the same file that contains the Altera ones. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/arm/altera.yaml | 26 ++++++++++++ .../bindings/arm/intel,socfpga.yaml | 41 ------------------- 2 files changed, 26 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/intel,socfpga.yaml diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index db61537b7115..26ab75bc6ed3 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -9,6 +9,9 @@ title: Altera's SoCFPGA platform maintainers: - Dinh Nguyen +description: + Altera/Intel boards with ARM 32/64 bits cores + properties: $nodename: const: "/" @@ -81,6 +84,29 @@ properties: - altr,socfpga-stratix10-swvp - const: altr,socfpga-stratix10 + - description: AgileX boards + items: + - enum: + - intel,n5x-socdk + - intel,socfpga-agilex-n6000 + - intel,socfpga-agilex-socdk + - const: intel,socfpga-agilex + + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex3 + - const: intel,socfpga-agilex5 + + - description: Agilex5 boards + items: + - enum: + - intel,socfpga-agilex5-socdk + - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-nand + - const: intel,socfpga-agilex5 + - description: SoCFPGA VT items: - const: altr,socfpga-vt diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml deleted file mode 100644 index 6b2d88947352..000000000000 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel SoCFPGA platform - -maintainers: - - Dinh Nguyen - -properties: - $nodename: - const: "/" - compatible: - oneOf: - - description: AgileX boards - items: - - enum: - - intel,n5x-socdk - - intel,socfpga-agilex-n6000 - - intel,socfpga-agilex-socdk - - const: intel,socfpga-agilex - - description: Agilex3 boards - items: - - enum: - - intel,socfpga-agilex3-socdk - - const: intel,socfpga-agilex3 - - const: intel,socfpga-agilex5 - - description: Agilex5 boards - items: - - enum: - - intel,socfpga-agilex5-socdk - - intel,socfpga-agilex5-socdk-013b - - intel,socfpga-agilex5-socdk-modular - - intel,socfpga-agilex5-socdk-nand - - const: intel,socfpga-agilex5 - -additionalProperties: true - -... From 5acb925409e2f089e6e25212ae64d13dea6b464a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 23 Dec 2025 16:24:45 +0100 Subject: [PATCH 751/757] arm64: dts: altera: Use lowercase hex The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../boot/dts/altera/socfpga_stratix10.dtsi | 2 +- .../dts/altera/socfpga_stratix10_socdk.dts | 2 +- .../altera/socfpga_stratix10_socdk_nand.dts | 4 +- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 48 +++++++++---------- .../boot/dts/intel/socfpga_agilex_socdk.dts | 2 +- .../boot/dts/intel/socfpga_n5x_socdk.dts | 4 +- 6 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 657e986e5dba..0d9cad0c0351 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -382,7 +382,7 @@ pinctrl0: pinctrl@ffd13000 { compatible = "pinctrl-single"; - reg = <0xffd13000 0xA0>; + reg = <0xffd13000 0xa0>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x0000000f>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 58f776e411fc..4ae18a013bbe 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -192,7 +192,7 @@ root: partition@4200000 { label = "Root Filesystem - UBIFS"; - reg = <0x04200000 0x0BE00000>; + reg = <0x04200000 0x0be00000>; }; }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index 92954c5beb54..7951ce46ae1f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -174,12 +174,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x03fe0000>; }; qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + reg = <0x03fe0000 0x0c020000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index db8d5c426821..a98bd23c3fa2 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -622,31 +622,31 @@ snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -735,31 +735,31 @@ snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -848,31 +848,31 @@ snps,dcb-algorithm; }; queue1 { - snps,weight = <0x0A>; + snps,weight = <0x0a>; snps,dcb-algorithm; }; queue2 { - snps,weight = <0x0B>; + snps,weight = <0x0b>; snps,coe-unsupported; snps,dcb-algorithm; }; queue3 { - snps,weight = <0x0C>; + snps,weight = <0x0c>; snps,coe-unsupported; snps,dcb-algorithm; }; queue4 { - snps,weight = <0x0D>; + snps,weight = <0x0d>; snps,coe-unsupported; snps,dcb-algorithm; }; queue5 { - snps,weight = <0x0E>; + snps,weight = <0x0e>; snps,coe-unsupported; snps,dcb-algorithm; }; queue6 { - snps,weight = <0x0F>; + snps,weight = <0x0f>; snps,coe-unsupported; snps,dcb-algorithm; }; @@ -918,24 +918,24 @@ pmu0_tbu3: pmu@160a2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160A2000 0x1000>, - <0x160B2000 0x1000>; + reg = <0x160a2000 0x1000>, + <0x160b2000 0x1000>; interrupt-parent = <&intc>; interrupts = ; }; pmu0_tbu4: pmu@160c2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160C2000 0x1000>, - <0x160D2000 0x1000>; + reg = <0x160c2000 0x1000>, + <0x160d2000 0x1000>; interrupt-parent = <&intc>; interrupts = ; }; pmu0_tbu5: pmu@160e2000 { compatible = "arm,smmu-v3-pmcg"; - reg = <0x160E2000 0x1000>, - <0x160F2000 0x1000>; + reg = <0x160e2000 0x1000>, + <0x160f2000 0x1000>; interrupt-parent = <&intc>; interrupts = ; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 9ee312bae8d2..8f8a5423ba02 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -131,7 +131,7 @@ root: partition@4200000 { label = "Root Filesystem - UBIFS"; - reg = <0x04200000 0x0BE00000>; + reg = <0x04200000 0x0be00000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 0034a4897220..d7d500f50a07 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -103,12 +103,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x03fe0000>; }; qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + reg = <0x03fe0000 0x0c020000>; }; }; }; From 42918d28cb47f1907daa843a68c2abb801f57761 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 26 Dec 2025 07:05:40 -0600 Subject: [PATCH 752/757] dt-bindings: altera: document syscon as fallback for sys-mgr For 32-bit Altera SoCFPGA parts, the sys-mgr uses the syscon as a fallback. This change addresses this warning from dtbs_check: sysmgr@ffd08000 (altr,sys-mgr): compatible: 'oneOf' conditional failed, one must be fixed: ['altr,sys-mgr', 'syscon'] is too long 'altr,sys-mgr-s10' was expected 'altr,sys-mgr' was expected from schema $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml Acked-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- .../devicetree/bindings/soc/altera/altr,sys-mgr.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml b/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml index d56ff4c05ae5..2dd3395f3f63 100644 --- a/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml +++ b/Documentation/devicetree/bindings/soc/altera/altr,sys-mgr.yaml @@ -13,7 +13,9 @@ properties: compatible: oneOf: - description: Cyclone5/Arria5/Arria10 - const: altr,sys-mgr + items: + - const: altr,sys-mgr + - const: syscon - description: Stratix10 SoC items: - const: altr,sys-mgr-s10 @@ -45,7 +47,7 @@ additionalProperties: false examples: - | sysmgr@ffd08000 { - compatible = "altr,sys-mgr"; + compatible = "altr,sys-mgr", "syscon"; reg = <0xffd08000 0x1000>; cpu1-start-addr = <0xffd080c4>; }; From 6ba5f9b4241b83dd57fe20a63fd66b6273aa95b1 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 26 Dec 2025 15:31:16 -0600 Subject: [PATCH 753/757] ARM: dts: socfpga: add #address-cells and #size-cells for sram node Add #address-cells and #size-cells for sram node to fix below DTB_CHECK warnings: socfpga_arria5_socdk.dtb: sram@ffff0000 (mmio-sram): '#size-cells' is a required property from schema $id: http://devicetree.org/schemas/sram/sram.yaml Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 3 +++ arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 35be14150f41..58d9fd0c34f0 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -785,6 +785,9 @@ ocram: sram@ffff0000 { compatible = "mmio-sram"; reg = <0xffff0000 0x10000>; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges; }; qspi: spi@ff705000 { diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index b108265e9bde..4df2b98a3e59 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -686,6 +686,9 @@ ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; }; eccmgr: eccmgr { From e0f489a52a1a5f9a9ce745feec95d0b517b8d6e9 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sat, 27 Dec 2025 16:14:08 -0600 Subject: [PATCH 754/757] ARM: dts: socfpga: fix dtbs_check warning for fpga-region soc (simple-bus): base_fpga_region: 'ranges' is a required property from schema $id: http://devicetree.org/schemas/simple-bus.yaml base_fpga_region (fpga-region): $nodename:0: 'base_fpga_region' does not match '^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$' from schema $id: http://devicetree.org/schemas/fpga/fpga-region.yaml Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 3 ++- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi index 58d9fd0c34f0..5dc8d33e8ad7 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi @@ -87,12 +87,13 @@ }; }; - base_fpga_region { + base_fpga_region: fpga-region { compatible = "fpga-region"; fpga-mgr = <&fpgamgr0>; #address-cells = <0x1>; #size-cells = <0x1>; + ranges; }; can0: can@ffc00000 { diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 4df2b98a3e59..a53a94678df2 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -80,12 +80,13 @@ }; }; - base_fpga_region { + base_fpga_region: fpga-region { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "fpga-region"; fpga-mgr = <&fpga_mgr>; + ranges; }; clkmgr@ffd04000 { From 4e6e93dfd501a16650806e7a39aa7b5203867276 Mon Sep 17 00:00:00 2001 From: Khairul Anuar Romli Date: Mon, 29 Dec 2025 11:49:02 +0800 Subject: [PATCH 755/757] arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node Move dma-controller node under simple-bus node to allow bus node specific property able to be properly defined. This is require to fulfill Agilex5 bus limitation that is limited to 40-addressable-bit. Update the compatible string for the DMA controller nodes in the Agilex5 device tree from the generic "snps,axi-dma-1.01a" to the platform-specific "altr,agilex5-axi-dma". Add fallback capability to ensure driver is able to initialize properly. This change enables the use of platform-specific features and constraints in the driver, such as setting a 40-bit DMA addressable mask through dma-ranges, which is required for Agilex5. It also aligns with the updated device tree bindings and driver support for this compatible string. Signed-off-by: Khairul Anuar Romli Signed-off-by: Dinh Nguyen --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 78 ++++++++++--------- 1 file changed, 43 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index a98bd23c3fa2..352c96d144a8 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -324,42 +324,50 @@ #size-cells = <1>; }; - dmac0: dma-controller@10db0000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x10db0000 0x500>; - clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, - <&clkmgr AGILEX5_L4_MP_CLK>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = ; - #dma-cells = <1>; - dma-channels = <4>; - snps,dma-masters = <1>; - snps,data-width = <2>; - snps,block-size = <32767 32767 32767 32767>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <8>; - iommus = <&smmu 8>; - dma-coherent; - }; + dma: dma-bus@10db0000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <2>; + ranges = <0x00 0x10db0000 0x00 0x20000>; + dma-ranges = <0x00 0x00 0x100 0x00>; - dmac1: dma-controller@10dc0000 { - compatible = "snps,axi-dma-1.01a"; - reg = <0x10dc0000 0x500>; - clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, - <&clkmgr AGILEX5_L4_MP_CLK>; - clock-names = "core-clk", "cfgr-clk"; - interrupt-parent = <&intc>; - interrupts = ; - #dma-cells = <1>; - dma-channels = <4>; - snps,dma-masters = <1>; - snps,data-width = <2>; - snps,block-size = <32767 32767 32767 32767>; - snps,priority = <0 1 2 3>; - snps,axi-max-burst-len = <8>; - iommus = <&smmu 9>; - dma-coherent; + dmac0: dma-controller@0 { + compatible = "altr,agilex5-axi-dma", + "snps,axi-dma-1.01a"; + reg = <0x0 0x0 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = ; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + iommus = <&smmu 8>; + }; + + dmac1: dma-controller@10000 { + compatible = "altr,agilex5-axi-dma", + "snps,axi-dma-1.01a"; + reg = <0x10000 0x0 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = ; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + iommus = <&smmu 9>; + }; }; rst: rstmgr@10d11000 { From 95cc767d6f54e48629b593edc2ccbd154ec65d95 Mon Sep 17 00:00:00 2001 From: Ng Tze Yee Date: Sun, 25 Jan 2026 22:42:05 -0800 Subject: [PATCH 756/757] arm64: dts: socfpga: agilex: add emmc support The Agilex devkit supports a separate eMMC daughter card. The eMMC daughter card replaces the SDMMC slot that is on the default daughter card and thus requires a separate board dts file. Signed-off-by: Ng Tze Yee Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + .../dts/intel/socfpga_agilex_socdk_emmc.dts | 105 ++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index b15e9c5083b6..33fcc55d0cb9 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ + socfpga_agilex_socdk_emmc.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts new file mode 100644 index 000000000000..1d3a2d7d48c0 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_emmc.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Altera Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model = "SoCFPGA Agilex SoCDK eMMC daughter board"; + compatible = "intel,socfpga-agilex-socdk-emmc", "intel,socfpga-agilex"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0x80000000 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + /* PHY delays is configured via skew properties */ + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@4 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&mmc { + status = "okay"; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; From 4d904af4d6ce29b9240ebecd35e31458d08cd577 Mon Sep 17 00:00:00 2001 From: Ng Tze Yee Date: Fri, 30 Jan 2026 09:46:57 -0600 Subject: [PATCH 757/757] dt-bindings: intel: Add Agilex eMMC support Agilex devkit support a separate eMMC daughter card. Document Agilex eMMC daughter board compatible. [dinguyen] becauce of patch 1cb8486ac5f3 ("dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml"), I moved the change to altera.yaml file. Acked-by: Krzysztof Kozlowski Signed-off-by: Ng Tze Yee Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 26ab75bc6ed3..13a3a9696821 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -90,6 +90,7 @@ properties: - intel,n5x-socdk - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk + - intel,socfpga-agilex-socdk-emmc - const: intel,socfpga-agilex - description: Agilex3 boards