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drm/amdgpu: Move in_gpu_reset into reset_domain
We should have a single instance per entrire reset domain. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://www.spinics.net/lists/amd-gfx/msg74116.html
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@@ -3554,7 +3554,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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mutex_init(&adev->mn_lock);
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mutex_init(&adev->virt.vf_errors.lock);
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hash_init(adev->mn_hash);
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atomic_set(&adev->in_gpu_reset, 0);
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mutex_init(&adev->psp.mutex);
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mutex_init(&adev->notifier_lock);
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@@ -4829,7 +4828,7 @@ end:
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static void amdgpu_device_lock_adev(struct amdgpu_device *adev,
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struct amdgpu_hive_info *hive)
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{
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atomic_set(&adev->in_gpu_reset, 1);
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atomic_set(&adev->reset_domain->in_gpu_reset, 1);
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if (hive) {
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down_write_nest_lock(&adev->reset_domain->sem, &hive->hive_lock);
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@@ -4854,7 +4853,7 @@ static void amdgpu_device_unlock_adev(struct amdgpu_device *adev)
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{
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amdgpu_vf_error_trans_all(adev);
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adev->mp1_state = PP_MP1_STATE_NONE;
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atomic_set(&adev->in_gpu_reset, 0);
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atomic_set(&adev->reset_domain->in_gpu_reset, 0);
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up_write(&adev->reset_domain->sem);
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}
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@@ -5699,6 +5698,11 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
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amdgpu_asic_invalidate_hdp(adev, ring);
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}
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int amdgpu_in_reset(struct amdgpu_device *adev)
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{
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return atomic_read(&adev->reset_domain->in_gpu_reset);
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}
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/**
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* amdgpu_device_halt() - bring hardware to some kind of halt state
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*
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