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drm/amd/display: Remove DCE12 guards

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Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
2017-06-15 16:21:43 -04:00
parent 7fc6ff772b
commit 8fa9ca2ec6
45 changed files with 16 additions and 175 deletions
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4
drivers/gpu/drm/amd/display/dc/dm_services.h
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@@ -192,7 +192,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx,
unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
const char *func_name);
#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
/* These macros need to be used with soc15 registers in order to retrieve
* the actual offset.
@@ -274,7 +273,6 @@ static inline bool wait_reg_func(
20000,\
200000)
#endif
/**************************************
* Power Play (PP) interfaces
**************************************/
@@ -337,11 +335,9 @@ bool dm_pp_notify_wm_clock_changes(
const struct dc_context *ctx,
struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);
#if defined(CONFIG_DRM_AMD_DC_DCE12_0)
bool dm_pp_notify_wm_clock_changes_soc15(
const struct dc_context *ctx,
struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
#endif
/* DAL calls this function to notify PP about completion of Mode Set.
* For PP it means that current DCE clocks are those which were returned