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drm/amd/amdgpu: Add ISP driver support
Add the isp driver in amdgpu to support ISP device on the APUs that supports ISP IP block. ISP hw block is used for camera front-end, pre and post processing operations. Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Pratap Nirujogi
committed by
Alex Deucher
Alex Deucher
parent
772e4d56da
commit
8fcbfd53ea
278
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
Normal file
278
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
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@@ -0,0 +1,278 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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#include <linux/firmware.h>
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#include <linux/mfd/core.h>
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#include "amdgpu.h"
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#include "amdgpu_isp.h"
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#define mmDAGB0_WRCLI5_V4_1 0x6811C
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#define mmDAGB0_WRCLI9_V4_1 0x6812C
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#define mmDAGB0_WRCLI10_V4_1 0x68130
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#define mmDAGB0_WRCLI14_V4_1 0x68140
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#define mmDAGB0_WRCLI19_V4_1 0x68154
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#define mmDAGB0_WRCLI20_V4_1 0x68158
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static int isp_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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adev->isp.parent = adev->dev;
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adev->isp.cgs_device = amdgpu_cgs_create_device(adev);
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if (!adev->isp.cgs_device)
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return -EINVAL;
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return 0;
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}
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static int isp_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->isp.cgs_device)
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amdgpu_cgs_destroy_device(adev->isp.cgs_device);
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return 0;
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}
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/**
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* isp_hw_init - start and test isp block
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*
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* @handle: handle for amdgpu_device pointer
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*
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*/
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static int isp_hw_init(void *handle)
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{
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int r;
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u64 isp_base;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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const struct amdgpu_ip_block *ip_block =
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amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ISP);
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if (!ip_block)
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return -EINVAL;
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if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
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return -EINVAL;
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isp_base = adev->rmmio_base;
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adev->isp.isp_cell = kcalloc(1, sizeof(struct mfd_cell), GFP_KERNEL);
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if (!adev->isp.isp_cell) {
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r = -ENOMEM;
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DRM_ERROR("%s: isp mfd cell alloc failed\n", __func__);
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goto failure;
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}
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adev->isp.isp_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL);
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if (!adev->isp.isp_res) {
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r = -ENOMEM;
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DRM_ERROR("%s: isp mfd res alloc failed\n", __func__);
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goto failure;
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}
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adev->isp.isp_pdata = kzalloc(sizeof(*adev->isp.isp_pdata), GFP_KERNEL);
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if (!adev->isp.isp_pdata) {
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r = -ENOMEM;
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DRM_ERROR("%s: isp platform data alloc failed\n", __func__);
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goto failure;
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}
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/* initialize isp platform data */
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adev->isp.isp_pdata->adev = (void *)adev;
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adev->isp.isp_pdata->asic_type = adev->asic_type;
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adev->isp.isp_pdata->base_rmmio_size = adev->rmmio_size;
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adev->isp.isp_res[0].name = "isp_reg";
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adev->isp.isp_res[0].flags = IORESOURCE_MEM;
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adev->isp.isp_res[0].start = isp_base;
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adev->isp.isp_res[0].end = isp_base + ISP_REGS_OFFSET_END;
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adev->isp.isp_cell[0].name = "amd_isp_capture";
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adev->isp.isp_cell[0].num_resources = 1;
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adev->isp.isp_cell[0].resources = &adev->isp.isp_res[0];
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adev->isp.isp_cell[0].platform_data = adev->isp.isp_pdata;
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adev->isp.isp_cell[0].pdata_size = sizeof(struct isp_platform_data);
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r = mfd_add_hotplug_devices(adev->isp.parent, adev->isp.isp_cell, 1);
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if (r) {
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DRM_ERROR("%s: add mfd hotplug device failed\n", __func__);
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goto failure;
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}
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/*
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* Temporary WA added to disable MMHUB TLSi until the GART initialization
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* is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory
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* using the TLSi path
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*/
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cgs_write_register(adev->isp.cgs_device, mmDAGB0_WRCLI5_V4_1 >> 2, 0xFE5FEAA8);
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cgs_write_register(adev->isp.cgs_device, mmDAGB0_WRCLI9_V4_1 >> 2, 0xFE5FEAA8);
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cgs_write_register(adev->isp.cgs_device, mmDAGB0_WRCLI10_V4_1 >> 2, 0xFE5FEAA8);
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cgs_write_register(adev->isp.cgs_device, mmDAGB0_WRCLI14_V4_1 >> 2, 0xFE5FEAA8);
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cgs_write_register(adev->isp.cgs_device, mmDAGB0_WRCLI19_V4_1 >> 2, 0xFE5FEAA8);
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cgs_write_register(adev->isp.cgs_device, mmDAGB0_WRCLI20_V4_1 >> 2, 0xFE5FEAA8);
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return 0;
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failure:
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kfree(adev->isp.isp_pdata);
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kfree(adev->isp.isp_res);
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kfree(adev->isp.isp_cell);
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return r;
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}
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/**
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* isp_hw_fini - stop the hardware block
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*
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* @handle: handle for amdgpu_device pointer
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*
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*/
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static int isp_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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/* remove isp mfd device */
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mfd_remove_devices(adev->isp.parent);
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kfree(adev->isp.isp_res);
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kfree(adev->isp.isp_cell);
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kfree(adev->isp.isp_pdata);
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return 0;
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}
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static int isp_suspend(void *handle)
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{
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return 0;
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}
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static int isp_resume(void *handle)
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{
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return 0;
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}
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static int isp_load_fw_by_psp(struct amdgpu_device *adev)
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{
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const struct common_firmware_header *hdr;
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char ucode_prefix[30];
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char fw_name[40];
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int r = 0;
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/* get isp fw binary name and path */
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amdgpu_ucode_ip_version_decode(adev, ISP_HWIP, ucode_prefix,
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sizeof(ucode_prefix));
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snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
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/* read isp fw */
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r = amdgpu_ucode_request(adev, &adev->isp.fw, fw_name);
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if (r) {
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amdgpu_ucode_release(&adev->isp.fw);
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return r;
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}
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hdr = (const struct common_firmware_header *)adev->isp.fw->data;
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adev->firmware.ucode[AMDGPU_UCODE_ID_ISP].ucode_id =
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AMDGPU_UCODE_ID_ISP;
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adev->firmware.ucode[AMDGPU_UCODE_ID_ISP].fw = adev->isp.fw;
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adev->firmware.fw_size +=
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ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
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return r;
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}
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static int isp_early_init(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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ret = isp_load_fw_by_psp(adev);
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if (ret) {
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DRM_WARN("%s: isp fw load failed %d\n", __func__, ret);
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/* allow amdgpu init to proceed though isp fw load fails */
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ret = 0;
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}
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return ret;
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}
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static bool isp_is_idle(void *handle)
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{
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return true;
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}
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static int isp_wait_for_idle(void *handle)
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{
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return 0;
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}
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static int isp_soft_reset(void *handle)
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{
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return 0;
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}
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static int isp_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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return 0;
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}
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static int isp_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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return 0;
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}
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static const struct amd_ip_funcs isp_ip_funcs = {
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.name = "isp_ip",
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.early_init = isp_early_init,
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.late_init = NULL,
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.sw_init = isp_sw_init,
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.sw_fini = isp_sw_fini,
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.hw_init = isp_hw_init,
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.hw_fini = isp_hw_fini,
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.suspend = isp_suspend,
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.resume = isp_resume,
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.is_idle = isp_is_idle,
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.wait_for_idle = isp_wait_for_idle,
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.soft_reset = isp_soft_reset,
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.set_clockgating_state = isp_set_clockgating_state,
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.set_powergating_state = isp_set_powergating_state,
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};
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const struct amdgpu_ip_block_version isp_ip_block = {
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.type = AMD_IP_BLOCK_TYPE_ISP,
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.major = 4,
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.minor = 1,
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.rev = 0,
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.funcs = &isp_ip_funcs,
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};
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