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drm/amdgpu/display: buffer INTERRUPT_LOW_IRQ_CONTEXT interrupt work
amdgpu DM handles INTERRUPT_LOW_IRQ_CONTEXT interrupt(hpd, hpd_rx) by using work queue and uses single work_struct. If new interrupt is recevied before the previous handler finished, new interrupts(same type) will be discarded and driver just sends "amdgpu_dm_irq_schedule_work FAILED" message out. If some important hpd, hpd_rx related interrupts are missed by driver the hot (un)plug devices may cause system hang or instability, such as issues with system resume from S3 sleep with mst device connected. This patch dynamically allocates new amdgpu_dm_irq_handler_data for new interrupts if previous INTERRUPT_LOW_IRQ_CONTEXT interrupt work has not been handled. So the new interrupt works can be queued to the same workqueue_struct, instead of discard the new interrupts. All allocated amdgpu_dm_irq_handler_data are put into a single linked list and will be reused after. Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
a8a2e13486
commit
b6f91fc183
@@ -68,18 +68,6 @@ struct common_irq_params {
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enum dc_irq_source irq_src;
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};
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/**
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* struct irq_list_head - Linked-list for low context IRQ handlers.
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*
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* @head: The list_head within &struct handler_data
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* @work: A work_struct containing the deferred handler work
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*/
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struct irq_list_head {
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struct list_head head;
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/* In case this interrupt needs post-processing, 'work' will be queued*/
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struct work_struct work;
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};
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/**
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* struct dm_compressor_info - Buffer info used by frame buffer compression
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* @cpu_addr: MMIO cpu addr
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@@ -293,7 +281,7 @@ struct amdgpu_display_manager {
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* Note that handlers are called in the same order as they were
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* registered (FIFO).
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*/
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struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
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struct list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER];
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/**
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* @irq_handler_list_high_tab:
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