Commit baf97ce6 authored by Russell King's avatar Russell King Committed by Russell King
Browse files

[ARM] Cleanups for 4cc9bd2e 



- Document the meaning for OP_SCALAR, OP_SD and add OP_DD.
- Formatting cleanups
- Remove now redundant code for making compare instructions
  operate on scalar values.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 4cc9bd2e

arch/arm/vfp/vfp.h

+5 −1
Original line number Diff line number Diff line
@@ -357,10 +357,14 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand); 
#define VFP_EXCEPTION_ERROR	((u32)-1 & ~VFP_NAN_FLAG)



/*

 * A flag to tell vfp instruction type

 * A flag to tell vfp instruction type.

 *  OP_SCALAR - this operation always operates in scalar mode

 *  OP_SD - the instruction exceptionally writes to a single precision result.

 *  OP_DD - the instruction exceptionally writes to a double precision result.

 */

#define OP_SCALAR	(1 << 0)

#define OP_SD		(1 << 1)

#define OP_DD		(1 << 1)



struct op {

	u32 (* const fn)(int dd, int dn, int dm, u32 fpscr);

arch/arm/vfp/vfpdouble.c

+32 −41
Original line number Diff line number Diff line
@@ -668,13 +668,13 @@ static struct op fops_ext[32] = { 
	[FEXT_TO_IDX(FEXT_FCMPE)]	= { vfp_double_fcmpe,  OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FCMPZ)]	= { vfp_double_fcmpz,  OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FCMPEZ)]	= { vfp_double_fcmpez, OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FCVT)]	= {vfp_double_fcvts, (OP_SD|OP_SCALAR)},

	[FEXT_TO_IDX(FEXT_FCVT)]	= { vfp_double_fcvts,  OP_SCALAR|OP_SD },

	[FEXT_TO_IDX(FEXT_FUITO)]	= { vfp_double_fuito,  OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FSITO)]	= { vfp_double_fsito,  OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FTOUI)]	= {vfp_double_ftoui, (OP_SD|OP_SCALAR)},

	[FEXT_TO_IDX(FEXT_FTOUIZ)]	= {vfp_double_ftouiz, (OP_SD|OP_SCALAR)},

	[FEXT_TO_IDX(FEXT_FTOSI)]	= {vfp_double_ftosi, (OP_SD|OP_SCALAR)},

	[FEXT_TO_IDX(FEXT_FTOSIZ)]	= {vfp_double_ftosiz, (OP_SD|OP_SCALAR)},

	[FEXT_TO_IDX(FEXT_FTOUI)]	= { vfp_double_ftoui,  OP_SCALAR|OP_SD },

	[FEXT_TO_IDX(FEXT_FTOUIZ)]	= { vfp_double_ftouiz, OP_SCALAR|OP_SD },

	[FEXT_TO_IDX(FEXT_FTOSI)]	= { vfp_double_ftosi,  OP_SCALAR|OP_SD },

	[FEXT_TO_IDX(FEXT_FTOSIZ)]	= { vfp_double_ftosiz, OP_SCALAR|OP_SD },

};
@@ -1136,6 +1136,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) 
	vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;



	fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];



	/*

	 * fcvtds takes an sN register number as destination, not dN.

	 * It also always operates on scalars.
@@ -1162,19 +1163,17 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) 


	for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {

		u32 except;

		char type;



		if (op == FOP_EXT && (fop->flags & OP_SD))

			pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n",

				 vecitr >> FPSCR_LENGTH_BIT,

				 dest, dn, dm);

		else if (op == FOP_EXT)

			pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n",

		type = fop->flags & OP_SD ? 's' : 'd';

		if (op == FOP_EXT)

			pr_debug("VFP: itr%d (%c%u) = op[%u] (d%u)\n",

				 vecitr >> FPSCR_LENGTH_BIT,

				 dest, dn, dm);

				 type, dest, dn, dm);

		else

			pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n",

			pr_debug("VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",

				 vecitr >> FPSCR_LENGTH_BIT,

				 dest, dn, FOP_TO_IDX(op), dm);

				 type, dest, dn, FOP_TO_IDX(op), dm);



		except = fop->fn(dest, dn, dm, fpscr);

		pr_debug("VFP: itr%d: exceptions=%08x\n",
@@ -1182,18 +1181,10 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) 


		exceptions |= except;



		/*

		 * This ensures that comparisons only operate on scalars;

		 * comparisons always return with one FPSCR status bit set.

		 */

		if (except & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))

			break;



		/*

		 * CHECK: It appears to be undefined whether we stop when

		 * we encounter an exception.  We continue.

		 */



		dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6);

		dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6);

		if (FREG_BANK(dm) != 0)

arch/arm/vfp/vfpsingle.c

+36 −43
Original line number Diff line number Diff line
@@ -711,7 +711,7 @@ static struct op fops_ext[32] = { 
	[FEXT_TO_IDX(FEXT_FCMPE)]	= { vfp_single_fcmpe,  OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FCMPZ)]	= { vfp_single_fcmpz,  OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FCMPEZ)]	= { vfp_single_fcmpez, OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FCVT)]	= {vfp_single_fcvtd, (OP_SD|OP_SCALAR)},

	[FEXT_TO_IDX(FEXT_FCVT)]	= { vfp_single_fcvtd,  OP_SCALAR|OP_DD },

	[FEXT_TO_IDX(FEXT_FUITO)]	= { vfp_single_fuito,  OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FSITO)]	= { vfp_single_fsito,  OP_SCALAR },

	[FEXT_TO_IDX(FEXT_FTOUI)]	= { vfp_single_ftoui,  OP_SCALAR },
@@ -1179,22 +1179,23 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) 
	vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK);



	fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];



	/*

	 * fcvtsd takes a dN register number as destination, not sN.

	 * Technically, if bit 0 of dd is set, this is an invalid

	 * instruction.  However, we ignore this for efficiency.

	 * It also only operates on scalars.

	 */

	if (fop->flags & OP_SD) {

	if (fop->flags & OP_DD)

		dest = vfp_get_dd(inst);

	} else

	else

		dest = vfp_get_sd(inst);



	/*

	 * If destination bank is zero, vector length is always '1'.

	 * ARM DDI0100F C5.1.3, C5.3.2.

	 */

	if ((fop->flags & OP_SCALAR) || (FREG_BANK(dest) == 0))

	if ((fop->flags & OP_SCALAR) || FREG_BANK(dest) == 0)

		veclen = 0;

	else

		veclen = fpscr & FPSCR_LENGTH_MASK;
@@ -1208,16 +1209,16 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) 
	for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {

		s32 m = vfp_get_float(sm);

		u32 except;

		char type;



		if (op == FOP_EXT && (fop->flags & OP_SD))

			pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n",

				 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);

		else if (op == FOP_EXT)

			pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n",

				 vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);

		type = fop->flags & OP_DD ? 'd' : 's';

		if (op == FOP_EXT)

			pr_debug("VFP: itr%d (%c%u) = op[%u] (s%u=%08x)\n",

				 vecitr >> FPSCR_LENGTH_BIT, type, dest, sn,

				 sm, m);

		else

			pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n",

				 vecitr >> FPSCR_LENGTH_BIT, dest, sn,

			pr_debug("VFP: itr%d (%c%u) = (s%u) op[%u] (s%u=%08x)\n",

				 vecitr >> FPSCR_LENGTH_BIT, type, dest, sn,

				 FOP_TO_IDX(op), sm, m);



		except = fop->fn(dest, sn, m, fpscr);
@@ -1226,18 +1227,10 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) 


		exceptions |= except;



		/*

		 * This ensures that comparisons only operate on scalars;

		 * comparisons always return with one FPSCR status bit set.

		 */

		if (except & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))

			break;



		/*

		 * CHECK: It appears to be undefined whether we stop when

		 * we encounter an exception.  We continue.

		 */



		dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7);

		sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7);

		if (FREG_BANK(sm) != 0)