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drm/amdgpu: add core driver (v4)
This adds the non-asic specific core driver code. v2: remove extra kconfig option v3: implement minor fixes from Fengguang Wu v4: fix cast in amdgpu_ucode.c Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
832
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
Normal file
832
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
Normal file
@@ -0,0 +1,832 @@
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/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "amdgpu_i2c.h"
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#include "atom.h"
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#include "amdgpu_connectors.h"
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#include <asm/div64.h>
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#include <linux/pm_runtime.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_edid.h>
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static void amdgpu_flip_work_func(struct work_struct *__work)
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{
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struct amdgpu_flip_work *work =
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container_of(__work, struct amdgpu_flip_work, flip_work);
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struct amdgpu_device *adev = work->adev;
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struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id];
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struct drm_crtc *crtc = &amdgpuCrtc->base;
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struct amdgpu_fence *fence;
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unsigned long flags;
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int r;
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down_read(&adev->exclusive_lock);
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if (work->fence) {
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fence = to_amdgpu_fence(work->fence);
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if (fence) {
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r = amdgpu_fence_wait(fence, false);
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if (r == -EDEADLK) {
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up_read(&adev->exclusive_lock);
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r = amdgpu_gpu_reset(adev);
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down_read(&adev->exclusive_lock);
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}
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} else
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r = fence_wait(work->fence, false);
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if (r)
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DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
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/* We continue with the page flip even if we failed to wait on
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* the fence, otherwise the DRM core and userspace will be
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* confused about which BO the CRTC is scanning out
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*/
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fence_put(work->fence);
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work->fence = NULL;
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}
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/* We borrow the event spin lock for protecting flip_status */
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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/* set the proper interrupt */
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amdgpu_irq_get(adev, &adev->pageflip_irq, work->crtc_id);
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/* do the flip (mmio) */
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adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
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/* set the flip status */
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amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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up_read(&adev->exclusive_lock);
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}
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/*
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* Handle unpin events outside the interrupt handler proper.
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*/
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static void amdgpu_unpin_work_func(struct work_struct *__work)
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{
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struct amdgpu_flip_work *work =
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container_of(__work, struct amdgpu_flip_work, unpin_work);
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int r;
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/* unpin of the old buffer */
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r = amdgpu_bo_reserve(work->old_rbo, false);
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if (likely(r == 0)) {
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r = amdgpu_bo_unpin(work->old_rbo);
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if (unlikely(r != 0)) {
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DRM_ERROR("failed to unpin buffer after flip\n");
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}
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amdgpu_bo_unreserve(work->old_rbo);
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} else
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DRM_ERROR("failed to reserve buffer after flip\n");
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drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
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kfree(work);
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}
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int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event,
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uint32_t page_flip_flags)
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{
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struct drm_device *dev = crtc->dev;
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struct amdgpu_device *adev = dev->dev_private;
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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struct amdgpu_framebuffer *old_amdgpu_fb;
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struct amdgpu_framebuffer *new_amdgpu_fb;
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struct drm_gem_object *obj;
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struct amdgpu_flip_work *work;
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struct amdgpu_bo *new_rbo;
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unsigned long flags;
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u64 tiling_flags;
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u64 base;
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int r;
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work = kzalloc(sizeof *work, GFP_KERNEL);
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if (work == NULL)
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return -ENOMEM;
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INIT_WORK(&work->flip_work, amdgpu_flip_work_func);
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INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
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work->event = event;
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work->adev = adev;
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work->crtc_id = amdgpu_crtc->crtc_id;
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/* schedule unpin of the old buffer */
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old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
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obj = old_amdgpu_fb->obj;
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/* take a reference to the old object */
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drm_gem_object_reference(obj);
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work->old_rbo = gem_to_amdgpu_bo(obj);
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new_amdgpu_fb = to_amdgpu_framebuffer(fb);
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obj = new_amdgpu_fb->obj;
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new_rbo = gem_to_amdgpu_bo(obj);
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/* pin the new buffer */
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r = amdgpu_bo_reserve(new_rbo, false);
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if (unlikely(r != 0)) {
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DRM_ERROR("failed to reserve new rbo buffer before flip\n");
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goto cleanup;
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}
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r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, &base);
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if (unlikely(r != 0)) {
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amdgpu_bo_unreserve(new_rbo);
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r = -EINVAL;
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DRM_ERROR("failed to pin new rbo buffer before flip\n");
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goto cleanup;
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}
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work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
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amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags);
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amdgpu_bo_unreserve(new_rbo);
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work->base = base;
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r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
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if (r) {
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DRM_ERROR("failed to get vblank before flip\n");
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goto pflip_cleanup;
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}
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/* we borrow the event spin lock for protecting flip_wrok */
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
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DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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r = -EBUSY;
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goto vblank_cleanup;
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}
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amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
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amdgpu_crtc->pflip_works = work;
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/* update crtc fb */
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crtc->primary->fb = fb;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
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return 0;
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vblank_cleanup:
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drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
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pflip_cleanup:
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if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
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DRM_ERROR("failed to reserve new rbo in error path\n");
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goto cleanup;
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}
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if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) {
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DRM_ERROR("failed to unpin new rbo in error path\n");
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}
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amdgpu_bo_unreserve(new_rbo);
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cleanup:
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drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
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fence_put(work->fence);
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kfree(work);
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return r;
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}
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int amdgpu_crtc_set_config(struct drm_mode_set *set)
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{
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struct drm_device *dev;
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struct amdgpu_device *adev;
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struct drm_crtc *crtc;
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bool active = false;
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int ret;
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if (!set || !set->crtc)
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return -EINVAL;
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dev = set->crtc->dev;
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ret = pm_runtime_get_sync(dev->dev);
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if (ret < 0)
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return ret;
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ret = drm_crtc_helper_set_config(set);
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
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if (crtc->enabled)
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active = true;
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pm_runtime_mark_last_busy(dev->dev);
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adev = dev->dev_private;
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/* if we have active crtcs and we don't have a power ref,
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take the current one */
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if (active && !adev->have_disp_power_ref) {
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adev->have_disp_power_ref = true;
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return ret;
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}
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/* if we have no active crtcs, then drop the power ref
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we got before */
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if (!active && adev->have_disp_power_ref) {
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pm_runtime_put_autosuspend(dev->dev);
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adev->have_disp_power_ref = false;
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}
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/* drop the power reference we got coming in here */
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pm_runtime_put_autosuspend(dev->dev);
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return ret;
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}
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static const char *encoder_names[38] = {
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"NONE",
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"INTERNAL_LVDS",
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"INTERNAL_TMDS1",
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"INTERNAL_TMDS2",
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"INTERNAL_DAC1",
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"INTERNAL_DAC2",
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"INTERNAL_SDVOA",
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"INTERNAL_SDVOB",
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"SI170B",
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"CH7303",
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"CH7301",
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"INTERNAL_DVO1",
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"EXTERNAL_SDVOA",
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"EXTERNAL_SDVOB",
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"TITFP513",
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"INTERNAL_LVTM1",
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"VT1623",
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"HDMI_SI1930",
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"HDMI_INTERNAL",
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"INTERNAL_KLDSCP_TMDS1",
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"INTERNAL_KLDSCP_DVO1",
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"INTERNAL_KLDSCP_DAC1",
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"INTERNAL_KLDSCP_DAC2",
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"SI178",
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"MVPU_FPGA",
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"INTERNAL_DDI",
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"VT1625",
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"HDMI_SI1932",
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"DP_AN9801",
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"DP_DP501",
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"INTERNAL_UNIPHY",
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"INTERNAL_KLDSCP_LVTMA",
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"INTERNAL_UNIPHY1",
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"INTERNAL_UNIPHY2",
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"NUTMEG",
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"TRAVIS",
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"INTERNAL_VCE",
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"INTERNAL_UNIPHY3",
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};
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static const char *hpd_names[6] = {
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"HPD1",
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"HPD2",
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"HPD3",
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"HPD4",
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"HPD5",
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"HPD6",
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};
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void amdgpu_print_display_setup(struct drm_device *dev)
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{
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struct drm_connector *connector;
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struct amdgpu_connector *amdgpu_connector;
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struct drm_encoder *encoder;
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struct amdgpu_encoder *amdgpu_encoder;
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uint32_t devices;
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int i = 0;
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DRM_INFO("AMDGPU Display Connectors\n");
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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amdgpu_connector = to_amdgpu_connector(connector);
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DRM_INFO("Connector %d:\n", i);
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DRM_INFO(" %s\n", connector->name);
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if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
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DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
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if (amdgpu_connector->ddc_bus) {
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DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
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amdgpu_connector->ddc_bus->rec.mask_clk_reg,
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amdgpu_connector->ddc_bus->rec.mask_data_reg,
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amdgpu_connector->ddc_bus->rec.a_clk_reg,
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amdgpu_connector->ddc_bus->rec.a_data_reg,
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amdgpu_connector->ddc_bus->rec.en_clk_reg,
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amdgpu_connector->ddc_bus->rec.en_data_reg,
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amdgpu_connector->ddc_bus->rec.y_clk_reg,
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amdgpu_connector->ddc_bus->rec.y_data_reg);
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if (amdgpu_connector->router.ddc_valid)
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DRM_INFO(" DDC Router 0x%x/0x%x\n",
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amdgpu_connector->router.ddc_mux_control_pin,
|
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amdgpu_connector->router.ddc_mux_state);
|
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if (amdgpu_connector->router.cd_valid)
|
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DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
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amdgpu_connector->router.cd_mux_control_pin,
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amdgpu_connector->router.cd_mux_state);
|
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} else {
|
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if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
|
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connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
|
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connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
|
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connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
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connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
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||||
connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
|
||||
DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
|
||||
}
|
||||
DRM_INFO(" Encoders:\n");
|
||||
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
||||
amdgpu_encoder = to_amdgpu_encoder(encoder);
|
||||
devices = amdgpu_encoder->devices & amdgpu_connector->devices;
|
||||
if (devices) {
|
||||
if (devices & ATOM_DEVICE_CRT1_SUPPORT)
|
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DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_CRT2_SUPPORT)
|
||||
DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_LCD1_SUPPORT)
|
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DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_DFP1_SUPPORT)
|
||||
DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_DFP2_SUPPORT)
|
||||
DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_DFP3_SUPPORT)
|
||||
DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_DFP4_SUPPORT)
|
||||
DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_DFP5_SUPPORT)
|
||||
DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_DFP6_SUPPORT)
|
||||
DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_TV1_SUPPORT)
|
||||
DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
if (devices & ATOM_DEVICE_CV_SUPPORT)
|
||||
DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
|
||||
}
|
||||
}
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_ddc_probe
|
||||
*
|
||||
*/
|
||||
bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
|
||||
bool use_aux)
|
||||
{
|
||||
u8 out = 0x0;
|
||||
u8 buf[8];
|
||||
int ret;
|
||||
struct i2c_msg msgs[] = {
|
||||
{
|
||||
.addr = DDC_ADDR,
|
||||
.flags = 0,
|
||||
.len = 1,
|
||||
.buf = &out,
|
||||
},
|
||||
{
|
||||
.addr = DDC_ADDR,
|
||||
.flags = I2C_M_RD,
|
||||
.len = 8,
|
||||
.buf = buf,
|
||||
}
|
||||
};
|
||||
|
||||
/* on hw with routers, select right port */
|
||||
if (amdgpu_connector->router.ddc_valid)
|
||||
amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
|
||||
|
||||
if (use_aux) {
|
||||
ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
|
||||
} else {
|
||||
ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
|
||||
}
|
||||
|
||||
if (ret != 2)
|
||||
/* Couldn't find an accessible DDC on this connector */
|
||||
return false;
|
||||
/* Probe also for valid EDID header
|
||||
* EDID header starts with:
|
||||
* 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
|
||||
* Only the first 6 bytes must be valid as
|
||||
* drm_edid_block_valid() can fix the last 2 bytes */
|
||||
if (drm_edid_header_is_valid(buf) < 6) {
|
||||
/* Couldn't find an accessible EDID on this
|
||||
* connector */
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
|
||||
{
|
||||
struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
|
||||
|
||||
if (amdgpu_fb->obj) {
|
||||
drm_gem_object_unreference_unlocked(amdgpu_fb->obj);
|
||||
}
|
||||
drm_framebuffer_cleanup(fb);
|
||||
kfree(amdgpu_fb);
|
||||
}
|
||||
|
||||
static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
|
||||
struct drm_file *file_priv,
|
||||
unsigned int *handle)
|
||||
{
|
||||
struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
|
||||
|
||||
return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
|
||||
}
|
||||
|
||||
static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
|
||||
.destroy = amdgpu_user_framebuffer_destroy,
|
||||
.create_handle = amdgpu_user_framebuffer_create_handle,
|
||||
};
|
||||
|
||||
int
|
||||
amdgpu_framebuffer_init(struct drm_device *dev,
|
||||
struct amdgpu_framebuffer *rfb,
|
||||
struct drm_mode_fb_cmd2 *mode_cmd,
|
||||
struct drm_gem_object *obj)
|
||||
{
|
||||
int ret;
|
||||
rfb->obj = obj;
|
||||
drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
|
||||
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
|
||||
if (ret) {
|
||||
rfb->obj = NULL;
|
||||
return ret;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct drm_framebuffer *
|
||||
amdgpu_user_framebuffer_create(struct drm_device *dev,
|
||||
struct drm_file *file_priv,
|
||||
struct drm_mode_fb_cmd2 *mode_cmd)
|
||||
{
|
||||
struct drm_gem_object *obj;
|
||||
struct amdgpu_framebuffer *amdgpu_fb;
|
||||
int ret;
|
||||
|
||||
obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
|
||||
if (obj == NULL) {
|
||||
dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
|
||||
"can't create framebuffer\n", mode_cmd->handles[0]);
|
||||
return ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
|
||||
if (amdgpu_fb == NULL) {
|
||||
drm_gem_object_unreference_unlocked(obj);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
|
||||
if (ret) {
|
||||
kfree(amdgpu_fb);
|
||||
drm_gem_object_unreference_unlocked(obj);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return &amdgpu_fb->base;
|
||||
}
|
||||
|
||||
static void amdgpu_output_poll_changed(struct drm_device *dev)
|
||||
{
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
amdgpu_fb_output_poll_changed(adev);
|
||||
}
|
||||
|
||||
const struct drm_mode_config_funcs amdgpu_mode_funcs = {
|
||||
.fb_create = amdgpu_user_framebuffer_create,
|
||||
.output_poll_changed = amdgpu_output_poll_changed
|
||||
};
|
||||
|
||||
static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
|
||||
{ { UNDERSCAN_OFF, "off" },
|
||||
{ UNDERSCAN_ON, "on" },
|
||||
{ UNDERSCAN_AUTO, "auto" },
|
||||
};
|
||||
|
||||
static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
|
||||
{ { AMDGPU_AUDIO_DISABLE, "off" },
|
||||
{ AMDGPU_AUDIO_ENABLE, "on" },
|
||||
{ AMDGPU_AUDIO_AUTO, "auto" },
|
||||
};
|
||||
|
||||
/* XXX support different dither options? spatial, temporal, both, etc. */
|
||||
static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
|
||||
{ { AMDGPU_FMT_DITHER_DISABLE, "off" },
|
||||
{ AMDGPU_FMT_DITHER_ENABLE, "on" },
|
||||
};
|
||||
|
||||
int amdgpu_modeset_create_props(struct amdgpu_device *adev)
|
||||
{
|
||||
int sz;
|
||||
|
||||
if (adev->is_atom_bios) {
|
||||
adev->mode_info.coherent_mode_property =
|
||||
drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
|
||||
if (!adev->mode_info.coherent_mode_property)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
adev->mode_info.load_detect_property =
|
||||
drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
|
||||
if (!adev->mode_info.load_detect_property)
|
||||
return -ENOMEM;
|
||||
|
||||
drm_mode_create_scaling_mode_property(adev->ddev);
|
||||
|
||||
sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
|
||||
adev->mode_info.underscan_property =
|
||||
drm_property_create_enum(adev->ddev, 0,
|
||||
"underscan",
|
||||
amdgpu_underscan_enum_list, sz);
|
||||
|
||||
adev->mode_info.underscan_hborder_property =
|
||||
drm_property_create_range(adev->ddev, 0,
|
||||
"underscan hborder", 0, 128);
|
||||
if (!adev->mode_info.underscan_hborder_property)
|
||||
return -ENOMEM;
|
||||
|
||||
adev->mode_info.underscan_vborder_property =
|
||||
drm_property_create_range(adev->ddev, 0,
|
||||
"underscan vborder", 0, 128);
|
||||
if (!adev->mode_info.underscan_vborder_property)
|
||||
return -ENOMEM;
|
||||
|
||||
sz = ARRAY_SIZE(amdgpu_audio_enum_list);
|
||||
adev->mode_info.audio_property =
|
||||
drm_property_create_enum(adev->ddev, 0,
|
||||
"audio",
|
||||
amdgpu_audio_enum_list, sz);
|
||||
|
||||
sz = ARRAY_SIZE(amdgpu_dither_enum_list);
|
||||
adev->mode_info.dither_property =
|
||||
drm_property_create_enum(adev->ddev, 0,
|
||||
"dither",
|
||||
amdgpu_dither_enum_list, sz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void amdgpu_update_display_priority(struct amdgpu_device *adev)
|
||||
{
|
||||
/* adjustment options for the display watermarks */
|
||||
if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
|
||||
adev->mode_info.disp_priority = 0;
|
||||
else
|
||||
adev->mode_info.disp_priority = amdgpu_disp_priority;
|
||||
|
||||
}
|
||||
|
||||
static bool is_hdtv_mode(const struct drm_display_mode *mode)
|
||||
{
|
||||
/* try and guess if this is a tv or a monitor */
|
||||
if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
|
||||
(mode->vdisplay == 576) || /* 576p */
|
||||
(mode->vdisplay == 720) || /* 720p */
|
||||
(mode->vdisplay == 1080)) /* 1080p */
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
|
||||
const struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_encoder *encoder;
|
||||
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
|
||||
struct amdgpu_encoder *amdgpu_encoder;
|
||||
struct drm_connector *connector;
|
||||
struct amdgpu_connector *amdgpu_connector;
|
||||
u32 src_v = 1, dst_v = 1;
|
||||
u32 src_h = 1, dst_h = 1;
|
||||
|
||||
amdgpu_crtc->h_border = 0;
|
||||
amdgpu_crtc->v_border = 0;
|
||||
|
||||
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
||||
if (encoder->crtc != crtc)
|
||||
continue;
|
||||
amdgpu_encoder = to_amdgpu_encoder(encoder);
|
||||
connector = amdgpu_get_connector_for_encoder(encoder);
|
||||
amdgpu_connector = to_amdgpu_connector(connector);
|
||||
|
||||
/* set scaling */
|
||||
if (amdgpu_encoder->rmx_type == RMX_OFF)
|
||||
amdgpu_crtc->rmx_type = RMX_OFF;
|
||||
else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
|
||||
mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
|
||||
amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
|
||||
else
|
||||
amdgpu_crtc->rmx_type = RMX_OFF;
|
||||
/* copy native mode */
|
||||
memcpy(&amdgpu_crtc->native_mode,
|
||||
&amdgpu_encoder->native_mode,
|
||||
sizeof(struct drm_display_mode));
|
||||
src_v = crtc->mode.vdisplay;
|
||||
dst_v = amdgpu_crtc->native_mode.vdisplay;
|
||||
src_h = crtc->mode.hdisplay;
|
||||
dst_h = amdgpu_crtc->native_mode.hdisplay;
|
||||
|
||||
/* fix up for overscan on hdmi */
|
||||
if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
|
||||
((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
|
||||
((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
|
||||
drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
|
||||
is_hdtv_mode(mode)))) {
|
||||
if (amdgpu_encoder->underscan_hborder != 0)
|
||||
amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
|
||||
else
|
||||
amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
|
||||
if (amdgpu_encoder->underscan_vborder != 0)
|
||||
amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
|
||||
else
|
||||
amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
|
||||
amdgpu_crtc->rmx_type = RMX_FULL;
|
||||
src_v = crtc->mode.vdisplay;
|
||||
dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
|
||||
src_h = crtc->mode.hdisplay;
|
||||
dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
|
||||
}
|
||||
}
|
||||
if (amdgpu_crtc->rmx_type != RMX_OFF) {
|
||||
fixed20_12 a, b;
|
||||
a.full = dfixed_const(src_v);
|
||||
b.full = dfixed_const(dst_v);
|
||||
amdgpu_crtc->vsc.full = dfixed_div(a, b);
|
||||
a.full = dfixed_const(src_h);
|
||||
b.full = dfixed_const(dst_h);
|
||||
amdgpu_crtc->hsc.full = dfixed_div(a, b);
|
||||
} else {
|
||||
amdgpu_crtc->vsc.full = dfixed_const(1);
|
||||
amdgpu_crtc->hsc.full = dfixed_const(1);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Retrieve current video scanout position of crtc on a given gpu, and
|
||||
* an optional accurate timestamp of when query happened.
|
||||
*
|
||||
* \param dev Device to query.
|
||||
* \param crtc Crtc to query.
|
||||
* \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
|
||||
* \param *vpos Location where vertical scanout position should be stored.
|
||||
* \param *hpos Location where horizontal scanout position should go.
|
||||
* \param *stime Target location for timestamp taken immediately before
|
||||
* scanout position query. Can be NULL to skip timestamp.
|
||||
* \param *etime Target location for timestamp taken immediately after
|
||||
* scanout position query. Can be NULL to skip timestamp.
|
||||
*
|
||||
* Returns vpos as a positive number while in active scanout area.
|
||||
* Returns vpos as a negative number inside vblank, counting the number
|
||||
* of scanlines to go until end of vblank, e.g., -1 means "one scanline
|
||||
* until start of active scanout / end of vblank."
|
||||
*
|
||||
* \return Flags, or'ed together as follows:
|
||||
*
|
||||
* DRM_SCANOUTPOS_VALID = Query successful.
|
||||
* DRM_SCANOUTPOS_INVBL = Inside vblank.
|
||||
* DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
|
||||
* this flag means that returned position may be offset by a constant but
|
||||
* unknown small number of scanlines wrt. real scanout position.
|
||||
*
|
||||
*/
|
||||
int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
|
||||
int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
|
||||
{
|
||||
u32 vbl = 0, position = 0;
|
||||
int vbl_start, vbl_end, vtotal, ret = 0;
|
||||
bool in_vbl = true;
|
||||
|
||||
struct amdgpu_device *adev = dev->dev_private;
|
||||
|
||||
/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
|
||||
|
||||
/* Get optional system timestamp before query. */
|
||||
if (stime)
|
||||
*stime = ktime_get();
|
||||
|
||||
if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0)
|
||||
ret |= DRM_SCANOUTPOS_VALID;
|
||||
|
||||
/* Get optional system timestamp after query. */
|
||||
if (etime)
|
||||
*etime = ktime_get();
|
||||
|
||||
/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
|
||||
|
||||
/* Decode into vertical and horizontal scanout position. */
|
||||
*vpos = position & 0x1fff;
|
||||
*hpos = (position >> 16) & 0x1fff;
|
||||
|
||||
/* Valid vblank area boundaries from gpu retrieved? */
|
||||
if (vbl > 0) {
|
||||
/* Yes: Decode. */
|
||||
ret |= DRM_SCANOUTPOS_ACCURATE;
|
||||
vbl_start = vbl & 0x1fff;
|
||||
vbl_end = (vbl >> 16) & 0x1fff;
|
||||
}
|
||||
else {
|
||||
/* No: Fake something reasonable which gives at least ok results. */
|
||||
vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
|
||||
vbl_end = 0;
|
||||
}
|
||||
|
||||
/* Test scanout position against vblank region. */
|
||||
if ((*vpos < vbl_start) && (*vpos >= vbl_end))
|
||||
in_vbl = false;
|
||||
|
||||
/* Check if inside vblank area and apply corrective offsets:
|
||||
* vpos will then be >=0 in video scanout area, but negative
|
||||
* within vblank area, counting down the number of lines until
|
||||
* start of scanout.
|
||||
*/
|
||||
|
||||
/* Inside "upper part" of vblank area? Apply corrective offset if so: */
|
||||
if (in_vbl && (*vpos >= vbl_start)) {
|
||||
vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
|
||||
*vpos = *vpos - vtotal;
|
||||
}
|
||||
|
||||
/* Correct for shifted end of vbl at vbl_end. */
|
||||
*vpos = *vpos - vbl_end;
|
||||
|
||||
/* In vblank? */
|
||||
if (in_vbl)
|
||||
ret |= DRM_SCANOUTPOS_IN_VBLANK;
|
||||
|
||||
/* Is vpos outside nominal vblank area, but less than
|
||||
* 1/100 of a frame height away from start of vblank?
|
||||
* If so, assume this isn't a massively delayed vblank
|
||||
* interrupt, but a vblank interrupt that fired a few
|
||||
* microseconds before true start of vblank. Compensate
|
||||
* by adding a full frame duration to the final timestamp.
|
||||
* Happens, e.g., on ATI R500, R600.
|
||||
*
|
||||
* We only do this if DRM_CALLED_FROM_VBLIRQ.
|
||||
*/
|
||||
if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
|
||||
vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
|
||||
vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
|
||||
|
||||
if (vbl_start - *vpos < vtotal / 100) {
|
||||
*vpos -= vtotal;
|
||||
|
||||
/* Signal this correction as "applied". */
|
||||
ret |= 0x8;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
|
||||
{
|
||||
if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
|
||||
return AMDGPU_CRTC_IRQ_NONE;
|
||||
|
||||
switch (crtc) {
|
||||
case 0:
|
||||
return AMDGPU_CRTC_IRQ_VBLANK1;
|
||||
case 1:
|
||||
return AMDGPU_CRTC_IRQ_VBLANK2;
|
||||
case 2:
|
||||
return AMDGPU_CRTC_IRQ_VBLANK3;
|
||||
case 3:
|
||||
return AMDGPU_CRTC_IRQ_VBLANK4;
|
||||
case 4:
|
||||
return AMDGPU_CRTC_IRQ_VBLANK5;
|
||||
case 5:
|
||||
return AMDGPU_CRTC_IRQ_VBLANK6;
|
||||
default:
|
||||
return AMDGPU_CRTC_IRQ_NONE;
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user