Loading arch/mips/kernel/proc.c +1 −1 Original line number Diff line number Diff line Loading @@ -107,7 +107,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", cpu_has_fpu ? " FPU V%d.%d" : ""); cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ? cpu_data[n].cputype : CPU_UNKNOWN], (version >> 4) & 0x0f, version & 0x0f, Loading arch/mips/kernel/process.c +1 −1 Original line number Diff line number Diff line Loading @@ -115,7 +115,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) status |= KU_USER; regs->cp0_status = status; clear_used_math(); lose_fpu(); clear_fpu_owner(); if (cpu_has_dsp) __init_dsp(); regs->cp0_epc = pc; Loading arch/mips/kernel/ptrace.c +10 −8 Original line number Diff line number Diff line Loading @@ -106,6 +106,7 @@ int ptrace_setregs (struct task_struct *child, __s64 __user *data) int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) { int i; unsigned int tmp; if (!access_ok(VERIFY_WRITE, data, 33 * 8)) return -EIO; Loading @@ -121,10 +122,10 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) __put_user (child->thread.fpu.fcr31, data + 64); preempt_disable(); if (cpu_has_fpu) { unsigned int flags, tmp; unsigned int flags; preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); Loading @@ -138,11 +139,11 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); write_c0_status(flags); } preempt_enable(); __put_user (tmp, data + 65); } else { __put_user ((__u32) 0, data + 65); tmp = 0; } preempt_enable(); __put_user (tmp, data + 65); return 0; } Loading Loading @@ -245,16 +246,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) unsigned int mtflags; #endif /* CONFIG_MIPS_MT_SMTC */ if (!cpu_has_fpu) preempt_disable(); if (!cpu_has_fpu) { preempt_enable(); break; } #ifdef CONFIG_MIPS_MT_SMTC /* Read-modify-write of Status must be atomic */ local_irq_save(irqflags); mtflags = dmt(); #endif /* CONFIG_MIPS_MT_SMTC */ preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); Loading arch/mips/kernel/ptrace32.c +2 −1 Original line number Diff line number Diff line Loading @@ -175,7 +175,9 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) unsigned int mtflags; #endif /* CONFIG_MIPS_MT_SMTC */ preempt_disable(); if (!cpu_has_fpu) { preempt_enable(); tmp = 0; break; } Loading @@ -186,7 +188,6 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) mtflags = dmt(); #endif /* CONFIG_MIPS_MT_SMTC */ preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); Loading arch/mips/kernel/traps.c +9 −7 Original line number Diff line number Diff line Loading @@ -66,7 +66,7 @@ extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx); struct mips_fpu_struct *ctx, int has_fpu); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); Loading Loading @@ -641,7 +641,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) preempt_enable(); /* Run the emulator */ sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu); sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); preempt_disable(); Loading Loading @@ -791,11 +791,13 @@ asmlinkage void do_cpu(struct pt_regs *regs) set_used_math(); } if (cpu_has_fpu) { preempt_enable(); if (!cpu_has_fpu) { int sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu); } else { int sig; preempt_enable(); sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0); if (sig) force_sig(sig, current); #ifdef CONFIG_MIPS_MT_FPAFF Loading Loading
arch/mips/kernel/proc.c +1 −1 Original line number Diff line number Diff line Loading @@ -107,7 +107,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "processor\t\t: %ld\n", n); sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", cpu_has_fpu ? " FPU V%d.%d" : ""); cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ? cpu_data[n].cputype : CPU_UNKNOWN], (version >> 4) & 0x0f, version & 0x0f, Loading
arch/mips/kernel/process.c +1 −1 Original line number Diff line number Diff line Loading @@ -115,7 +115,7 @@ void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp) status |= KU_USER; regs->cp0_status = status; clear_used_math(); lose_fpu(); clear_fpu_owner(); if (cpu_has_dsp) __init_dsp(); regs->cp0_epc = pc; Loading
arch/mips/kernel/ptrace.c +10 −8 Original line number Diff line number Diff line Loading @@ -106,6 +106,7 @@ int ptrace_setregs (struct task_struct *child, __s64 __user *data) int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) { int i; unsigned int tmp; if (!access_ok(VERIFY_WRITE, data, 33 * 8)) return -EIO; Loading @@ -121,10 +122,10 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) __put_user (child->thread.fpu.fcr31, data + 64); preempt_disable(); if (cpu_has_fpu) { unsigned int flags, tmp; unsigned int flags; preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); Loading @@ -138,11 +139,11 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); write_c0_status(flags); } preempt_enable(); __put_user (tmp, data + 65); } else { __put_user ((__u32) 0, data + 65); tmp = 0; } preempt_enable(); __put_user (tmp, data + 65); return 0; } Loading Loading @@ -245,16 +246,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) unsigned int mtflags; #endif /* CONFIG_MIPS_MT_SMTC */ if (!cpu_has_fpu) preempt_disable(); if (!cpu_has_fpu) { preempt_enable(); break; } #ifdef CONFIG_MIPS_MT_SMTC /* Read-modify-write of Status must be atomic */ local_irq_save(irqflags); mtflags = dmt(); #endif /* CONFIG_MIPS_MT_SMTC */ preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); Loading
arch/mips/kernel/ptrace32.c +2 −1 Original line number Diff line number Diff line Loading @@ -175,7 +175,9 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) unsigned int mtflags; #endif /* CONFIG_MIPS_MT_SMTC */ preempt_disable(); if (!cpu_has_fpu) { preempt_enable(); tmp = 0; break; } Loading @@ -186,7 +188,6 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data) mtflags = dmt(); #endif /* CONFIG_MIPS_MT_SMTC */ preempt_disable(); if (cpu_has_mipsmt) { unsigned int vpflags = dvpe(); flags = read_c0_status(); Loading
arch/mips/kernel/traps.c +9 −7 Original line number Diff line number Diff line Loading @@ -66,7 +66,7 @@ extern asmlinkage void handle_mcheck(void); extern asmlinkage void handle_reserved(void); extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx); struct mips_fpu_struct *ctx, int has_fpu); void (*board_be_init)(void); int (*board_be_handler)(struct pt_regs *regs, int is_fixup); Loading Loading @@ -641,7 +641,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) preempt_enable(); /* Run the emulator */ sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu); sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1); preempt_disable(); Loading Loading @@ -791,11 +791,13 @@ asmlinkage void do_cpu(struct pt_regs *regs) set_used_math(); } if (cpu_has_fpu) { preempt_enable(); if (!cpu_has_fpu) { int sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu); } else { int sig; preempt_enable(); sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0); if (sig) force_sig(sig, current); #ifdef CONFIG_MIPS_MT_FPAFF Loading