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drm/amd/display: Clean up for DCN1 clock debug logging

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[Why]
To prepare for clock debug logging. With the exception of removing
max_supported_dppclk_khz from logs, there are no functional changes.

[How]
Add clk_bypass struct and clean up buffer logic

Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Su Chung <Su.Chung@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Fatemeh Darbehani
2018-10-30 11:32:40 -04:00
committed by Alex Deucher
parent e96938a09d
commit e210167522
5 changed files with 32 additions and 23 deletions
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2
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
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@@ -102,7 +102,7 @@ struct pp_smu_funcs_rv {
*/
void (*set_display_count)(struct pp_smu *pp, int count);
/* which SMU message? are reader and writer WM separate SMU msg? */
/* reader and writer WM's are sent together as part of one table*/
/*
* PPSMC_MSG_SetDriverDramAddrHigh
* PPSMC_MSG_SetDriverDramAddrLow