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Merge tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"There has been a lot of activity in the MTD subsystem recently, with a
number of SPI-NOR cleanups as well as the introduction of ECC engines
that can be used by SPI controllers (hence a few SPI patches in here).
Core MTD changes:
- Replace the expert mode symbols with a single helper
- Fix misuses of of_match_ptr()
- Remove partid and partname debugfs files
- tests: Fix eraseblock read speed miscalculation for lower partition
sizes
- TRX parser: Allow to use on MediaTek MIPS SoCs
MTD driver changes:
- spear_smi: use GFP_KERNEL
- mchp48l640: Add SPI ID table
- mchp23k256: Add SPI ID table
- blkdevs: Avoid soft lockups with some mtd/spi devices
- aspeed-smc: Improve probe resilience
Hyperbus changes:
- HBMC_AM654 should depend on ARCH_K3
NAND core changes:
- ECC:
- Add infrastructure to support hardware engines
- Add a new helper to retrieve the ECC context
- Provide a helper to retrieve a pilelined engine device
NAND-ECC changes:
- Macronix ECC engine:
- Add Macronix external ECC engine support
- Support SPI pipelined mode
- Make two read-only arrays static const
- Fix compile test issue
Raw NAND core changes:
- Fix misuses of of_match_node()
- Rework of_get_nand_bus_width()
- Remove of_get_nand_on_flash_bbt() wrapper
- Protect access to rawnand devices while in suspend
- bindings: Document the wp-gpios property
Rax NAND controller driver changes:
- atmel: Fix refcount issue in atmel_nand_controller_init
- nandsim:
- Add NS_PAGE_BYTE_SHIFT macro to replace the repeat pattern
- Merge repeat codes in ns_switch_state
- Replace overflow check with kzalloc to single kcalloc
- rockchip: Fix platform_get_irq.cocci warning
- stm32_fmc2: Add NAND Write Protect support
- pl353: Set the nand chip node as the flash node
- brcmnand: Fix sparse warnings in bcma_nand
- omap_elm: Remove redundant variable 'errors'
- gpmi:
- Support fast edo timings for mx28
- Validate controller clock rate
- Fix controller timings setting
- brcmnand:
- Add BCMA shim
- BCMA controller uses command shift of 0
- Allow platform data instantation
- Add platform data structure for BCMA
- Allow working without interrupts
- Move OF operations out of brcmnand_init_cs()
- Avoid pdev in brcmnand_init_cs()
- Allow SoC to provide I/O operations
- Assign soc as early as possible
Onenand changes:
- Check for error irq
SPI-NAND core changes:
- Delay a little bit the dirmap creation
- Create direct mapping descriptors for ECC operations
SPI-NAND driver changes:
- macronix: Use random program load
SPI NOR core changes:
- Move vendor specific code out of the core into vendor drivers.
- Unify all function and object names in the vendor modules.
- Make setup() callback optional to improve readability.
- Skip erase logic when the SPI_NOR_NO_ERASE flag is set at flash
declaration.
SPI changes:
- Macronix SPI controller:
- Fix the transmit path
- Create a helper to configure the controller before an operation
- Create a helper to ease the start of an operation
- Add support for direct mapping
- Add support for pipelined ECC operations
- spi-mem:
- Introduce a capability structure
- Check the controller extra capabilities
- cadence-quadspi/mxic: Provide capability structures
- Kill the spi_mem_dtr_supports_op() helper
- Add an ecc parameter to the spi_mem_op structure
Binding changes:
- Dropped mtd/cortina,gemini-flash.txt
- Convert BCM47xx partitions to json-schema
- Vendor prefixes: Clarify Macronix prefix
- SPI NAND: Convert spi-nand description file to yaml
- Raw NAND chip: Create a NAND chip description
- Raw NAND controller:
- Harmonize the property types
- Fix a comment in the examples
- Fix the reg property description
- Describe Macronix NAND ECC engine
- Macronix SPI controller:
- Document the nand-ecc-engine property
- Convert to yaml
- The interrupt property is not mandatory"
* tag 'mtd/changes-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (104 commits)
mtd: nand: ecc: mxic: Fix compile test issue
mtd: nand: mxic-ecc: make two read-only arrays static const
mtd: hyperbus: HBMC_AM654 should depend on ARCH_K3
mtd: core: Remove partid and partname debugfs files
dt-bindings: mtd: partitions: convert BCM47xx to the json-schema
mtd: tests: Fix eraseblock read speed miscalculation for lower partition sizes
mtd: rawnand: atmel: fix refcount issue in atmel_nand_controller_init
mtd: rawnand: rockchip: fix platform_get_irq.cocci warning
mtd: spi-nor: Skip erase logic when SPI_NOR_NO_ERASE is set
mtd: spi-nor: renumber flags
mtd: spi-nor: slightly change code style in spi_nor_sr_ready()
mtd: spi-nor: spansion: rename vendor specific functions and defines
mtd: spi-nor: spansion: convert USE_CLSR to a manufacturer flag
mtd: spi-nor: move all spansion specifics into spansion.c
mtd: spi-nor: spansion: slightly rework control flow in late_init()
mtd: spi-nor: micron-st: rename vendor specific functions and defines
mtd: spi-nor: micron-st: convert USE_FSR to a manufacturer flag
mtd: spi-nor: move all micron-st specifics into micron-st.c
mtd: spi-nor: xilinx: correct the debug message
mtd: spi-nor: xilinx: rename vendor specific functions and defines
...
This commit is contained in:
Linus Torvalds
@@ -89,6 +89,7 @@ enum spi_mem_data_dir {
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* @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
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* @data.buswidth: number of IO lanes used to send/receive the data
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* @data.dtr: whether the data should be sent in DTR mode or not
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* @data.ecc: whether error correction is required or not
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* @data.dir: direction of the transfer
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* @data.nbytes: number of data bytes to send/receive. Can be zero if the
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* operation does not involve transferring data
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@@ -119,6 +120,7 @@ struct spi_mem_op {
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struct {
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u8 buswidth;
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u8 dtr : 1;
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u8 ecc : 1;
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enum spi_mem_data_dir dir;
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unsigned int nbytes;
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union {
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@@ -285,6 +287,19 @@ struct spi_controller_mem_ops {
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unsigned long timeout_ms);
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};
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/**
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* struct spi_controller_mem_caps - SPI memory controller capabilities
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* @dtr: Supports DTR operations
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* @ecc: Supports operations with error correction
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*/
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struct spi_controller_mem_caps {
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bool dtr;
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bool ecc;
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};
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#define spi_mem_controller_is_capable(ctlr, cap) \
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((ctlr)->mem_caps && (ctlr)->mem_caps->cap)
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/**
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* struct spi_mem_driver - SPI memory driver
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* @spidrv: inherit from a SPI driver
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@@ -319,10 +334,6 @@ void spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
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bool spi_mem_default_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op);
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bool spi_mem_dtr_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op);
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#else
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static inline int
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spi_controller_dma_map_mem_op_data(struct spi_controller *ctlr,
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@@ -345,13 +356,6 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
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{
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return false;
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}
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static inline
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bool spi_mem_dtr_supports_op(struct spi_mem *mem,
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const struct spi_mem_op *op)
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{
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return false;
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}
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#endif /* CONFIG_SPI_MEM */
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int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op);
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@@ -24,6 +24,7 @@ struct ptp_system_timestamp;
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struct spi_controller;
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struct spi_transfer;
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struct spi_controller_mem_ops;
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struct spi_controller_mem_caps;
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/*
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* INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
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@@ -413,6 +414,7 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch
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* @mem_ops: optimized/dedicated operations for interactions with SPI memory.
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* This field is optional and should only be implemented if the
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* controller has native support for memory like operations.
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* @mem_caps: controller capabilities for the handling of memory operations.
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* @unprepare_message: undo any work done by prepare_message().
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* @slave_abort: abort the ongoing transfer request on an SPI slave controller
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* @cs_gpiods: Array of GPIO descs to use as chip select lines; one per CS
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@@ -632,6 +634,7 @@ struct spi_controller {
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/* Optimized handlers for SPI memory-like operations. */
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const struct spi_controller_mem_ops *mem_ops;
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const struct spi_controller_mem_caps *mem_caps;
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/* gpio chip select */
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struct gpio_desc **cs_gpiods;
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