Commit fb5f0049 authored by Sonic Zhang's avatar Sonic Zhang Committed by Bryan Wu
Browse files

[Blackfin] arch: Fix bug to Enable kernel to build for bf548 with PM. 



On BF548-EZKIT, build kernel faills with power management, video and audio enabled.
This patch fix this.

Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent c50e19f4

arch/blackfin/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -951,6 +951,8 @@ config PM_WAKEUP_SIC_IWR 
	depends on PM_WAKEUP_GPIO_BY_SIC_IWR

	default 0x80000000 if (BF537 || BF536 || BF534)

	default 0x100000 if (BF533 || BF532 || BF531)

	default 0x800000 if (BF549 || BF548 || BF547 || BF542)

	default 0x800000 if (BF527 || BF524 || BF522)



config PM_WAKEUP_GPIO_NUMBER

	int "Wakeup GPIO number"

arch/blackfin/mach-bf548/head.S

+4 −4
Original line number Diff line number Diff line
@@ -298,8 +298,8 @@ ENTRY(_start_dma_code) 
	w[p0] = r0.l;

	ssync;



	p0.h = hi(SIC_IWR);

	p0.l = lo(SIC_IWR);

	p0.h = hi(SIC_IWR0);

	p0.l = lo(SIC_IWR0);

	r0.l = 0x1;

	r0.h = 0x0;

	[p0] = r0;
@@ -395,8 +395,8 @@ ENTRY(_start_dma_code) 
	[P2] = R1;

	SSYNC;



	p0.h = hi(SIC_IWR);

	p0.l = lo(SIC_IWR);

	p0.h = hi(SIC_IWR0);

	p0.l = lo(SIC_IWR0);

	r0.l = lo(IWR_ENABLE_ALL);

	r0.h = hi(IWR_ENABLE_ALL);

	[p0] = r0;

arch/blackfin/mach-bf548/ints-priority.c

+1 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ void program_IAR(void) 
			    ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |

			    ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |

			    ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |

			    ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));

			    ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCH_POS));



	bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |

			    ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |

arch/blackfin/mach-common/dpmc.S

+38 −8
Original line number Diff line number Diff line
@@ -38,6 +38,9 @@ ENTRY(_unmask_wdog_wakeup_evt) 
#if defined(CONFIG_BF561)

	P0.H = hi(SICA_IWR1);

	P0.L = lo(SICA_IWR1);

#elif defined(CONFIG_BF54x) || defined(CONFIG_BF52x)

	P0.h = HI(SIC_IWR0);

	P0.l = LO(SIC_IWR0);

#else

	P0.h = HI(SIC_IWR);

	P0.l = LO(SIC_IWR);
@@ -236,7 +239,7 @@ ENTRY(_deep_sleep) 


	call _set_sic_iwr;



	call _set_sdram_srfs;

	call _set_dram_srfs;



	/* Clear all the interrupts,bits sticky */

	R0 = 0xFFFF (Z);
@@ -253,7 +256,7 @@ ENTRY(_deep_sleep) 
	SSYNC;

	IDLE;



	call _unset_sdram_srfs;

	call _unset_dram_srfs;



	call _test_pll_locked;
@@ -285,7 +288,7 @@ ENTRY(_sleep_deeper) 
	P3 = R0;

	R0 = IWR_ENABLE(0);

	call _set_sic_iwr;

	call _set_sdram_srfs;

	call _set_dram_srfs;



	/* Clear all the interrupts,bits sticky */

	R0 = 0xFFFF (Z);
@@ -360,7 +363,7 @@ ENTRY(_sleep_deeper) 
	IDLE;

	call _test_pll_locked;



	call _unset_sdram_srfs;

	call _unset_dram_srfs;



	STI R4;
@@ -368,25 +371,47 @@ ENTRY(_sleep_deeper) 
	( R7:0, P5:0 ) = [SP++];

	RTS;



ENTRY(_set_sdram_srfs)

	/*  set the sdram to self refresh mode */

ENTRY(_set_dram_srfs)

	/*  set the dram to self refresh mode */

#if defined(CONFIG_BF54x)

	P0.H = hi(EBIU_RSTCTL);

	P0.L = lo(EBIU_RSTCTL);

	R2 = [P0];

	R3.H = hi(SRREQ);

	R3.L = lo(SRREQ);

#else

	P0.H = hi(EBIU_SDGCTL);

	P0.L = lo(EBIU_SDGCTL);

	R2 = [P0];

	R3.H = hi(SRFS);

	R3.L = lo(SRFS);

#endif

	R2 = R2|R3;

	[P0] = R2;

	ssync;

#if defined(CONFIG_BF54x)

.LSRR_MODE:

	R2 = [P0];

	CC = BITTST(R2, 4);

	if !CC JUMP .LSRR_MODE;

#endif

	RTS;



ENTRY(_unset_sdram_srfs)

	/*  set the sdram out of self refresh mode */

ENTRY(_unset_dram_srfs)

	/*  set the dram out of self refresh mode */

#if defined(CONFIG_BF54x)

	P0.H = hi(EBIU_RSTCTL);

	P0.L = lo(EBIU_RSTCTL);

	R2 = [P0];

	R3.H = hi(SRREQ);

	R3.L = lo(SRREQ);

#else

	P0.H = hi(EBIU_SDGCTL);

	P0.L = lo(EBIU_SDGCTL);

	R2 = [P0];

	R3.H = hi(SRFS);

	R3.L = lo(SRFS);

#endif

	R3 = ~R3;

	R2 = R2&R3;

	[P0] = R2;
@@ -394,8 +419,13 @@ ENTRY(_unset_sdram_srfs) 
	RTS;



ENTRY(_set_sic_iwr)

#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)

	P0.H = hi(SIC_IWR0);

	P0.L = lo(SIC_IWR0);

#else

	P0.H = hi(SIC_IWR);

	P0.L = lo(SIC_IWR);

#endif

	[P0] = R0;

	SSYNC;

	RTS;

arch/blackfin/mach-common/pm.c

+16 −0
Original line number Diff line number Diff line
@@ -77,7 +77,15 @@ void bfin_pm_suspend_standby_enter(void) 


		gpio_pm_restore();



#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)

		bfin_write_SIC_IWR0(IWR_ENABLE_ALL);

		bfin_write_SIC_IWR1(IWR_ENABLE_ALL);

# ifdef CONFIG_BF54x

		bfin_write_SIC_IWR2(IWR_ENABLE_ALL);

# endif

#else

		bfin_write_SIC_IWR(IWR_ENABLE_ALL);

#endif



		local_irq_restore(flags);

	}
@@ -85,7 +93,15 @@ void bfin_pm_suspend_standby_enter(void) 


#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR)

	sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR);

# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)

	bfin_write_SIC_IWR0(IWR_ENABLE_ALL);

	bfin_write_SIC_IWR1(IWR_ENABLE_ALL);

#  ifdef CONFIG_BF54x

	bfin_write_SIC_IWR2(IWR_ENABLE_ALL);

#  endif

# else

	bfin_write_SIC_IWR(IWR_ENABLE_ALL);

# endif

#endif				/* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */

}