Krzysztof Kozlowski
a0d3aeaa34
Merge branch 'for-v6.20/dt-bindings-clk' into next/clk
...
Merge DT binding headers from topic branch, used by the driver.
2026-01-17 20:29:51 +01:00
Peter Griffin
52300cd894
dt-bindings: clock: google,gs101-clock: Add DPU clock management unit
...
Add dt schema documentation and clock IDs for the Display Process Unit
(DPU) clock management unit (CMU). This CMU feeds IPs such as image scaler,
enhancer and compressor.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org >
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Reviewed-by: André Draszik <andre.draszik@linaro.org >
Link: https://patch.msgid.link/20260113-dpu-clocks-v3-2-cb85424f2c72@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org >
2026-01-17 20:29:38 +01:00
Peter Griffin
3a2741fa31
dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering
...
Ensure children of cmu_top have alphanumeric ordering. Top is special as it
feeds all the other children CMUs. This ordering then matches the
clk-gs101.c file.
Reviewed-by: André Draszik <andre.draszik@linaro.org >
Signed-off-by: Peter Griffin <peter.griffin@linaro.org >
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Link: https://patch.msgid.link/20260113-dpu-clocks-v3-1-cb85424f2c72@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org >
2026-01-17 20:29:38 +01:00
Peter Griffin
2e8e9a2492
dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required
...
Each CMU (with the exception of cmu_top) has a corresponding sysreg bank
that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers.
The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of
bus components and MEMCLK gates the sram clock.
Now the clock driver supports automatic clock mode, to fully enable dynamic
root clock gating it is required to configure these registers. Update the
bindings documentation so that all CMUs (with the exception of
gs101-cmu-top) have samsung,sysreg as a required property.
Note this is NOT an ABI break, as if the property isn't specified the
clock driver will fallback to the current behaviour of not initializing
the registers. The system still boots, but bus components won't benefit
from dynamic root clock gating and dynamic power will be higher (which has
been the case until now anyway).
Additionally update the DT example to included the correct CMU size as
registers in that region are used for automatic clock mode.
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Reviewed-by: André Draszik <andre.draszik@linaro.org >
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Signed-off-by: Peter Griffin <peter.griffin@linaro.org >
Link: https://patch.msgid.link/20251222-automatic-clocks-v7-1-fec86fa89874@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org >
2025-12-22 12:42:54 +01:00
André Draszik
8c644749ab
dt-bindings: clock: google,gs101-clock: add power-domains
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The CMU can be part of a power domain, so we need to allow the relevant
property 'power-domains'.
Signed-off-by: André Draszik <andre.draszik@linaro.org >
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Reviewed-by: Peter Griffin <peter.griffin@linaro.org >
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2025-10-13 02:27:10 +02:00
Peter Griffin
01aea123b1
dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
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Add dt schema documentation and clock IDs for the High Speed Interface
2 (HSI2) clock management unit. This CMU feeds high speed interfaces
such as PCIe and UFS.
[AD: * keep CMUs in google,gs101.h sorted alphabetically
* resolve minor merge conflicts in google,gs101-clock.yaml
* s/ufs_embd/ufs s/mmc_card/mmc
Signed-off-by: Peter Griffin <peter.griffin@linaro.org >
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Signed-off-by: André Draszik <andre.draszik@linaro.org >
Link: https://lore.kernel.org/r/20240429-hsi0-gs101-v3-1-f233be0a2455@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2024-04-29 19:06:57 +02:00
André Draszik
dbf76c0d3d
dt-bindings: clock: google,gs101-clock: add HSI0 clock management unit
...
Add dt-schema documentation and clock IDs for the high speed interface
0 HSI0 clock management unit. This is used (amongst others) for USB.
While the usual (sed) script has been used to derive the linux clock
IDs from the data sheet, one manual tweak was applied to fix a typo
which we don't want to carry:
HSI0_USPDPDBG_USER -> HSI0_USBDPDBG_USER (note USB vs USP).
Signed-off-by: André Draszik <andre.draszik@linaro.org >
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Link: https://lore.kernel.org/r/20240423-hsi0-gs101-v1-1-2c3ddb50c720@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2024-04-25 09:06:09 +02:00
Arnd Bergmann
1422eb8585
Merge tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
...
Samsung DTS ARM64 changes for v6.9
Mostly work around Google GS101 SoC and Pixel phone (Oriole) adding
support for:
1. Multi Core Timer (MCT) clocksource.
2. Several clock controllers (DTS and DT bindings) and use new clocks in
several other device nodes.
3. More serial-interface instances: USI8 and USI12 with I2C.
Exynos850:
1. SPI and DMA controllers (PL330).
* tag 'samsung-dt64-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux :
arm64: dts: fsd: Add fifosize for UART in Device Tree
arm64: dts: exynos: gs101: minor whitespace cleanup
arm64: dts: exynos: gs101: enable i2c bus 12 on gs101-oriole
arm64: dts: exynos: gs101: define USI12 with I2C configuration
arm64: dts: exynos: gs101: enable cmu-peric1 clock controller
dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
arm64: dts: exynos: Add SPI nodes for Exynos850
arm64: dts: exynos: Add PDMA node for Exynos850
arm64: dts: exynos: gs101: use correct clocks for usi_uart
arm64: dts: exynos: gs101: use correct clocks for usi8
arm64: dts: exynos: gs101: sysreg_peric0 needs a clock
arm64: dts: exynos: gs101: enable eeprom on gs101-oriole
arm64: dts: exynos: gs101: define USI8 with I2C configuration
arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
arm64: dts: exynos: gs101: enable cmu-peric0 clock controller
arm64: dts: exynos: gs101: remove reg-io-width from serial
arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node
dt-bindings: clock: exynos850: Add PDMA clocks
dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit
Link: https://lore.kernel.org/r/20240218182141.31213-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de >
2024-02-29 16:10:36 +01:00
André Draszik
455061eb32
dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
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Add dt-schema documentation and clock IDs for the Connectivity
Peripheral 1 (PERIC1) clock management unit.
Signed-off-by: André Draszik <andre.draszik@linaro.org >
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org >
Reviewed-by: Peter Griffin <peter.griffin@linaro.org >
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org >
Reviewed-by: Rob Herring <robh@kernel.org >
Link: https://lore.kernel.org/r/20240201161258.1013664-3-andre.draszik@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2024-02-07 16:27:13 +01:00
Tudor Ambarus
f80c43887a
dt-bindings: clock: google,gs101-clock: add PERIC0 clock management unit
...
Add dt-schema documentation for the Connectivity Peripheral 0 (PERIC0)
clock management unit.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org >
Reviewed-by: Peter Griffin <peter.griffin@linaro.org >
Reviewed-by: Rob Herring <robh@kernel.org >
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org >
Link: https://lore.kernel.org/r/20240119111132.1290455-2-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2024-01-23 10:46:55 +01:00
Tudor Ambarus
1755c4b037
dt-bindings: clock: gs101: rename cmu_misc clock-names
...
'bus' and 'ip' are sufficient because naming is local to the module.
As the bindings have not made a release yet, rename the cmu_misc
clock-names.
Fixes: 0a910f1606robh@kernel.org >
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org >
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org >
Acked-by: Rob Herring <robh@kernel.org >
Link: https://lore.kernel.org/r/20240109114908.3623645-2-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2024-01-22 11:38:31 +01:00
Peter Griffin
0a910f1606
dt-bindings: clock: Add Google gs101 clock management unit bindings
...
Provide dt-schema documentation for Google gs101 SoC clock controller.
Currently this adds support for cmu_top, cmu_misc and cmu_apm.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org >
Signed-off-by: Peter Griffin <peter.griffin@linaro.org >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20231209233106.147416-3-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2023-12-10 14:59:40 +01:00
