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Intel Elkhart Lake Programmable Service Engine (PSE) includes two PCI devices that expose two different capabilities of GPIO and Timed I/O as a single PCI function through shared MMIO with below layout. GPIO: 0x0000 - 0x1000 TIO: 0x1000 - 0x2000 This driver enumerates the PCI parent device and creates auxiliary child devices for these capabilities. The actual functionalities are provided by their respective auxiliary drivers. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20251112034040.457801-2-raag.jadav@intel.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
25 lines
473 B
C
25 lines
473 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Elkhart Lake PSE I/O Auxiliary Device
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*
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* Copyright (c) 2025 Intel Corporation.
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*
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* Author: Raag Jadav <raag.jadav@intel.com>
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*/
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#ifndef _EHL_PSE_IO_AUX_H_
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#define _EHL_PSE_IO_AUX_H_
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#include <linux/ioport.h>
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#define EHL_PSE_IO_NAME "ehl_pse_io"
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#define EHL_PSE_GPIO_NAME "gpio"
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#define EHL_PSE_TIO_NAME "pps_tio"
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struct ehl_pse_io_data {
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struct resource mem;
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int irq;
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};
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#endif /* _EHL_PSE_IO_AUX_H_ */
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