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pic64gx has a clock controller compatible with mpfs-clkcfg. Don't permit the deprecated configuration that was never supported for this SoC. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20260113-glue-justifier-566ffab2ffd3@spud Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
103 lines
2.7 KiB
YAML
103 lines
2.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire Clock Control Module
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maintainers:
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- Daire McNamara <daire.mcnamara@microchip.com>
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description: |
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Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
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which gates and enables all peripheral clocks.
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This device tree binding describes 33 gate clocks. Clocks are referenced by
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user nodes by the CLKCFG node phandle and the clock index in the group, from
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0 to 32.
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properties:
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compatible:
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oneOf:
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- items:
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- const: microchip,pic64gx-clkcfg
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- const: microchip,mpfs-clkcfg
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- const: microchip,mpfs-clkcfg
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reg:
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oneOf:
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- items:
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- description: |
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clock config registers:
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These registers contain enable, reset & divider tables for the, cpu,
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axi, ahb and rtc/mtimer reference clocks as well as enable and reset
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for the peripheral clocks.
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- description: |
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mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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deprecated: true
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- items:
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- description: |
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mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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clocks:
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maxItems: 1
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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resets:
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maxItems: 1
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'#reset-cells':
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description:
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The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
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CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
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peripheral via the clock ID in its "resets" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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if:
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properties:
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compatible:
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contains:
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const: microchip,pic64gx-clkcfg
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then:
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properties:
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reg:
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maxItems: 1
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additionalProperties: false
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examples:
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# Clock Config node:
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- |
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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clkcfg: clock-controller@3E001000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x3E001000 0x1000>;
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clocks = <&ref>;
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#clock-cells = <1>;
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};
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};
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