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18cc1814d4
Some of the atomics return the result of a test applied after the atomic operation, and almost all architectures implement these as trivial wrappers around the underlying atomic. Specifically: * <atomic>_inc_and_test(v) is (<atomic>_inc_return(v) == 0) * <atomic>_dec_and_test(v) is (<atomic>_dec_return(v) == 0) * <atomic>_sub_and_test(i, v) is (<atomic>_sub_return(i, v) == 0) * <atomic>_add_negative(i, v) is (<atomic>_add_return(i, v) < 0) Rather than have these definitions duplicated in all architectures, with minor inconsistencies in formatting and documentation, let's make these operations optional, with default fallbacks as above. Implementations must now provide a preprocessor symbol. The instrumented atomics are updated accordingly. Both x86 and m68k have custom implementations, which are left as-is, given preprocessor symbols to avoid being overridden. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Palmer Dabbelt <palmer@sifive.com> Cc: Boqun Feng <boqun.feng@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/lkml/20180621121321.4761-16-mark.rutland@arm.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
238 lines
5.7 KiB
C
238 lines
5.7 KiB
C
/*
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* include/asm-xtensa/atomic.h
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*
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* Atomic operations that C can't guarantee us. Useful for resource counting..
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2008 Tensilica Inc.
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*/
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#ifndef _XTENSA_ATOMIC_H
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#define _XTENSA_ATOMIC_H
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#include <linux/stringify.h>
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#include <linux/types.h>
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#ifdef __KERNEL__
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#include <asm/processor.h>
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#include <asm/cmpxchg.h>
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#include <asm/barrier.h>
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#define ATOMIC_INIT(i) { (i) }
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/*
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* This Xtensa implementation assumes that the right mechanism
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* for exclusion is for locking interrupts to level EXCM_LEVEL.
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*
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* Locking interrupts looks like this:
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*
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* rsil a15, TOPLEVEL
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* <code>
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* wsr a15, PS
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* rsync
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*
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* Note that a15 is used here because the register allocation
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* done by the compiler is not guaranteed and a window overflow
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* may not occur between the rsil and wsr instructions. By using
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* a15 in the rsil, the machine is guaranteed to be in a state
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* where no register reference will cause an overflow.
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*/
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/**
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* atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v.
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*/
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#define atomic_read(v) READ_ONCE((v)->counter)
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/**
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* atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i.
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*/
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#define atomic_set(v,i) WRITE_ONCE((v)->counter, (i))
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#if XCHAL_HAVE_S32C1I
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#define ATOMIC_OP(op) \
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static inline void atomic_##op(int i, atomic_t * v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32i %1, %3, 0\n" \
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" wsr %1, scompare1\n" \
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" " #op " %0, %1, %2\n" \
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" s32c1i %0, %3, 0\n" \
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" bne %0, %1, 1b\n" \
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: "=&a" (result), "=&a" (tmp) \
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: "a" (i), "a" (v) \
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: "memory" \
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); \
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} \
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#define ATOMIC_OP_RETURN(op) \
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static inline int atomic_##op##_return(int i, atomic_t * v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32i %1, %3, 0\n" \
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" wsr %1, scompare1\n" \
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" " #op " %0, %1, %2\n" \
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" s32c1i %0, %3, 0\n" \
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" bne %0, %1, 1b\n" \
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" " #op " %0, %0, %2\n" \
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: "=&a" (result), "=&a" (tmp) \
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: "a" (i), "a" (v) \
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: "memory" \
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); \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(op) \
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static inline int atomic_fetch_##op(int i, atomic_t * v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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__asm__ __volatile__( \
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"1: l32i %1, %3, 0\n" \
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" wsr %1, scompare1\n" \
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" " #op " %0, %1, %2\n" \
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" s32c1i %0, %3, 0\n" \
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" bne %0, %1, 1b\n" \
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: "=&a" (result), "=&a" (tmp) \
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: "a" (i), "a" (v) \
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: "memory" \
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); \
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\
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return result; \
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}
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#else /* XCHAL_HAVE_S32C1I */
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#define ATOMIC_OP(op) \
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static inline void atomic_##op(int i, atomic_t * v) \
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{ \
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unsigned int vval; \
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\
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__asm__ __volatile__( \
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" rsil a15, "__stringify(TOPLEVEL)"\n"\
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" l32i %0, %2, 0\n" \
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" " #op " %0, %0, %1\n" \
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" s32i %0, %2, 0\n" \
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" wsr a15, ps\n" \
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" rsync\n" \
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: "=&a" (vval) \
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: "a" (i), "a" (v) \
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: "a15", "memory" \
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); \
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} \
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#define ATOMIC_OP_RETURN(op) \
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static inline int atomic_##op##_return(int i, atomic_t * v) \
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{ \
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unsigned int vval; \
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\
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__asm__ __volatile__( \
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" rsil a15,"__stringify(TOPLEVEL)"\n" \
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" l32i %0, %2, 0\n" \
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" " #op " %0, %0, %1\n" \
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" s32i %0, %2, 0\n" \
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" wsr a15, ps\n" \
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" rsync\n" \
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: "=&a" (vval) \
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: "a" (i), "a" (v) \
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: "a15", "memory" \
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); \
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\
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return vval; \
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}
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#define ATOMIC_FETCH_OP(op) \
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static inline int atomic_fetch_##op(int i, atomic_t * v) \
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{ \
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unsigned int tmp, vval; \
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\
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__asm__ __volatile__( \
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" rsil a15,"__stringify(TOPLEVEL)"\n" \
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" l32i %0, %3, 0\n" \
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" " #op " %1, %0, %2\n" \
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" s32i %1, %3, 0\n" \
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" wsr a15, ps\n" \
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" rsync\n" \
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: "=&a" (vval), "=&a" (tmp) \
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: "a" (i), "a" (v) \
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: "a15", "memory" \
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); \
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\
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return vval; \
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}
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#endif /* XCHAL_HAVE_S32C1I */
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OP_RETURN(op)
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ATOMIC_OPS(add)
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ATOMIC_OPS(sub)
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op)
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ATOMIC_OPS(and)
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ATOMIC_OPS(or)
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ATOMIC_OPS(xor)
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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/**
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* atomic_inc - increment atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1.
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*/
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#define atomic_inc(v) atomic_add(1,(v))
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/**
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* atomic_inc - increment atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1.
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*/
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#define atomic_inc_return(v) atomic_add_return(1,(v))
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/**
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* atomic_dec - decrement atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically decrements @v by 1.
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*/
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#define atomic_dec(v) atomic_sub(1,(v))
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/**
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* atomic_dec_return - decrement atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically decrements @v by 1.
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*/
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#define atomic_dec_return(v) atomic_sub_return(1,(v))
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#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_ATOMIC_H */
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