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Document the bindings for STM32MP25 PCIe Controller configured in root complex mode with one root port. Supports 4 INTx and MSI interrupts from the ARM GICv2m controller. STM32 PCIe may be in a power domain which is the case for the STM32MP25 based boards. Supports WAKE# from wake-gpios Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250820075411.1178729-4-christian.bruel@foss.st.com
34 lines
582 B
YAML
34 lines
582 B
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32MP25 PCIe RC/EP controller
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maintainers:
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- Christian Bruel <christian.bruel@foss.st.com>
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description:
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STM32MP25 PCIe RC/EP common properties
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properties:
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clocks:
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maxItems: 1
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description: PCIe system clock
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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access-controllers:
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maxItems: 1
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required:
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- clocks
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- resets
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additionalProperties: true
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