mirror of
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d60c471a86
This reverts commit 557a28811c.
This commit introduced an init sequence from downstream DT [1] in the
driver. As mentioned by the comment above the HSPHY_INIT_CFG macro for
this sequence:
/*
* The macro is used to define an initialization sequence. Each tuple
* is meant to program 'value' into phy register at 'offset' with 'delay'
* in us followed.
*/
Instead of corresponding to offsets into the phy register, the sequence
read by the downstream driver [2] is passed into ulpi_write [3] which
crafts the address-value pair into a new value and writes it into the
same register at USB_ULPI_VIEWPORT [4]. In other words, this init
sequence is programmed into the hardware in a totally different way than
downstream and is unlikely to achieve the desired result, if the hsphy
is working at all.
An alternative method needs to be found to write these init values at
the desired location. Fortunately mdm9607 did not land upstream yet [5]
and should have its compatible revised to use the generic one, instead
of a compatible that writes wrong data to the wrong registers.
[1]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/arch/arm/boot/dts/qcom/mdm9607.dtsi#585
[2]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#4183
[3]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#468
[4]: https://android.googlesource.com/kernel/msm/+/android-7.1.0_r0.2/drivers/usb/phy/phy-msm-usb.c#418
[5]: https://lore.kernel.org/linux-arm-msm/20210805222812.40731-1-konrad.dybcio@somainline.org/
Reported-by: Michael Srba <Michael.Srba@seznam.cz>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20221214223733.648167-1-marijn.suijten@somainline.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
91 lines
2.0 KiB
YAML
91 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
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maintainers:
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- Bryan O'Donoghue <bryan.odonoghue@linaro.org>
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description: |
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Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
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properties:
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compatible:
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enum:
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- qcom,usb-hs-28nm-femtophy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 0
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clocks:
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items:
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- description: rpmcc ref clock
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- description: PHY AHB clock
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- description: Rentention clock
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clock-names:
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items:
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- const: ref
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- const: ahb
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- const: sleep
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resets:
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items:
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- description: PHY core reset
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- description: POR reset
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reset-names:
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items:
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- const: phy
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- const: por
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vdd-supply:
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description: phandle to the regulator VDD supply node.
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vdda1p8-supply:
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description: phandle to the regulator 1.8V supply node.
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vdda3p3-supply:
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description: phandle to the regulator 3.3V supply node.
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required:
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- compatible
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- reg
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- "#phy-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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- vdd-supply
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- vdda1p8-supply
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- vdda3p3-supply
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-qcs404.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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usb2_phy_prim: phy@7a000 {
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compatible = "qcom,usb-hs-28nm-femtophy";
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reg = <0x0007a000 0x200>;
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#phy-cells = <0>;
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clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
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<&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
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<&gcc GCC_USB2A_PHY_SLEEP_CLK>;
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clock-names = "ref", "ahb", "sleep";
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resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
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<&gcc GCC_USB2A_PHY_BCR>;
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reset-names = "phy", "por";
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vdd-supply = <&vreg_l4_1p2>;
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vdda1p8-supply = <&vreg_l5_1p8>;
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vdda3p3-supply = <&vreg_l12_3p3>;
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};
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...
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