mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/
synced 2026-04-17 22:23:45 -04:00
57d72196df
The GICv5 architecture implements Interrupt Translation Service
(ITS) components in order to translate events coming from peripherals
into interrupt events delivered to the connected IRSes.
Events (ie MSI memory writes to ITS translate frame), are translated
by the ITS using tables kept in memory.
ITS translation tables for peripherals is kept in memory storage
(device table [DT] and Interrupt Translation Table [ITT]) that
is allocated by the driver on boot.
Both tables can be 1- or 2-level; the structure is chosen by the
driver after probing the ITS HW parameters and checking the
allowed table splits and supported {device/event}_IDbits.
DT table entries are allocated on demand (ie when a device is
probed); the DT table is sized using the number of supported
deviceID bits in that that's a system design decision (ie the
number of deviceID bits implemented should reflect the number
of devices expected in a system) therefore it makes sense to
allocate a DT table that can cater for the maximum number of
devices.
DT and ITT tables are allocated using the kmalloc interface;
the allocation size may be smaller than a page or larger,
and must provide contiguous memory pages.
LPIs INTIDs backing the device events are allocated one-by-one
and only upon Linux IRQ allocation; this to avoid preallocating
a large number of LPIs to cover the HW device MSI vector
size whereas few MSI entries are actually enabled by a device.
ITS cacheability/shareability attributes are programmed
according to the provided firmware ITS description.
The GICv5 partially reuses the GICv3 ITS MSI parent infrastructure
and adds functions required to retrieve the ITS translate frame
addresses out of msi-map and msi-parent properties to implement
the GICv5 ITS MSI parent callbacks.
Co-developed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Co-developed-by: Timothy Hayes <timothy.hayes@arm.com>
Signed-off-by: Timothy Hayes <timothy.hayes@arm.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-28-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
378 lines
10 KiB
C
378 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2025 ARM Limited, All Rights Reserved.
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*/
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#ifndef __LINUX_IRQCHIP_ARM_GIC_V5_H
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#define __LINUX_IRQCHIP_ARM_GIC_V5_H
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#include <linux/iopoll.h>
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#include <asm/cacheflush.h>
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#include <asm/smp.h>
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#include <asm/sysreg.h>
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#define GICV5_IPIS_PER_CPU MAX_IPI
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/*
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* INTID handling
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*/
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#define GICV5_HWIRQ_ID GENMASK(23, 0)
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#define GICV5_HWIRQ_TYPE GENMASK(31, 29)
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#define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0)
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#define GICV5_HWIRQ_TYPE_PPI UL(0x1)
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#define GICV5_HWIRQ_TYPE_LPI UL(0x2)
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#define GICV5_HWIRQ_TYPE_SPI UL(0x3)
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/*
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* Tables attributes
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*/
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#define GICV5_NO_READ_ALLOC 0b0
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#define GICV5_READ_ALLOC 0b1
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#define GICV5_NO_WRITE_ALLOC 0b0
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#define GICV5_WRITE_ALLOC 0b1
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#define GICV5_NON_CACHE 0b00
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#define GICV5_WB_CACHE 0b01
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#define GICV5_WT_CACHE 0b10
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#define GICV5_NON_SHARE 0b00
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#define GICV5_OUTER_SHARE 0b10
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#define GICV5_INNER_SHARE 0b11
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/*
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* IRS registers and tables structures
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*/
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#define GICV5_IRS_IDR1 0x0004
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#define GICV5_IRS_IDR2 0x0008
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#define GICV5_IRS_IDR5 0x0014
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#define GICV5_IRS_IDR6 0x0018
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#define GICV5_IRS_IDR7 0x001c
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#define GICV5_IRS_CR0 0x0080
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#define GICV5_IRS_CR1 0x0084
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#define GICV5_IRS_SYNCR 0x00c0
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#define GICV5_IRS_SYNC_STATUSR 0x00c4
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#define GICV5_IRS_SPI_SELR 0x0108
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#define GICV5_IRS_SPI_CFGR 0x0114
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#define GICV5_IRS_SPI_STATUSR 0x0118
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#define GICV5_IRS_PE_SELR 0x0140
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#define GICV5_IRS_PE_STATUSR 0x0144
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#define GICV5_IRS_PE_CR0 0x0148
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#define GICV5_IRS_IST_BASER 0x0180
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#define GICV5_IRS_IST_CFGR 0x0190
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#define GICV5_IRS_IST_STATUSR 0x0194
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#define GICV5_IRS_MAP_L2_ISTR 0x01c0
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#define GICV5_IRS_IDR1_PRIORITY_BITS GENMASK(22, 20)
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#define GICV5_IRS_IDR1_IAFFID_BITS GENMASK(19, 16)
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#define GICV5_IRS_IDR1_PRIORITY_BITS_1BITS 0b000
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#define GICV5_IRS_IDR1_PRIORITY_BITS_2BITS 0b001
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#define GICV5_IRS_IDR1_PRIORITY_BITS_3BITS 0b010
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#define GICV5_IRS_IDR1_PRIORITY_BITS_4BITS 0b011
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#define GICV5_IRS_IDR1_PRIORITY_BITS_5BITS 0b100
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#define GICV5_IRS_IDR2_ISTMD_SZ GENMASK(19, 15)
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#define GICV5_IRS_IDR2_ISTMD BIT(14)
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#define GICV5_IRS_IDR2_IST_L2SZ GENMASK(13, 11)
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#define GICV5_IRS_IDR2_IST_LEVELS BIT(10)
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#define GICV5_IRS_IDR2_MIN_LPI_ID_BITS GENMASK(9, 6)
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#define GICV5_IRS_IDR2_LPI BIT(5)
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#define GICV5_IRS_IDR2_ID_BITS GENMASK(4, 0)
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#define GICV5_IRS_IDR5_SPI_RANGE GENMASK(24, 0)
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#define GICV5_IRS_IDR6_SPI_IRS_RANGE GENMASK(24, 0)
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#define GICV5_IRS_IDR7_SPI_BASE GENMASK(23, 0)
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#define GICV5_IRS_IST_L2SZ_SUPPORT_4KB(r) FIELD_GET(BIT(11), (r))
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#define GICV5_IRS_IST_L2SZ_SUPPORT_16KB(r) FIELD_GET(BIT(12), (r))
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#define GICV5_IRS_IST_L2SZ_SUPPORT_64KB(r) FIELD_GET(BIT(13), (r))
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#define GICV5_IRS_CR0_IDLE BIT(1)
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#define GICV5_IRS_CR0_IRSEN BIT(0)
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#define GICV5_IRS_CR1_VPED_WA BIT(15)
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#define GICV5_IRS_CR1_VPED_RA BIT(14)
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#define GICV5_IRS_CR1_VMD_WA BIT(13)
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#define GICV5_IRS_CR1_VMD_RA BIT(12)
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#define GICV5_IRS_CR1_VPET_WA BIT(11)
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#define GICV5_IRS_CR1_VPET_RA BIT(10)
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#define GICV5_IRS_CR1_VMT_WA BIT(9)
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#define GICV5_IRS_CR1_VMT_RA BIT(8)
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#define GICV5_IRS_CR1_IST_WA BIT(7)
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#define GICV5_IRS_CR1_IST_RA BIT(6)
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#define GICV5_IRS_CR1_IC GENMASK(5, 4)
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#define GICV5_IRS_CR1_OC GENMASK(3, 2)
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#define GICV5_IRS_CR1_SH GENMASK(1, 0)
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#define GICV5_IRS_SYNCR_SYNC BIT(31)
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#define GICV5_IRS_SYNC_STATUSR_IDLE BIT(0)
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#define GICV5_IRS_SPI_STATUSR_V BIT(1)
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#define GICV5_IRS_SPI_STATUSR_IDLE BIT(0)
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#define GICV5_IRS_SPI_SELR_ID GENMASK(23, 0)
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#define GICV5_IRS_SPI_CFGR_TM BIT(0)
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#define GICV5_IRS_PE_SELR_IAFFID GENMASK(15, 0)
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#define GICV5_IRS_PE_STATUSR_V BIT(1)
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#define GICV5_IRS_PE_STATUSR_IDLE BIT(0)
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#define GICV5_IRS_PE_CR0_DPS BIT(0)
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#define GICV5_IRS_IST_STATUSR_IDLE BIT(0)
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#define GICV5_IRS_IST_CFGR_STRUCTURE BIT(16)
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#define GICV5_IRS_IST_CFGR_ISTSZ GENMASK(8, 7)
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#define GICV5_IRS_IST_CFGR_L2SZ GENMASK(6, 5)
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#define GICV5_IRS_IST_CFGR_LPI_ID_BITS GENMASK(4, 0)
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#define GICV5_IRS_IST_CFGR_STRUCTURE_LINEAR 0b0
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#define GICV5_IRS_IST_CFGR_STRUCTURE_TWO_LEVEL 0b1
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#define GICV5_IRS_IST_CFGR_ISTSZ_4 0b00
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#define GICV5_IRS_IST_CFGR_ISTSZ_8 0b01
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#define GICV5_IRS_IST_CFGR_ISTSZ_16 0b10
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#define GICV5_IRS_IST_CFGR_L2SZ_4K 0b00
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#define GICV5_IRS_IST_CFGR_L2SZ_16K 0b01
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#define GICV5_IRS_IST_CFGR_L2SZ_64K 0b10
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#define GICV5_IRS_IST_BASER_ADDR_MASK GENMASK_ULL(55, 6)
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#define GICV5_IRS_IST_BASER_VALID BIT_ULL(0)
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#define GICV5_IRS_MAP_L2_ISTR_ID GENMASK(23, 0)
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#define GICV5_ISTL1E_VALID BIT_ULL(0)
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#define GICV5_ISTL1E_L2_ADDR_MASK GENMASK_ULL(55, 12)
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/*
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* ITS registers and tables structures
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*/
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#define GICV5_ITS_IDR1 0x0004
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#define GICV5_ITS_IDR2 0x0008
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#define GICV5_ITS_CR0 0x0080
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#define GICV5_ITS_CR1 0x0084
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#define GICV5_ITS_DT_BASER 0x00c0
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#define GICV5_ITS_DT_CFGR 0x00d0
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#define GICV5_ITS_DIDR 0x0100
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#define GICV5_ITS_EIDR 0x0108
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#define GICV5_ITS_INV_EVENTR 0x010c
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#define GICV5_ITS_INV_DEVICER 0x0110
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#define GICV5_ITS_STATUSR 0x0120
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#define GICV5_ITS_SYNCR 0x0140
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#define GICV5_ITS_SYNC_STATUSR 0x0148
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#define GICV5_ITS_IDR1_L2SZ GENMASK(10, 8)
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#define GICV5_ITS_IDR1_ITT_LEVELS BIT(7)
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#define GICV5_ITS_IDR1_DT_LEVELS BIT(6)
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#define GICV5_ITS_IDR1_DEVICEID_BITS GENMASK(5, 0)
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#define GICV5_ITS_IDR1_L2SZ_SUPPORT_4KB(r) FIELD_GET(BIT(8), (r))
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#define GICV5_ITS_IDR1_L2SZ_SUPPORT_16KB(r) FIELD_GET(BIT(9), (r))
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#define GICV5_ITS_IDR1_L2SZ_SUPPORT_64KB(r) FIELD_GET(BIT(10), (r))
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#define GICV5_ITS_IDR2_XDMN_EVENTs GENMASK(6, 5)
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#define GICV5_ITS_IDR2_EVENTID_BITS GENMASK(4, 0)
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#define GICV5_ITS_CR0_IDLE BIT(1)
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#define GICV5_ITS_CR0_ITSEN BIT(0)
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#define GICV5_ITS_CR1_ITT_RA BIT(7)
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#define GICV5_ITS_CR1_DT_RA BIT(6)
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#define GICV5_ITS_CR1_IC GENMASK(5, 4)
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#define GICV5_ITS_CR1_OC GENMASK(3, 2)
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#define GICV5_ITS_CR1_SH GENMASK(1, 0)
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#define GICV5_ITS_DT_CFGR_STRUCTURE BIT(16)
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#define GICV5_ITS_DT_CFGR_L2SZ GENMASK(7, 6)
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#define GICV5_ITS_DT_CFGR_DEVICEID_BITS GENMASK(5, 0)
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#define GICV5_ITS_DT_BASER_ADDR_MASK GENMASK_ULL(55, 3)
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#define GICV5_ITS_INV_DEVICER_I BIT(31)
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#define GICV5_ITS_INV_DEVICER_EVENTID_BITS GENMASK(5, 1)
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#define GICV5_ITS_INV_DEVICER_L1 BIT(0)
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#define GICV5_ITS_DIDR_DEVICEID GENMASK_ULL(31, 0)
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#define GICV5_ITS_EIDR_EVENTID GENMASK(15, 0)
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#define GICV5_ITS_INV_EVENTR_I BIT(31)
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#define GICV5_ITS_INV_EVENTR_ITT_L2SZ GENMASK(2, 1)
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#define GICV5_ITS_INV_EVENTR_L1 BIT(0)
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#define GICV5_ITS_STATUSR_IDLE BIT(0)
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#define GICV5_ITS_SYNCR_SYNC BIT_ULL(63)
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#define GICV5_ITS_SYNCR_SYNCALL BIT_ULL(32)
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#define GICV5_ITS_SYNCR_DEVICEID GENMASK_ULL(31, 0)
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#define GICV5_ITS_SYNC_STATUSR_IDLE BIT(0)
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#define GICV5_DTL1E_VALID BIT_ULL(0)
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/* Note that there is no shift for the address by design */
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#define GICV5_DTL1E_L2_ADDR_MASK GENMASK_ULL(55, 3)
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#define GICV5_DTL1E_SPAN GENMASK_ULL(63, 60)
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#define GICV5_DTL2E_VALID BIT_ULL(0)
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#define GICV5_DTL2E_ITT_L2SZ GENMASK_ULL(2, 1)
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/* Note that there is no shift for the address by design */
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#define GICV5_DTL2E_ITT_ADDR_MASK GENMASK_ULL(55, 3)
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#define GICV5_DTL2E_ITT_DSWE BIT_ULL(57)
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#define GICV5_DTL2E_ITT_STRUCTURE BIT_ULL(58)
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#define GICV5_DTL2E_EVENT_ID_BITS GENMASK_ULL(63, 59)
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#define GICV5_ITTL1E_VALID BIT_ULL(0)
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/* Note that there is no shift for the address by design */
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#define GICV5_ITTL1E_L2_ADDR_MASK GENMASK_ULL(55, 3)
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#define GICV5_ITTL1E_SPAN GENMASK_ULL(63, 60)
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#define GICV5_ITTL2E_LPI_ID GENMASK_ULL(23, 0)
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#define GICV5_ITTL2E_DAC GENMASK_ULL(29, 28)
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#define GICV5_ITTL2E_VIRTUAL BIT_ULL(30)
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#define GICV5_ITTL2E_VALID BIT_ULL(31)
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#define GICV5_ITTL2E_VM_ID GENMASK_ULL(47, 32)
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#define GICV5_ITS_DT_ITT_CFGR_L2SZ_4k 0b00
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#define GICV5_ITS_DT_ITT_CFGR_L2SZ_16k 0b01
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#define GICV5_ITS_DT_ITT_CFGR_L2SZ_64k 0b10
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#define GICV5_ITS_DT_ITT_CFGR_STRUCTURE_LINEAR 0
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#define GICV5_ITS_DT_ITT_CFGR_STRUCTURE_TWO_LEVEL 1
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#define GICV5_ITS_HWIRQ_DEVICE_ID GENMASK_ULL(31, 0)
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#define GICV5_ITS_HWIRQ_EVENT_ID GENMASK_ULL(63, 32)
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/*
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* Global Data structures and functions
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*/
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struct gicv5_chip_data {
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struct fwnode_handle *fwnode;
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struct irq_domain *ppi_domain;
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struct irq_domain *spi_domain;
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struct irq_domain *lpi_domain;
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struct irq_domain *ipi_domain;
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u32 global_spi_count;
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u8 cpuif_pri_bits;
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u8 cpuif_id_bits;
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u8 irs_pri_bits;
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struct {
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__le64 *l1ist_addr;
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u32 l2_size;
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u8 l2_bits;
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bool l2;
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} ist;
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};
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extern struct gicv5_chip_data gicv5_global_data __read_mostly;
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struct gicv5_irs_chip_data {
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struct list_head entry;
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struct fwnode_handle *fwnode;
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void __iomem *irs_base;
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u32 flags;
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u32 spi_min;
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u32 spi_range;
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raw_spinlock_t spi_config_lock;
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};
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static inline int gicv5_wait_for_op_s_atomic(void __iomem *addr, u32 offset,
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const char *reg_s, u32 mask,
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u32 *val)
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{
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void __iomem *reg = addr + offset;
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u32 tmp;
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int ret;
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ret = readl_poll_timeout_atomic(reg, tmp, tmp & mask, 1, 10 * USEC_PER_MSEC);
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if (unlikely(ret == -ETIMEDOUT)) {
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pr_err_ratelimited("%s timeout...\n", reg_s);
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return ret;
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}
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if (val)
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*val = tmp;
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return 0;
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}
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static inline int gicv5_wait_for_op_s(void __iomem *addr, u32 offset,
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const char *reg_s, u32 mask)
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{
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void __iomem *reg = addr + offset;
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u32 val;
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int ret;
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ret = readl_poll_timeout(reg, val, val & mask, 1, 10 * USEC_PER_MSEC);
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if (unlikely(ret == -ETIMEDOUT)) {
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pr_err_ratelimited("%s timeout...\n", reg_s);
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return ret;
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}
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return 0;
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}
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#define gicv5_wait_for_op_atomic(base, reg, mask, val) \
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gicv5_wait_for_op_s_atomic(base, reg, #reg, mask, val)
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#define gicv5_wait_for_op(base, reg, mask) \
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gicv5_wait_for_op_s(base, reg, #reg, mask)
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void __init gicv5_init_lpi_domain(void);
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void __init gicv5_free_lpi_domain(void);
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int gicv5_irs_of_probe(struct device_node *parent);
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void gicv5_irs_remove(void);
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int gicv5_irs_enable(void);
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void gicv5_irs_its_probe(void);
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int gicv5_irs_register_cpu(int cpuid);
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int gicv5_irs_cpu_to_iaffid(int cpu_id, u16 *iaffid);
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struct gicv5_irs_chip_data *gicv5_irs_lookup_by_spi_id(u32 spi_id);
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int gicv5_spi_irq_set_type(struct irq_data *d, unsigned int type);
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int gicv5_irs_iste_alloc(u32 lpi);
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void gicv5_irs_syncr(void);
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struct gicv5_its_devtab_cfg {
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union {
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struct {
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__le64 *devtab;
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} linear;
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struct {
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__le64 *l1devtab;
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__le64 **l2ptrs;
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} l2;
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};
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u32 cfgr;
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};
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struct gicv5_its_itt_cfg {
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union {
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struct {
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__le64 *itt;
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unsigned int num_ents;
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} linear;
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struct {
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__le64 *l1itt;
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__le64 **l2ptrs;
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unsigned int num_l1_ents;
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u8 l2sz;
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} l2;
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};
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u8 event_id_bits;
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bool l2itt;
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};
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void gicv5_init_lpis(u32 max);
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void gicv5_deinit_lpis(void);
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int gicv5_alloc_lpi(void);
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void gicv5_free_lpi(u32 lpi);
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void __init gicv5_its_of_probe(struct device_node *parent);
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#endif
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