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8a59954192
The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add a new device tree binding document for nvidia,tegra264-cmdqv. Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv property. This property is a phandle to the CMDQV device node, allowing the SMMU driver to associate with its corresponding CMDQV instance. Restrict this property usage to Nvidia Tegra264 only. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Nicolin Chen <nicolinc@nvidia.com> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
43 lines
949 B
YAML
43 lines
949 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra264 CMDQV
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description:
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The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
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on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
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maintainers:
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- Nicolin Chen <nicolinc@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra264-cmdqv
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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cmdqv@5200000 {
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compatible = "nvidia,tegra264-cmdqv";
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reg = <0x5200000 0x830000>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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};
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