mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/
synced 2026-04-18 06:33:43 -04:00
58e69e8f9c
Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm Kaanapali, which is compatible with X1E80100, use fallback to indicate this. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20251021-knp-cpufreq-v2-1-95391d66c84e@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
57 lines
1.3 KiB
YAML
57 lines
1.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
|
|
|
|
maintainers:
|
|
- Sibi Sankar <quic_sibis@quicinc.com>
|
|
|
|
description:
|
|
The CPUSS Control Processor (CPUCP) mailbox controller enables communication
|
|
between AP and CPUCP by acting as a doorbell between them.
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- items:
|
|
- enum:
|
|
- qcom,glymur-cpucp-mbox
|
|
- qcom,kaanapali-cpucp-mbox
|
|
- qcom,sm8750-cpucp-mbox
|
|
- const: qcom,x1e80100-cpucp-mbox
|
|
- enum:
|
|
- qcom,x1e80100-cpucp-mbox
|
|
|
|
reg:
|
|
items:
|
|
- description: CPUCP rx register region
|
|
- description: CPUCP tx register region
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
"#mbox-cells":
|
|
const: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- "#mbox-cells"
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
mailbox@17430000 {
|
|
compatible = "qcom,x1e80100-cpucp-mbox";
|
|
reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
};
|