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e2f085ab86
Improve the binding example by fixing indentation and adding missing blank lines for better readability. Also correct the OPP clock values to match the actual SM6150 DTS configuration. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/685342/ Link: https://lore.kernel.org/r/20251104-add-displayport-support-to-qcs615-devicetree-v7-2-e51669170a6f@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
256 lines
6.9 KiB
YAML
256 lines
6.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM6150 Display MDSS
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maintainers:
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- Abhinav Kumar <quic_abhinavk@quicinc.com>
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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description:
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Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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bindings of MDSS are mentioned for SM6150 target.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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items:
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- const: qcom,sm6150-mdss
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display hf axi clock
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core
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iommus:
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maxItems: 1
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interconnects:
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maxItems: 2
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interconnect-names:
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maxItems: 2
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sm6150-dpu
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"^displayport-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,sm6150-dp
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"^dsi@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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items:
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- const: qcom,sm6150-dsi-ctrl
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- const: qcom,mdss-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sm6150-dsi-phy-14nm
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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display-subsystem@ae00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sm6150-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "mdp0-mem", "cpu-cfg";
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power-domains = <&dispcc_mdss_gdsc>;
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clocks = <&dispcc_mdss_ahb_clk>,
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<&gcc_disp_hf_axi_clk>,
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<&dispcc_mdss_mdp_clk>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x800 0x0>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sm6150-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&dispcc_mdss_ahb_clk>,
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<&gcc_disp_hf_axi_clk>,
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<&dispcc_mdss_mdp_clk>,
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<&dispcc_mdss_vsync_clk>;
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clock-names = "iface", "bus", "core", "vsync";
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assigned-clocks = <&dispcc_mdss_vsync_clk>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf0_out: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-192000000 {
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opp-hz = /bits/ 64 <192000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-256000000 {
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opp-hz = /bits/ 64 <256000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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dsi@ae94000 {
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compatible = "qcom,sm6150-dsi-ctrl",
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"qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc_mdss_byte0_clk>,
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<&dispcc_mdss_byte0_intf_clk>,
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<&dispcc_mdss_pclk0_clk>,
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<&dispcc_mdss_esc0_clk>,
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<&dispcc_mdss_ahb_clk>,
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<&gcc_disp_hf_axi_clk>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
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<&dispcc_mdss_pclk0_clk_src>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>,
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<&mdss_dsi0_phy 1>;
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operating-points-v2 = <&dsi0_opp_table>;
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phys = <&mdss_dsi0_phy>;
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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};
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};
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};
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dsi0_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-164000000 {
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opp-hz = /bits/ 64 <164000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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};
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};
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mdss_dsi0_phy: phy@ae94400 {
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compatible = "qcom,sm6150-dsi-phy-14nm";
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reg = <0x0ae94400 0x100>,
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<0x0ae94500 0x300>,
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<0x0ae94800 0x188>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc_mdss_ahb_clk>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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};
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};
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...
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