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b93bdff44a
Add DPU and MDSS schemas to describe MDSS and DPU blocks on the Qualcomm SM6115 platform. Configuration for DSI/PHY is shared with QCM2290 so compatibles are reused. Lack of dsi phy supply in example is intended due to fact on qcm2290, sm6115 and sm6125 this phy is supplied via power domain, not regulator. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/512872/ Link: https://lore.kernel.org/r/20221124001708.25720-2-a39.skl@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
95 lines
2.2 KiB
YAML
95 lines
2.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DPU dt properties for SM6115 target
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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$ref: /schemas/display/msm/dpu-common.yaml#
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properties:
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compatible:
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items:
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- const: qcom,sm6115-dpu
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reg:
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items:
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- description: MDP register set
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- description: VBIF register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display AXI
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- description: Display AHB
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- description: Display core
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- description: Display lut
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- description: Display rotator
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- description: Display vsync
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clock-names:
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items:
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- const: bus
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- const: iface
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- const: core
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- const: lut
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- const: rot
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- const: vsync
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
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#include <dt-bindings/clock/qcom,gcc-sm6115.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-controller@5e01000 {
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compatible = "qcom,sm6115-dpu";
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reg = <0x05e01000 0x8f000>,
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<0x05eb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmpd SM6115_VDDCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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...
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