Commit 0157e111 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/sophgo' 

- Check for existence of struct cdns_pcie.ops before using it to allow
  Cadence drivers that don't need to supply ops (Chen Wang)

- Add DT binding and driver for the Sophgo SG2042 PCIe controller (Chen
  Wang)

* pci/controller/sophgo:
  PCI: sg2042: Add Sophgo SG2042 PCIe driver
  PCI: cadence: Check for the existence of cdns_pcie::ops before using it
  dt-bindings: pci: Add Sophgo SG2042 PCIe host
parents 2ee6181f 1c72774d

Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)



description:

  Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.



maintainers:

  - Chen Wang <unicorn_wang@outlook.com>



properties:

  compatible:

    const: sophgo,sg2042-pcie-host



  reg:

    maxItems: 2



  reg-names:

    items:

      - const: reg

      - const: cfg



  vendor-id:

    const: 0x1f1c



  device-id:

    const: 0x2042



  msi-parent: true



allOf:

  - $ref: cdns-pcie-host.yaml#



required:

  - compatible

  - reg

  - reg-names



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    pcie@62000000 {

      compatible = "sophgo,sg2042-pcie-host";

      device_type = "pci";

      reg = <0x62000000  0x00800000>,

            <0x48000000  0x00001000>;

      reg-names = "reg", "cfg";

      #address-cells = <3>;

      #size-cells = <2>;

      ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,

               <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;

      bus-range = <0x00 0xff>;

      vendor-id = <0x1f1c>;

      device-id = <0x2042>;

      cdns,no-bar-match-nbits = <48>;

      msi-parent = <&msi>;

    };

drivers/pci/controller/cadence/Kconfig

+10 −0
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@@ -42,6 +42,15 @@ config PCIE_CADENCE_PLAT_EP 
	  endpoint mode. This PCIe controller may be embedded into many

	  different vendors SoCs.



config PCIE_SG2042_HOST

	tristate "Sophgo SG2042 PCIe controller (host mode)"

	depends on OF && (ARCH_SOPHGO || COMPILE_TEST)

	select PCIE_CADENCE_HOST

	help

	  Say Y here if you want to support the Sophgo SG2042 PCIe platform

	  controller in host mode. Sophgo SG2042 PCIe controller uses Cadence

	  PCIe core.



config PCI_J721E

	tristate

	select PCIE_CADENCE_HOST if PCI_J721E_HOST != n
@@ -67,4 +76,5 @@ config PCI_J721E_EP 
	  Say Y here if you want to support the TI J721E PCIe platform

	  controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe

	  core.



endmenu

drivers/pci/controller/cadence/Makefile

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@@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o 
obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o

obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o

obj-$(CONFIG_PCI_J721E) += pci-j721e.o

obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o

drivers/pci/controller/cadence/pcie-cadence-host.c

+1 −1
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@@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) 
	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);

	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);



	if (pcie->ops->cpu_addr_fixup)

	if (pcie->ops && pcie->ops->cpu_addr_fixup)

		cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);



	addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |

drivers/pci/controller/cadence/pcie-cadence.c

+2 −2
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@@ -106,7 +106,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, 
	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);



	/* Set the CPU address */

	if (pcie->ops->cpu_addr_fixup)

	if (pcie->ops && pcie->ops->cpu_addr_fixup)

		cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);



	addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
@@ -137,7 +137,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, 
	}



	/* Set the CPU address */

	if (pcie->ops->cpu_addr_fixup)

	if (pcie->ops && pcie->ops->cpu_addr_fixup)

		cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);



	addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |