Commit 0159f88a authored by Melissa Wen's avatar Melissa Wen Committed by Alex Deucher
Browse files

drm/amd/display: remove redundant freesync parser for DP 



When updating connector under drm_edid infrastructure, many calculations
and validations are already done and become redundant inside AMD driver.
Remove those driver-specific code in favor of the DRM common code.

Signed-off-by: default avatarMelissa Wen <mwen@igalia.com>
Co-developed-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Reviewed-by: default avatarAlex Hung <alex.hung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent abb91c54

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+4 −66
Original line number Diff line number Diff line
@@ -12134,9 +12134,6 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 
				    const struct drm_edid *drm_edid)

{

	int i = 0;

	const struct detailed_timing *timing;

	const struct detailed_non_pixel *data;

	const struct detailed_data_monitor_range *range;

	struct amdgpu_dm_connector *amdgpu_dm_connector =

			to_amdgpu_dm_connector(connector);

	struct dm_connector_state *dm_con_state = NULL;
@@ -12163,8 +12160,6 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 


		amdgpu_dm_connector->min_vfreq = 0;

		amdgpu_dm_connector->max_vfreq = 0;

		connector->display_info.monitor_range.min_vfreq = 0;

		connector->display_info.monitor_range.max_vfreq = 0;

		freesync_capable = false;



		goto update;
@@ -12184,67 +12179,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 


	if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||

		     sink->sink_signal == SIGNAL_TYPE_EDP)) {

		bool edid_check_required = false;



		if (amdgpu_dm_connector->dc_link &&

		    amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {

			if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) {

		amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;

		amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;

				if (amdgpu_dm_connector->max_vfreq -

				    amdgpu_dm_connector->min_vfreq > 10)

					freesync_capable = true;

			} else {

				edid_check_required = edid->version > 1 ||

						      (edid->version == 1 &&

						       edid->revision > 1);

			}

		}



		if (edid_check_required) {

			for (i = 0; i < 4; i++) {



				timing	= &edid->detailed_timings[i];

				data	= &timing->data.other_data;

				range	= &data->data.range;

				/*

				 * Check if monitor has continuous frequency mode

				 */

				if (data->type != EDID_DETAIL_MONITOR_RANGE)

					continue;

				/*

				 * Check for flag range limits only. If flag == 1 then

				 * no additional timing information provided.

				 * Default GTF, GTF Secondary curve and CVT are not

				 * supported

				 */

				if (range->flags != 1)

					continue;



				connector->display_info.monitor_range.min_vfreq = range->min_vfreq;

				connector->display_info.monitor_range.max_vfreq = range->max_vfreq;



				if (edid->revision >= 4) {

					if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)

						connector->display_info.monitor_range.min_vfreq += 255;

					if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)

						connector->display_info.monitor_range.max_vfreq += 255;

				}



				amdgpu_dm_connector->min_vfreq =

					connector->display_info.monitor_range.min_vfreq;

				amdgpu_dm_connector->max_vfreq =

					connector->display_info.monitor_range.max_vfreq;



				break;

			}



			if (amdgpu_dm_connector->max_vfreq -

			    amdgpu_dm_connector->min_vfreq > 10) {



		if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)

			freesync_capable = true;

			}

		}

		parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);



		if (vsdb_info.replay_mode) {