Commit 025cf789 authored by Wei Fang's avatar Wei Fang Committed by Shawn Guo
Browse files

arm64: dts: imx95-19x19-evk: add ENETC 0 support 



Add ENETC 0 (1G ethernet port) support for i.MX95-19x19-EVK board. In
addition, because all ENETC instances share MDIO bus, so enable EMDIO
at the same time.

Signed-off-by: default avatarWei Fang <wei.fang@nxp.com>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 4511acd9

arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts

+52 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ / { 
	compatible = "fsl,imx95-19x19-evk", "fsl,imx95";



	aliases {

		ethernet0 = &enetc_port0;

		gpio0 = &gpio1;

		gpio1 = &gpio2;

		gpio2 = &gpio3;
@@ -193,6 +194,14 @@ sound-wm8962 { 
	};

};



&enetc_port0 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enetc0>;

	phy-handle = <&ethphy0>;

	phy-mode = "rgmii-id";

	status = "okay";

};



&flexspi1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_flexspi1>;
@@ -338,6 +347,25 @@ &mu7 { 
	status = "okay";

};



&netcmix_blk_ctrl {

	status = "okay";

};



&netc_blk_ctrl {

	status = "okay";

};



&netc_emdio {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_emdio>;

	status = "okay";



	ethphy0: ethernet-phy@1 {

		reg = <1>;

		realtek,clkout-disable;

	};

};



&pcie0 {

	pinctrl-0 = <&pinctrl_pcie0>;

	pinctrl-names = "default";
@@ -429,6 +457,30 @@ &wdog3 { 
};



&scmi_iomuxc {

	pinctrl_emdio: emdiogrp{

		fsl,pins = <

			IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x57e

			IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x97e

		>;

	};



	pinctrl_enetc0: enetc0grp {

		fsl,pins = <

			IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x57e

			IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x57e

			IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x57e

			IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x57e

			IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e

			IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK	0x58e

			IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e

			IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK	0x58e

			IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e

			IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e

			IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e

			IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e

		>;

	};



	pinctrl_flexspi1: flexspi1grp {

		fsl,pins = <

			IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B			0x3fe