Commit 038c5323 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: Update P010 scaling cap 



[Why]
Keep the same as previous APU and also insert clock dump

Reviewed-by: default avatarOvidiu Bunea <ovidiu.bunea@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2254ab45

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+12 −13
Original line number Diff line number Diff line
@@ -384,19 +384,6 @@ static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base) 
	dcn35_smu_enable_pme_wa(clk_mgr);

}



void dcn35_init_clocks(struct clk_mgr *clk_mgr)

{

	uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;



	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));



	// Assumption is that boot state always supports pstate

	clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk;	// restore ref_dtbclk

	clk_mgr->clks.p_state_change_support = true;

	clk_mgr->clks.prev_p_state_change_support = true;

	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

	clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;

}



bool dcn35_are_clock_states_equal(struct dc_clocks *a,

		struct dc_clocks *b)
@@ -421,7 +408,19 @@ static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs 
		struct clk_mgr_dcn35 *clk_mgr)

{

}

void dcn35_init_clocks(struct clk_mgr *clk_mgr)

{

	uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;



	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));



	// Assumption is that boot state always supports pstate

	clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk;	// restore ref_dtbclk

	clk_mgr->clks.p_state_change_support = true;

	clk_mgr->clks.prev_p_state_change_support = true;

	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;

	clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;

}

static struct clk_bw_params dcn35_bw_params = {

	.vram_type = Ddr4MemType,

	.num_channels = 1,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -701,7 +701,7 @@ static const struct dc_plane_cap plane_cap = { 


	// 6:1 downscaling ratio: 1000/6 = 166.666

	.max_downscale_factor = {

			.argb8888 = 167,

			.argb8888 = 250,

			.nv12 = 167,

			.fp16 = 167

	},