Commit 03ff6d72 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/gfx10: set UNORD_DISPATCH in compute MQDs 



This needs to be set to 1 to avoid a potential deadlock in
the GC 10.x and newer.  On GC 9.x and older, this needs
to be set to 0.  This can lead to hangs in some mixed
graphics and compute workloads.  Updated firmware is also
required for AQL.

Reviewed-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent e7a8594c

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+1 −1
Original line number Diff line number Diff line
@@ -6589,7 +6589,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 
#ifdef __BIG_ENDIAN

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);

#endif

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH,

			    prop->allow_tunneling);

	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);

drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c

+1 −0
Original line number Diff line number Diff line
@@ -170,6 +170,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, 
	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT;

	m->cp_hqd_pq_control |=

			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;

	m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK;

	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);



	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);