Commit 041b1061 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Catalin Marinas:

 - Expand the speculative SSBS errata workaround to more CPUs

 - Ensure jump label changes are visible to all CPUs with a
   kick_all_cpus_sync() (and also enable jump label batching as part of
   the fix)

 - The shadow call stack sanitiser is currently incompatible with Rust,
   make CONFIG_RUST conditional on !CONFIG_SHADOW_CALL_STACK

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: jump_label: Ensure patched jump_labels are visible to all CPUs
  rust: SHADOW_CALL_STACK is incompatible with Rust
  arm64: errata: Expand speculative SSBS workaround (again)
  arm64: cputype: Add Cortex-A725 definitions
  arm64: cputype: Add Cortex-X1C definitions
parents 1c424629 cfb00a35

Documentation/arch/arm64/silicon-errata.rst

+18 −0
Original line number Diff line number Diff line
@@ -122,10 +122,18 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1490853        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #3324349        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1491015        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #3324348        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A78      | #3324344        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A78C     | #3324346,3324347| ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |
@@ -138,8 +146,14 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A720     | #3456091        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A725     | #3456106        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X1       | #1502854        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X1       | #3324344        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X1C      | #3324346        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |
@@ -160,6 +174,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #3324349        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2067961        | ARM64_ERRATUM_2067961       |
@@ -170,6 +186,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V1     | #1619801        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V1     | #3324341        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V2     | #3324336        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |

arch/arm64/Kconfig

+16 −6
Original line number Diff line number Diff line
@@ -1069,18 +1069,28 @@ config ARM64_ERRATUM_3117295 
	  If unsure, say Y.



config ARM64_ERRATUM_3194386

	bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"

	bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"

	default y

	help

	  This option adds the workaround for the following errata:



	  * ARM Cortex-A76 erratum 3324349

	  * ARM Cortex-A77 erratum 3324348

	  * ARM Cortex-A78 erratum 3324344

	  * ARM Cortex-A78C erratum 3324346

	  * ARM Cortex-A78C erratum 3324347

	  * ARM Cortex-A710 erratam 3324338

	  * ARM Cortex-A720 erratum 3456091

	  * ARM Cortex-A725 erratum 3456106

	  * ARM Cortex-X1 erratum 3324344

	  * ARM Cortex-X1C erratum 3324346

	  * ARM Cortex-X2 erratum 3324338

	  * ARM Cortex-X3 erratum 3324335

	  * ARM Cortex-X4 erratum 3194386

	  * ARM Cortex-X925 erratum 3324334

	  * ARM Neoverse-N1 erratum 3324349

	  * ARM Neoverse N2 erratum 3324339

	  * ARM Neoverse-V1 erratum 3324341

	  * ARM Neoverse V2 erratum 3324336

	  * ARM Neoverse-V3 erratum 3312417
@@ -1088,11 +1098,11 @@ config ARM64_ERRATUM_3194386 
	  subsequent speculative instructions, which may permit unexepected

	  speculative store bypassing.



	  Work around this problem by placing a speculation barrier after

	  kernel changes to SSBS. The presence of the SSBS special-purpose

	  register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such

	  that userspace will use the PR_SPEC_STORE_BYPASS prctl to change

	  SSBS.

	  Work around this problem by placing a Speculation Barrier (SB) or

	  Instruction Synchronization Barrier (ISB) after kernel changes to

	  SSBS. The presence of the SSBS special-purpose register is hidden

	  from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace

	  will use the PR_SPEC_STORE_BYPASS prctl to change SSBS.



	  If unsure, say Y.

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -86,12 +86,14 @@ 
#define ARM_CPU_PART_CORTEX_X2		0xD48

#define ARM_CPU_PART_NEOVERSE_N2	0xD49

#define ARM_CPU_PART_CORTEX_A78C	0xD4B

#define ARM_CPU_PART_CORTEX_X1C		0xD4C

#define ARM_CPU_PART_CORTEX_X3		0xD4E

#define ARM_CPU_PART_NEOVERSE_V2	0xD4F

#define ARM_CPU_PART_CORTEX_A720	0xD81

#define ARM_CPU_PART_CORTEX_X4		0xD82

#define ARM_CPU_PART_NEOVERSE_V3	0xD84

#define ARM_CPU_PART_CORTEX_X925	0xD85

#define ARM_CPU_PART_CORTEX_A725	0xD87



#define APM_CPU_PART_XGENE		0x000

#define APM_CPU_VAR_POTENZA		0x00
@@ -165,12 +167,14 @@ 
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)

#define MIDR_CORTEX_X1C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)

#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)

#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)

#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)

#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)

#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)

#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)

#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

arch/arm64/include/asm/jump_label.h

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include <linux/types.h>

#include <asm/insn.h>



#define HAVE_JUMP_LABEL_BATCH

#define JUMP_LABEL_NOP_SIZE		AARCH64_INSN_SIZE



#define JUMP_TABLE_ENTRY(key, label)			\

arch/arm64/kernel/cpu_errata.c

+10 −1
Original line number Diff line number Diff line
@@ -434,15 +434,24 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = { 


#ifdef CONFIG_ARM64_ERRATUM_3194386

static const struct midr_range erratum_spec_ssbs_list[] = {

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A76),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A77),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A78),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X1C),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),

	{}

};

#endif