Unverified Commit 04f08ef2 authored by Rob Herring (Arm)'s avatar Rob Herring (Arm) Committed by Arnd Bergmann
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arm/arm64: dts: arm: Use generic clock and regulator nodenames



With the recent defining of preferred naming for fixed clock and
regulator nodes, convert the Arm Ltd. boards to use the preferred
names. In the cases which had a unit-address, warnings about missing
"reg" property are fixed.

Signed-off-by: default avatarRob Herring (Arm) <robh@kernel.org>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: default avatarSudeep Holla <sudeep.holla@arm.com>
Link: https://lore.kernel.org/20240528191536.1444649-2-robh@kernel.org


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20240630-arm-dts-fixes-2-v1-1-a32ba57e5b1d@linaro.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 7f8165ee
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+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@

/ {
	/* Introduce a fixed regulator for the new ethernet controller */
	veth: fixedregulator@0 {
	veth: regulator-veth {
		compatible = "regulator-fixed";
		regulator-name = "veth";
		regulator-min-microvolt = <3300000>;
+3 −3
Original line number Diff line number Diff line
@@ -45,7 +45,7 @@ memory {
	};

	/* The voltage to the MMC card is hardwired at 3.3V */
	vmmc: fixedregulator@0 {
	vmmc: regulator-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "vmmc";
		regulator-min-microvolt = <3300000>;
@@ -59,7 +59,7 @@ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
		clock-frequency = <24000000>;
	};

	timclk: timclk@1M {
	timclk: clock-1000000 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <24>;
@@ -68,7 +68,7 @@ timclk: timclk@1M {
	};

	/* FIXME: this actually hangs off the PLL clocks */
	pclk: pclk@0 {
	pclk: clock-pclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
+2 −2
Original line number Diff line number Diff line
@@ -69,7 +69,7 @@ xtal24mhz: mclk: kmiclk: sspclk: uartclk: clock-24000000 {
		clock-frequency = <24000000>;
	};

	timclk: timclk@1M {
	timclk: clock-1000000 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <24>;
@@ -78,7 +78,7 @@ timclk: timclk@1M {
	};

	/* FIXME: this actually hangs off the PLL clocks */
	pclk: pclk@0 {
	pclk: clock-pclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
+3 −3
Original line number Diff line number Diff line
@@ -169,13 +169,13 @@ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
		clock-frequency = <24000000>;
	};

	refclk32khz: refclk32khz {
	refclk32khz: clock-32768 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
	};

	timclk: timclk@1M {
	timclk: clock-1000000 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <24>;
@@ -184,7 +184,7 @@ timclk: timclk@1M {
	};

	/* FIXME: this actually hangs off the PLL clocks */
	pclk: pclk@0 {
	pclk: clock-pclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
+3 −3
Original line number Diff line number Diff line
@@ -68,13 +68,13 @@ xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 {
		clock-frequency = <24000000>;
	};

	refclk32khz: refclk32khz {
	refclk32khz: clock-32768 {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <32768>;
	};

	timclk: timclk@1M {
	timclk: clock-1000000 {
		#clock-cells = <0>;
		compatible = "fixed-factor-clock";
		clock-div = <24>;
@@ -83,7 +83,7 @@ timclk: timclk@1M {
	};

	/* FIXME: this actually hangs off the PLL clocks */
	pclk: pclk@0 {
	pclk: clock-pclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
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