Commit 0569af48 authored by Samuel Holland's avatar Samuel Holland Committed by Linus Walleij
Browse files

pinctrl: sunxi: Add driver for Allwinner D1 



This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the number of functions per pin from 8 to 16, taking advantage of all 4
bits in the mux config field (so far, only functions 0-8 and 14-15 are
used). This increases the maximum possible number of functions.

Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Tested-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.org


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 622b681e

drivers/pinctrl/sunxi/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -81,6 +81,11 @@ config PINCTRL_SUN9I_A80_R 
	default MACH_SUN9I

	select PINCTRL_SUNXI



config PINCTRL_SUN20I_D1

	bool "Support for the Allwinner D1 PIO"

	default MACH_SUN8I || (RISCV && ARCH_SUNXI)

	select PINCTRL_SUNXI



config PINCTRL_SUN50I_A64

	bool "Support for the Allwinner A64 PIO"

	default ARM64 && ARCH_SUNXI

drivers/pinctrl/sunxi/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o 
obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o

obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o

obj-$(CONFIG_PINCTRL_SUN8I_V3S)		+= pinctrl-sun8i-v3s.o

obj-$(CONFIG_PINCTRL_SUN20I_D1)		+= pinctrl-sun20i-d1.o

obj-$(CONFIG_PINCTRL_SUN50I_H5)		+= pinctrl-sun50i-h5.o

obj-$(CONFIG_PINCTRL_SUN50I_H6)		+= pinctrl-sun50i-h6.o

obj-$(CONFIG_PINCTRL_SUN50I_H6_R)	+= pinctrl-sun50i-h6-r.o

drivers/pinctrl/sunxi/pinctrl-sun20i-d1.c

0 → 100644
+840 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/pinctrl/sunxi/pinctrl-sunxi.c

+11 −5
Original line number Diff line number Diff line
@@ -1297,11 +1297,11 @@ static int sunxi_pinctrl_build_state(struct platform_device *pdev) 


	/*

	 * Find an upper bound for the maximum number of functions: in

	 * the worst case we have gpio_in, gpio_out, irq and up to four

	 * the worst case we have gpio_in, gpio_out, irq and up to seven

	 * special functions per pin, plus one entry for the sentinel.

	 * We'll reallocate that later anyway.

	 */

	pctl->functions = kcalloc(4 * pctl->ngroups + 4,

	pctl->functions = kcalloc(7 * pctl->ngroups + 4,

				  sizeof(*pctl->functions),

				  GFP_KERNEL);

	if (!pctl->functions)
@@ -1494,9 +1494,15 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev, 
	pctl->dev = &pdev->dev;

	pctl->desc = desc;

	pctl->variant = variant;

	if (pctl->variant >= PINCTRL_SUN20I_D1) {

		pctl->bank_mem_size = D1_BANK_MEM_SIZE;

		pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;

		pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;

	} else {

		pctl->bank_mem_size = BANK_MEM_SIZE;

		pctl->pull_regs_offset = PULL_REGS_OFFSET;

		pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH;

	}



	pctl->irq_array = devm_kcalloc(&pdev->dev,

				       IRQ_PER_BANK * pctl->desc->irq_banks,

drivers/pinctrl/sunxi/pinctrl-sunxi.h

+6 −0
Original line number Diff line number Diff line
@@ -44,6 +44,10 @@ 
#define PULL_REGS_OFFSET	0x1c

#define PULL_FIELD_WIDTH	2



#define D1_BANK_MEM_SIZE	0x30

#define D1_DLEVEL_FIELD_WIDTH	4

#define D1_PULL_REGS_OFFSET	0x24



#define PINS_PER_BANK		32



#define IRQ_PER_BANK		32
@@ -88,6 +92,8 @@ 
#define PINCTRL_SUN8I_R40	BIT(8)

#define PINCTRL_SUN8I_V3	BIT(9)

#define PINCTRL_SUN8I_V3S	BIT(10)

/* Variants below here have an updated register layout. */

#define PINCTRL_SUN20I_D1	BIT(11)



#define PIO_POW_MOD_SEL_REG	0x340

#define PIO_POW_MOD_CTL_REG	0x344